1 /**
2  *
3  * \file
4  *
5  * \brief KS8851SNL registers definitions.
6  *
7  * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
8  *
9  * \asf_license_start
10  *
11  * \page License
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions are met:
15  *
16  * 1. Redistributions of source code must retain the above copyright notice,
17  *    this list of conditions and the following disclaimer.
18  *
19  * 2. Redistributions in binary form must reproduce the above copyright notice,
20  *    this list of conditions and the following disclaimer in the documentation
21  *    and/or other materials provided with the distribution.
22  *
23  * 3. The name of Atmel may not be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * 4. This software may only be redistributed and used in connection with an
27  *    Atmel microcontroller product.
28  *
29  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
30  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
32  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
33  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
38  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39  * POSSIBILITY OF SUCH DAMAGE.
40  *
41  * \asf_license_stop
42  *
43  */
44 
45 /*
46  * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
47  */
48 
49 #ifndef KSZ8851SNL_REG_H_INCLUDED
50 #define KSZ8851SNL_REG_H_INCLUDED
51 
52 #define REG_ADDR_MASK                 ( 0x3F0 ) /* Register address mask */
53 #define OPCODE_MASK                   ( 3 << 14 )
54 #define CMD_READ                      ( 0 << 14 )
55 #define CMD_WRITE                     ( 1 << 14 )
56 #define FIFO_READ                     ( 0x80 )
57 #define FIFO_WRITE                    ( 0xC0 )
58 
59 /*
60  * MAC Registers
61  * (Offset 0x00 - 0x25)
62  */
63 #define REG_BUS_ERROR_STATUS          ( 0x06 )   /* BESR */
64 #define   BUS_ERROR_IBEC              ( 0x8000 )
65 #define   BUS_ERROR_IBECV_MASK        ( 0x7800 ) /* Default IPSec clock at 166Mhz */
66 
67 #define REG_CHIP_CFG_STATUS           ( 0x08 )   /* CCFG */
68 #define   LITTLE_ENDIAN_BUS_MODE      ( 0x0400 ) /* Bus in little endian mode */
69 #define   EEPROM_PRESENCE             ( 0x0200 ) /* External EEPROM is used */
70 #define   SPI_BUS_MODE                ( 0x0100 ) /* In SPI bus mode */
71 #define   DATA_BUS_8BIT               ( 0x0080 ) /* In 8-bit bus mode operation */
72 #define   DATA_BUS_16BIT              ( 0x0040 ) /* In 16-bit bus mode operation */
73 #define   DATA_BUS_32BIT              ( 0x0020 ) /* In 32-bit bus mode operation */
74 #define   MULTIPLEX_MODE              ( 0x0010 ) /* Data and address bus are shared */
75 #define   CHIP_PACKAGE_128PIN         ( 0x0008 ) /* 128-pin package */
76 #define   CHIP_PACKAGE_80PIN          ( 0x0004 ) /* 80-pin package */
77 #define   CHIP_PACKAGE_48PIN          ( 0x0002 ) /* 48-pin package */
78 #define   CHIP_PACKAGE_32PIN          ( 0x0001 ) /* 32-pin package for SPI host interface only */
79 
80 #define REG_MAC_ADDR_0                ( 0x10 )   /* MARL */
81 #define REG_MAC_ADDR_1                ( 0x11 )   /* MARL */
82 #define REG_MAC_ADDR_2                ( 0x12 )   /* MARM */
83 #define REG_MAC_ADDR_3                ( 0x13 )   /* MARM */
84 #define REG_MAC_ADDR_4                ( 0x14 )   /* MARH */
85 #define REG_MAC_ADDR_5                ( 0x15 )   /* MARH */
86 
87 #define REG_BUS_CLOCK_CTRL            ( 0x20 )   /* OBCR */
88 #define   BUS_CLOCK_166               ( 0x0004 ) /* 166 MHz on-chip bus clock (default is 125MHz) */
89 #define   BUS_CLOCK_DIVIDEDBY_5       ( 0x0003 ) /* Bus clock divided by 5 */
90 #define   BUS_CLOCK_DIVIDEDBY_3       ( 0x0002 ) /* Bus clock divided by 3 */
91 #define   BUS_CLOCK_DIVIDEDBY_2       ( 0x0001 ) /* Bus clock divided by 2 */
92 #define   BUS_CLOCK_DIVIDEDBY_1       ( 0x0000 ) /* Bus clock divided by 1 */
93 #define   BUS_CLOCK_DIVIDED_MASK      ( 0x0003 ) /* Bus clock divider mask */
94 
95 #define   BUS_SPEED_166_MHZ           ( 0x0004 ) /* Set bus speed to 166 MHz */
96 #define   BUS_SPEED_125_MHZ           ( 0x0000 ) /* Set bus speed to 125 MHz */
97 #define   BUS_SPEED_83_MHZ            ( 0x0005 ) /* Set bus speed to 83 MHz (166/2)*/
98 #define   BUS_SPEED_62_5_MHZ          ( 0x0001 ) /* Set bus speed to 62.5 MHz (125/2) */
99 #define   BUS_SPEED_53_3_MHZ          ( 0x0006 ) /* Set bus speed to 53.3 MHz (166/3) */
100 #define   BUS_SPEED_41_7_MHZ          ( 0x0002 ) /* Set bus speed to 41.67 MHz (125/3) */
101 #define   BUS_SPEED_33_2_MHZ          ( 0x0007 ) /* Set bus speed to 33.2 MHz (166/5) */
102 #define   BUS_SPEED_25_MHZ            ( 0x0003 ) /* Set bus speed to 25 MHz (125/5) */
103 
104 #define REG_EEPROM_CTRL               ( 0x22 )   /* EEPCR */
105 #define   EEPROM_ACCESS_ENABLE        ( 0x0010 ) /* Enable software to access EEPROM through bit 3 to bit 0 */
106 #define   EEPROM_DATA_IN              ( 0x0008 ) /* Data receive from EEPROM (EEDI pin) */
107 #define   EEPROM_DATA_OUT             ( 0x0004 ) /* Data transmit to EEPROM (EEDO pin) */
108 #define   EEPROM_SERIAL_CLOCK         ( 0x0002 ) /* Serial clock (EESK pin) */
109 #define   EEPROM_CHIP_SELECT          ( 0x0001 ) /* EEPROM chip select (EECS pin) */
110 
111 #define REG_MEM_BIST_INFO             ( 0x24 )   /* MBIR */
112 #define   TX_MEM_TEST_FINISHED        ( 0x1000 ) /* TX memeory BIST test finish */
113 #define   TX_MEM_TEST_FAILED          ( 0x0800 ) /* TX memory BIST test fail */
114 #define   TX_MEM_TEST_FAILED_COUNT    ( 0x0700 ) /* TX memory BIST test fail count */
115 #define   RX_MEM_TEST_FINISHED        ( 0x0010 ) /* RX memory BIST test finish */
116 #define   RX_MEM_TEST_FAILED          ( 0x0008 ) /* RX memory BIST test fail */
117 #define   RX_MEM_TEST_FAILED_COUNT    ( 0x0003 ) /* RX memory BIST test fail count */
118 
119 #define REG_RESET_CTRL                ( 0x26 )   /* GRR */
120 #define   QMU_SOFTWARE_RESET          ( 0x0002 ) /* QMU soft reset (clear TxQ, RxQ) */
121 #define   GLOBAL_SOFTWARE_RESET       ( 0x0001 ) /* Global soft reset (PHY, MAC, QMU) */
122 
123 /*
124  * Wake On Lan Control Registers
125  * (Offset 0x2A - 0x6B)
126  */
127 #define REG_WOL_CTRL                  ( 0x2A )   /* WFCR */
128 #define   WOL_MAGIC_ENABLE            ( 0x0080 ) /* Enable the magic packet pattern detection */
129 #define   WOL_FRAME3_ENABLE           ( 0x0008 ) /* Enable the wake up frame 3 pattern detection */
130 #define   WOL_FRAME2_ENABLE           ( 0x0004 ) /* Enable the wake up frame 2 pattern detection */
131 #define   WOL_FRAME1_ENABLE           ( 0x0002 ) /* Enable the wake up frame 1 pattern detection */
132 #define   WOL_FRAME0_ENABLE           ( 0x0001 ) /* Enable the wake up frame 0 pattern detection */
133 
134 #define REG_WOL_FRAME0_CRC0           ( 0x30 )   /* WF0CRC0 */
135 #define REG_WOL_FRAME0_CRC1           ( 0x32 )   /* WF0CRC1 */
136 #define REG_WOL_FRAME0_BYTE_MASK0     ( 0x34 )   /* WF0BM0 */
137 #define REG_WOL_FRAME0_BYTE_MASK1     ( 0x36 )   /* WF0BM1 */
138 #define REG_WOL_FRAME0_BYTE_MASK2     ( 0x38 )   /* WF0BM2 */
139 #define REG_WOL_FRAME0_BYTE_MASK3     ( 0x3A )   /* WF0BM3 */
140 
141 #define REG_WOL_FRAME1_CRC0           ( 0x40 )   /* WF1CRC0 */
142 #define REG_WOL_FRAME1_CRC1           ( 0x42 )   /* WF1CRC1 */
143 #define REG_WOL_FRAME1_BYTE_MASK0     ( 0x44 )   /* WF1BM0 */
144 #define REG_WOL_FRAME1_BYTE_MASK1     ( 0x46 )   /* WF1BM1 */
145 #define REG_WOL_FRAME1_BYTE_MASK2     ( 0x48 )   /* WF1BM2 */
146 #define REG_WOL_FRAME1_BYTE_MASK3     ( 0x4A )   /* WF1BM3 */
147 
148 #define REG_WOL_FRAME2_CRC0           ( 0x50 )   /* WF2CRC0 */
149 #define REG_WOL_FRAME2_CRC1           ( 0x52 )   /* WF2CRC1 */
150 #define REG_WOL_FRAME2_BYTE_MASK0     ( 0x54 )   /* WF2BM0 */
151 #define REG_WOL_FRAME2_BYTE_MASK1     ( 0x56 )   /* WF2BM1 */
152 #define REG_WOL_FRAME2_BYTE_MASK2     ( 0x58 )   /* WF2BM2 */
153 #define REG_WOL_FRAME2_BYTE_MASK3     ( 0x5A )   /* WF2BM3 */
154 
155 #define REG_WOL_FRAME3_CRC0           ( 0x60 )   /* WF3CRC0 */
156 #define REG_WOL_FRAME3_CRC1           ( 0x62 )   /* WF3CRC1 */
157 #define REG_WOL_FRAME3_BYTE_MASK0     ( 0x64 )   /* WF3BM0 */
158 #define REG_WOL_FRAME3_BYTE_MASK1     ( 0x66 )   /* WF3BM1 */
159 #define REG_WOL_FRAME3_BYTE_MASK2     ( 0x68 )   /* WF3BM2 */
160 #define REG_WOL_FRAME3_BYTE_MASK3     ( 0x6A )   /* WF3BM3 */
161 
162 /*
163  * Transmit/Receive Control Registers
164  * (Offset 0x70 - 0x9F)
165  */
166 
167 /* Transmit Frame Header */
168 #define REG_QDR_DUMMY                    ( 0x00 )   /* Dummy address to access QMU RxQ, TxQ */
169 #define   TX_CTRL_INTERRUPT_ON           ( 0x8000 ) /* Transmit Interrupt on Completion */
170 
171 #define REG_TX_CTRL                      ( 0x70 )   /* TXCR */
172 #define   TX_CTRL_ICMP_CHECKSUM          ( 0x0100 ) /* Enable ICMP frame checksum generation */
173 #define   TX_CTRL_UDP_CHECKSUM           ( 0x0080 ) /* Enable UDP frame checksum generation */
174 #define   TX_CTRL_TCP_CHECKSUM           ( 0x0040 ) /* Enable TCP frame checksum generation */
175 #define   TX_CTRL_IP_CHECKSUM            ( 0x0020 ) /* Enable IP frame checksum generation */
176 #define   TX_CTRL_FLUSH_QUEUE            ( 0x0010 ) /* Clear transmit queue, reset tx frame pointer */
177 #define   TX_CTRL_FLOW_ENABLE            ( 0x0008 ) /* Enable transmit flow control */
178 #define   TX_CTRL_PAD_ENABLE             ( 0x0004 ) /* Enable adding a padding to a packet shorter than 64 bytes */
179 #define   TX_CTRL_CRC_ENABLE             ( 0x0002 ) /* Enable adding a CRC to the end of transmit frame */
180 #define   TX_CTRL_ENABLE                 ( 0x0001 ) /* Enable transmit */
181 
182 #define REG_TX_STATUS                    ( 0x72 )   /* TXSR */
183 #define   TX_STAT_LATE_COL               ( 0x2000 ) /* Transmit late collision occurs */
184 #define   TX_STAT_MAX_COL                ( 0x1000 ) /* Transmit maximum collision is reached */
185 #define   TX_FRAME_ID_MASK               ( 0x003F ) /* Transmit frame ID mask */
186 #define   TX_STAT_ERRORS                 ( TX_STAT_MAX_COL | TX_STAT_LATE_COL )
187 
188 #define REG_RX_CTRL1                     ( 0x74 )   /* RXCR1 */
189 #define   RX_CTRL_FLUSH_QUEUE            ( 0x8000 ) /* Clear receive queue, reset rx frame pointer */
190 #define   RX_CTRL_UDP_CHECKSUM           ( 0x4000 ) /* Enable UDP frame checksum verification */
191 #define   RX_CTRL_TCP_CHECKSUM           ( 0x2000 ) /* Enable TCP frame checksum verification */
192 #define   RX_CTRL_IP_CHECKSUM            ( 0x1000 ) /* Enable IP frame checksum verification */
193 #define   RX_CTRL_MAC_FILTER             ( 0x0800 ) /* Receive with address that pass MAC address filtering */
194 #define   RX_CTRL_FLOW_ENABLE            ( 0x0400 ) /* Enable receive flow control */
195 #define   RX_CTRL_BAD_PACKET             ( 0x0200 ) /* Enable receive CRC error frames */
196 #define   RX_CTRL_MULTICAST              ( 0x0100 ) /* Receive multicast frames that pass the CRC hash filtering */
197 #define   RX_CTRL_BROADCAST              ( 0x0080 ) /* Receive all the broadcast frames */
198 #define   RX_CTRL_ALL_MULTICAST          ( 0x0040 ) /* Receive all the multicast frames (including broadcast frames) */
199 #define   RX_CTRL_UNICAST                ( 0x0020 ) /* Receive unicast frames that match the device MAC address */
200 #define   RX_CTRL_PROMISCUOUS            ( 0x0010 ) /* Receive all incoming frames, regardless of frame's DA */
201 #define   RX_CTRL_STRIP_CRC              ( 0x0008 ) /* Enable strip CRC on the received frames */
202 #define   RX_CTRL_INVERSE_FILTER         ( 0x0002 ) /* Receive with address check in inverse filtering mode */
203 #define   RX_CTRL_ENABLE                 ( 0x0001 ) /* Enable receive */
204 
205 /* Address filtering scheme mask */
206 #define RX_CTRL_FILTER_MASK              ( RX_CTRL_INVERSE_FILTER | RX_CTRL_PROMISCUOUS | RX_CTRL_MULTICAST | RX_CTRL_MAC_FILTER )
207 
208 #define REG_RX_CTRL2                     ( 0x76 )   /* RXCR2 */
209 #define   RX_CTRL_IPV6_UDP_NOCHECKSUM    ( 0x0010 ) /* No checksum generation and verification if IPv6 UDP is fragment */
210 #define   RX_CTRL_IPV6_UDP_CHECKSUM      ( 0x0008 ) /* Receive pass IPv6 UDP frame with UDP checksum is zero */
211 #define   RX_CTRL_UDP_LITE_CHECKSUM      ( 0x0004 ) /* Enable UDP Lite frame checksum generation and verification */
212 #define   RX_CTRL_ICMP_CHECKSUM          ( 0x0002 ) /* Enable ICMP frame checksum verification */
213 #define   RX_CTRL_BLOCK_MAC              ( 0x0001 ) /* Receive drop frame if the SA is same as device MAC address */
214 #define   RX_CTRL_BURST_LEN_MASK         ( 0x00e0 ) /* SRDBL SPI Receive Data Burst Length */
215 #define   RX_CTRL_BURST_LEN_4            ( 0x0000 )
216 #define   RX_CTRL_BURST_LEN_8            ( 0x0020 )
217 #define   RX_CTRL_BURST_LEN_16           ( 0x0040 )
218 #define   RX_CTRL_BURST_LEN_32           ( 0x0060 )
219 #define   RX_CTRL_BURST_LEN_FRAME        ( 0x0080 )
220 
221 #define REG_TX_MEM_INFO                  ( 0x78 )   /* TXMIR */
222 #define   TX_MEM_AVAILABLE_MASK          ( 0x1FFF ) /* The amount of memory available in TXQ */
223 
224 #define REG_RX_FHR_STATUS                ( 0x7C )   /* RXFHSR */
225 #define   RX_VALID                       ( 0x8000 ) /* Frame in the receive packet memory is valid */
226 #define   RX_ICMP_ERROR                  ( 0x2000 ) /* ICMP checksum field doesn't match */
227 #define   RX_IP_ERROR                    ( 0x1000 ) /* IP checksum field doesn't match */
228 #define   RX_TCP_ERROR                   ( 0x0800 ) /* TCP checksum field doesn't match */
229 #define   RX_UDP_ERROR                   ( 0x0400 ) /* UDP checksum field doesn't match */
230 #define   RX_BROADCAST                   ( 0x0080 ) /* Received frame is a broadcast frame */
231 #define   RX_MULTICAST                   ( 0x0040 ) /* Received frame is a multicast frame */
232 #define   RX_UNICAST                     ( 0x0020 ) /* Received frame is a unicast frame */
233 #define   RX_PHY_ERROR                   ( 0x0010 ) /* Received frame has runt error */
234 #define   RX_FRAME_ETHER                 ( 0x0008 ) /* Received frame is an Ethernet-type frame */
235 #define   RX_TOO_LONG                    ( 0x0004 ) /* Received frame length exceeds max size 0f 2048 bytes */
236 #define   RX_RUNT_ERROR                  ( 0x0002 ) /* Received frame was damaged by a collision */
237 #define   RX_BAD_CRC                     ( 0x0001 ) /* Received frame has a CRC error */
238 #define   RX_ERRORS                                             \
239     ( RX_BAD_CRC | RX_TOO_LONG | RX_RUNT_ERROR | RX_PHY_ERROR | \
240       RX_ICMP_ERROR | RX_IP_ERROR | RX_TCP_ERROR | RX_UDP_ERROR )
241 
242 #define REG_RX_FHR_BYTE_CNT              ( 0x7E )   /* RXFHBCR */
243 #define   RX_BYTE_CNT_MASK               ( 0x0FFF ) /* Received frame byte size mask */
244 
245 #define REG_TXQ_CMD                      ( 0x80 )   /* TXQCR */
246 #define   TXQ_AUTO_ENQUEUE               ( 0x0004 ) /* Enable enqueue tx frames from tx buffer automatically */
247 #define   TXQ_MEM_AVAILABLE_INT          ( 0x0002 ) /* Enable generate interrupt when tx memory is available */
248 #define   TXQ_ENQUEUE                    ( 0x0001 ) /* Enable enqueue tx frames one frame at a time */
249 
250 #define REG_RXQ_CMD                      ( 0x82 )   /* RXQCR */
251 #define   RXQ_STAT_TIME_INT              ( 0x1000 ) /* RX interrupt is occurred by timer duration */
252 #define   RXQ_STAT_BYTE_CNT_INT          ( 0x0800 ) /* RX interrupt is occurred by byte count threshold */
253 #define   RXQ_STAT_FRAME_CNT_INT         ( 0x0400 ) /* RX interrupt is occurred by frame count threshold */
254 #define   RXQ_TWOBYTE_OFFSET             ( 0x0200 ) /* Enable adding 2-byte before frame header for IP aligned with DWORD */
255 #define   RXQ_TIME_INT                   ( 0x0080 ) /* Enable RX interrupt by timer duration */
256 #define   RXQ_BYTE_CNT_INT               ( 0x0040 ) /* Enable RX interrupt by byte count threshold */
257 #define   RXQ_FRAME_CNT_INT              ( 0x0020 ) /* Enable RX interrupt by frame count threshold */
258 #define   RXQ_AUTO_DEQUEUE               ( 0x0010 ) /* Enable release rx frames from rx buffer automatically */
259 #define   RXQ_START                      ( 0x0008 ) /* Start QMU transfer operation */
260 #define   RXQ_CMD_FREE_PACKET            ( 0x0001 ) /* Manual dequeue (release the current frame from RxQ) */
261 
262 #define   RXQ_CMD_CNTL                   ( RXQ_FRAME_CNT_INT | RXQ_AUTO_DEQUEUE )
263 
264 #define REG_TX_ADDR_PTR                  ( 0x84 )   /* TXFDPR */
265 #define REG_RX_ADDR_PTR                  ( 0x86 )   /* RXFDPR */
266 #define   ADDR_PTR_AUTO_INC              ( 0x4000 ) /* Enable Frame data pointer increments automatically */
267 #define   ADDR_PTR_MASK                  ( 0x03ff ) /* Address pointer mask */
268 
269 #define REG_RX_TIME_THRES                ( 0x8C )   /* RXDTTR */
270 #define   RX_TIME_THRESHOLD_MASK         ( 0xFFFF ) /* Set receive timer duration threshold */
271 
272 #define REG_RX_BYTE_CNT_THRES            ( 0x8E )   /* RXDBCTR */
273 #define   RX_BYTE_THRESHOLD_MASK         ( 0xFFFF ) /* Set receive byte count threshold */
274 
275 #define REG_INT_MASK                     ( 0x90 )   /* IER */
276 #define   INT_PHY                        ( 0x8000 ) /* Enable link change interrupt */
277 #define   INT_TX                         ( 0x4000 ) /* Enable transmit done interrupt */
278 #define   INT_RX                         ( 0x2000 ) /* Enable receive interrupt */
279 #define   INT_RX_OVERRUN                 ( 0x0800 ) /* Enable receive overrun interrupt */
280 #define   INT_TX_STOPPED                 ( 0x0200 ) /* Enable transmit process stopped interrupt */
281 #define   INT_RX_STOPPED                 ( 0x0100 ) /* Enable receive process stopped interrupt */
282 #define   INT_TX_SPACE                   ( 0x0040 ) /* Enable transmit space available interrupt */
283 #define   INT_RX_WOL_FRAME               ( 0x0020 ) /* Enable WOL on receive wake-up frame detect interrupt */
284 #define   INT_RX_WOL_MAGIC               ( 0x0010 ) /* Enable WOL on receive magic packet detect interrupt */
285 #define   INT_RX_WOL_LINKUP              ( 0x0008 ) /* Enable WOL on link up detect interrupt */
286 #define   INT_RX_WOL_ENERGY              ( 0x0004 ) /* Enable WOL on energy detect interrupt */
287 #define   INT_RX_SPI_ERROR               ( 0x0002 ) /* Enable receive SPI bus error interrupt */
288 #define   INT_RX_WOL_DELAY_ENERGY        ( 0x0001 ) /* Enable WOL on delay energy detect interrupt */
289 #define   INT_MASK                       ( INT_RX | INT_TX | INT_PHY )
290 
291 #define REG_INT_STATUS                   ( 0x92 )   /* ISR */
292 
293 #define REG_RX_FRAME_CNT_THRES           ( 0x9C )   /* RXFCTFC */
294 #define   RX_FRAME_CNT_MASK              ( 0xFF00 ) /* Received frame count mask */
295 #define   RX_FRAME_THRESHOLD_MASK        ( 0x00FF ) /* Set receive frame count threshold mask */
296 
297 #define REG_TX_TOTAL_FRAME_SIZE          ( 0x9E )   /* TXNTFSR */
298 #define   TX_TOTAL_FRAME_SIZE_MASK       ( 0xFFFF ) /* Set next total tx frame size mask */
299 
300 /*
301  * MAC Address Hash Table Control Registers
302  * (Offset 0xA0 - 0xA7)
303  */
304 #define REG_MAC_HASH_0                   ( 0xA0 ) /* MAHTR0 */
305 #define REG_MAC_HASH_1                   ( 0xA1 )
306 
307 #define REG_MAC_HASH_2                   ( 0xA2 ) /* MAHTR1 */
308 #define REG_MAC_HASH_3                   ( 0xA3 )
309 
310 #define REG_MAC_HASH_4                   ( 0xA4 ) /* MAHTR2 */
311 #define REG_MAC_HASH_5                   ( 0xA5 )
312 
313 #define REG_MAC_HASH_6                   ( 0xA6 ) /* MAHTR3 */
314 #define REG_MAC_HASH_7                   ( 0xA7 )
315 
316 /*
317  * QMU Receive Queue Watermark Control Registers
318  * (Offset 0xB0 - 0xB5)
319  */
320 #define REG_RX_LOW_WATERMARK             ( 0xB0 )   /* FCLWR */
321 #define   RX_LOW_WATERMARK_MASK          ( 0x0FFF ) /* Set QMU RxQ low watermark mask */
322 
323 #define REG_RX_HIGH_WATERMARK            ( 0xB2 )   /* FCHWR */
324 #define   RX_HIGH_WATERMARK_MASK         ( 0x0FFF ) /* Set QMU RxQ high watermark mask */
325 
326 #define REG_RX_OVERRUN_WATERMARK         ( 0xB4 )   /* FCOWR */
327 #define   RX_OVERRUN_WATERMARK_MASK      ( 0x0FFF ) /* Set QMU RxQ overrun watermark mask */
328 
329 /*
330  * Global Control Registers
331  * (Offset 0xC0 - 0xD3)
332  */
333 #define REG_CHIP_ID                      ( 0xC0 )   /* CIDER */
334 #define   CHIP_ID_MASK                   ( 0xFFF0 ) /* Family ID and chip ID mask */
335 #define   REVISION_MASK                  ( 0x000E ) /* Chip revision mask */
336 #define   CHIP_ID_SHIFT                  ( 4 )
337 #define   REVISION_SHIFT                 ( 1 )
338 #define   CHIP_ID_8851_16                ( 0x8870 ) /* KS8851-16/32MQL chip ID */
339 
340 #define REG_LED_CTRL                     ( 0xC6 )   /* CGCR */
341 #define   LED_CTRL_SEL1                  ( 0x8000 ) /* Select LED3/LED2/LED1/LED0 indication */
342 #define   LED_CTRL_SEL0                  ( 0x0200 ) /* Select LED3/LED2/LED1/LED0 indication */
343 
344 #define REG_IND_IACR                     ( 0xC8 )   /* IACR */
345 #define   TABLE_READ                     ( 0x1000 ) /* Indirect read */
346 #define   TABLE_MIB                      ( 0x0C00 ) /* Select MIB counter table */
347 #define   TABLE_ENTRY_MASK               ( 0x001F ) /* Set table entry to access */
348 
349 #define REG_IND_DATA_LOW                 ( 0xD0 )   /* IADLR */
350 #define REG_IND_DATA_HIGH                ( 0xD2 )   /* IADHR */
351 
352 /*
353  * Power Management Control Registers
354  * (Offset 0xD4 - 0xD7)
355  */
356 #define REG_POWER_CNTL                   ( 0xD4 )   /* PMECR */
357 #define   PME_DELAY_ENABLE               ( 0x4000 ) /* Enable the PME output pin assertion delay */
358 #define   PME_ACTIVE_HIGHT               ( 0x1000 ) /* PME output pin is active high */
359 #define   PME_FROM_WKFRAME               ( 0x0800 ) /* PME asserted when wake-up frame is detected */
360 #define   PME_FROM_MAGIC                 ( 0x0400 ) /* PME asserted when magic packet is detected */
361 #define   PME_FROM_LINKUP                ( 0x0200 ) /* PME asserted when link up is detected */
362 #define   PME_FROM_ENERGY                ( 0x0100 ) /* PME asserted when energy is detected */
363 #define   PME_EVENT_MASK                 ( 0x0F00 ) /* PME asserted event mask */
364 #define   WAKEUP_AUTO_ENABLE             ( 0x0080 ) /* Enable auto wake-up in energy mode */
365 #define   WAKEUP_NORMAL_AUTO_ENABLE      ( 0x0040 ) /* Enable auto goto normal mode from energy detecion mode */
366 #define   WAKEUP_FROM_WKFRAME            ( 0x0020 ) /* Wake-up from wake-up frame event detected */
367 #define   WAKEUP_FROM_MAGIC              ( 0x0010 ) /* Wake-up from magic packet event detected */
368 #define   WAKEUP_FROM_LINKUP             ( 0x0008 ) /* Wake-up from link up event detected */
369 #define   WAKEUP_FROM_ENERGY             ( 0x0004 ) /* Wake-up from energy event detected */
370 #define   WAKEUP_EVENT_MASK              ( 0x003C ) /* Wake-up event mask */
371 #define   POWER_STATE_D1                 ( 0x0003 ) /* Power saving mode */
372 #define   POWER_STATE_D3                 ( 0x0002 ) /* Power down mode */
373 #define   POWER_STATE_D2                 ( 0x0001 ) /* Power detection mode */
374 #define   POWER_STATE_D0                 ( 0x0000 ) /* Normal operation mode (default) */
375 #define   POWER_STATE_MASK               ( 0x0003 ) /* Power management mode mask */
376 
377 #define REG_WAKEUP_TIME                  ( 0xD6 )   /* GSWUTR */
378 #define   WAKEUP_TIME                    ( 0xFF00 ) /* Min time (sec) wake-up after detected energy */
379 #define   GOSLEEP_TIME                   ( 0x00FF ) /* Min time (sec) before goto sleep when in energy mode */
380 
381 /*
382  * PHY Control Registers
383  * (Offset 0xD8 - 0xF9)
384  */
385 #define REG_PHY_RESET                    ( 0xD8 )   /* PHYRR */
386 #define   PHY_RESET                      ( 0x0001 ) /* Reset PHY */
387 
388 #define REG_PHY_CNTL                     ( 0xE4 )   /* P1MBCR */
389 #define   PHY_SPEED_100MBIT              ( 0x2000 ) /* Force PHY 100Mbps */
390 #define   PHY_AUTO_NEG_ENABLE            ( 0x1000 ) /* Enable PHY auto-negotiation */
391 #define   PHY_POWER_DOWN                 ( 0x0800 ) /* Set PHY power-down */
392 #define   PHY_AUTO_NEG_RESTART           ( 0x0200 ) /* Restart PHY auto-negotiation */
393 #define   PHY_FULL_DUPLEX                ( 0x0100 ) /* Force PHY in full duplex mode */
394 #define   PHY_HP_MDIX                    ( 0x0020 ) /* Set PHY in HP auto MDI-X mode */
395 #define   PHY_FORCE_MDIX                 ( 0x0010 ) /* Force MDI-X */
396 #define   PHY_AUTO_MDIX_DISABLE          ( 0x0008 ) /* Disable auto MDI-X */
397 #define   PHY_TRANSMIT_DISABLE           ( 0x0002 ) /* Disable PHY transmit */
398 #define   PHY_LED_DISABLE                ( 0x0001 ) /* Disable PHY LED */
399 
400 #define REG_PHY_STATUS                   ( 0xE6 )   /* P1MBSR */
401 #define   PHY_100BT4_CAPABLE             ( 0x8000 ) /* 100 BASE-T4 capable */
402 #define   PHY_100BTX_FD_CAPABLE          ( 0x4000 ) /* 100BASE-TX full duplex capable */
403 #define   PHY_100BTX_CAPABLE             ( 0x2000 ) /* 100BASE-TX half duplex capable */
404 #define   PHY_10BT_FD_CAPABLE            ( 0x1000 ) /* 10BASE-TX full duplex capable */
405 #define   PHY_10BT_CAPABLE               ( 0x0800 ) /* 10BASE-TX half duplex capable */
406 #define   PHY_AUTO_NEG_ACKNOWLEDGE       ( 0x0020 ) /* Auto-negotiation complete */
407 #define   PHY_AUTO_NEG_CAPABLE           ( 0x0008 ) /* Auto-negotiation capable */
408 #define   PHY_LINK_UP                    ( 0x0004 ) /* PHY link is up */
409 #define   PHY_EXTENDED_CAPABILITY        ( 0x0001 ) /* PHY extended register capable */
410 
411 #define REG_PHY_ID_LOW                   ( 0xE8 )   /* PHY1ILR */
412 #define REG_PHY_ID_HIGH                  ( 0xEA )   /* PHY1IHR */
413 
414 #define REG_PHY_AUTO_NEGOTIATION         ( 0xEC )   /* P1ANAR */
415 #define   PHY_AUTO_NEG_SYM_PAUSE         ( 0x0400 ) /* Advertise pause capability */
416 #define   PHY_AUTO_NEG_100BTX_FD         ( 0x0100 ) /* Advertise 100 full-duplex capability */
417 #define   PHY_AUTO_NEG_100BTX            ( 0x0080 ) /* Advertise 100 half-duplex capability */
418 #define   PHY_AUTO_NEG_10BT_FD           ( 0x0040 ) /* Advertise 10 full-duplex capability */
419 #define   PHY_AUTO_NEG_10BT              ( 0x0020 ) /* Advertise 10 half-duplex capability */
420 #define   PHY_AUTO_NEG_SELECTOR          ( 0x001F ) /* Selector field mask */
421 #define   PHY_AUTO_NEG_802_3             ( 0x0001 ) /* 802.3 */
422 
423 #define REG_PHY_REMOTE_CAPABILITY        ( 0xEE )   /* P1ANLPR */
424 #define   PHY_REMOTE_SYM_PAUSE           ( 0x0400 ) /* Link partner pause capability */
425 #define   PHY_REMOTE_100BTX_FD           ( 0x0100 ) /* Link partner 100 full-duplex capability */
426 #define   PHY_REMOTE_100BTX              ( 0x0080 ) /* Link partner 100 half-duplex capability */
427 #define   PHY_REMOTE_10BT_FD             ( 0x0040 ) /* Link partner 10 full-duplex capability */
428 #define   PHY_REMOTE_10BT                ( 0x0020 ) /* Link partner 10 half-duplex capability */
429 
430 #define REG_PORT_LINK_MD                 ( 0xF4 )   /* P1SCLMD */
431 #define   PORT_CABLE_10M_SHORT           ( 0x8000 ) /* Cable length is less than 10m short */
432 #define   PORT_CABLE_STAT_FAILED         ( 0x6000 ) /* Cable diagnostic test fail */
433 #define   PORT_CABLE_STAT_SHORT          ( 0x4000 ) /* Short condition detected in the cable */
434 #define   PORT_CABLE_STAT_OPEN           ( 0x2000 ) /* Open condition detected in the cable */
435 #define   PORT_CABLE_STAT_NORMAL         ( 0x0000 ) /* Normal condition */
436 #define   PORT_CABLE_DIAG_RESULT         ( 0x6000 ) /* Cable diagnostic test result mask */
437 #define   PORT_START_CABLE_DIAG          ( 0x1000 ) /* Enable cable diagnostic test */
438 #define   PORT_FORCE_LINK                ( 0x0800 ) /* Enable force link pass */
439 #define   PORT_POWER_SAVING              ( 0x0400 ) /* Disable power saving */
440 #define   PORT_REMOTE_LOOPBACK           ( 0x0200 ) /* Enable remote loopback at PHY */
441 #define   PORT_CABLE_FAULT_COUNTER       ( 0x01FF ) /* Cable length distance to the fault */
442 
443 #define REG_PORT_CTRL                    ( 0xF6 )   /* P1CR */
444 #define   PORT_LED_OFF                   ( 0x8000 ) /* Turn off all the port LEDs (LED3/LED2/LED1/LED0) */
445 #define   PORT_TX_DISABLE                ( 0x4000 ) /* Disable port transmit */
446 #define   PORT_AUTO_NEG_RESTART          ( 0x2000 ) /* Restart auto-negotiation */
447 #define   PORT_POWER_DOWN                ( 0x0800 ) /* Set port power-down */
448 #define   PORT_AUTO_MDIX_DISABLE         ( 0x0400 ) /* Disable auto MDI-X */
449 #define   PORT_FORCE_MDIX                ( 0x0200 ) /* Force MDI-X */
450 #define   PORT_AUTO_NEG_ENABLE           ( 0x0080 ) /* Enable auto-negotiation */
451 #define   PORT_FORCE_100_MBIT            ( 0x0040 ) /* Force PHY 100Mbps */
452 #define   PORT_FORCE_FULL_DUPLEX         ( 0x0020 ) /* Force PHY in full duplex mode */
453 #define   PORT_AUTO_NEG_SYM_PAUSE        ( 0x0010 ) /* Advertise pause capability */
454 #define   PORT_AUTO_NEG_100BTX_FD        ( 0x0008 ) /* Advertise 100 full-duplex capability */
455 #define   PORT_AUTO_NEG_100BTX           ( 0x0004 ) /* Advertise 100 half-duplex capability */
456 #define   PORT_AUTO_NEG_10BT_FD          ( 0x0002 ) /* Advertise 10 full-duplex capability */
457 #define   PORT_AUTO_NEG_10BT             ( 0x0001 ) /* Advertise 10 half-duplex capability */
458 
459 #define REG_PORT_STATUS                  ( 0xF8 )   /* P1SR */
460 #define   PORT_HP_MDIX                   ( 0x8000 ) /* Set PHY in HP auto MDI-X mode */
461 #define   PORT_REVERSED_POLARITY         ( 0x2000 ) /* Polarity is reversed */
462 #define   PORT_RX_FLOW_CTRL              ( 0x1000 ) /* Receive flow control feature is active */
463 #define   PORT_TX_FLOW_CTRL              ( 0x0800 ) /* Transmit flow control feature is active */
464 #define   PORT_STAT_SPEED_100MBIT        ( 0x0400 ) /* Link is 100Mbps */
465 #define   PORT_STAT_FULL_DUPLEX          ( 0x0200 ) /* Link is full duplex mode */
466 #define   PORT_MDIX_STATUS               ( 0x0080 ) /* Is MDI */
467 #define   PORT_AUTO_NEG_COMPLETE         ( 0x0040 ) /* Auto-negotiation complete */
468 #define   PORT_STATUS_LINK_GOOD          ( 0x0020 ) /* PHY link is up */
469 #define   PORT_REMOTE_SYM_PAUSE          ( 0x0010 ) /* Link partner pause capability */
470 #define   PORT_REMOTE_100BTX_FD          ( 0x0008 ) /* Link partner 100 full-duplex capability */
471 #define   PORT_REMOTE_100BTX             ( 0x0004 ) /* Link partner 100 half-duplex capability */
472 #define   PORT_REMOTE_10BT_FD            ( 0x0002 ) /* Link partner 10 full-duplex capability */
473 #define   PORT_REMOTE_10BT               ( 0x0001 ) /* Link partner 10 half-duplex capability */
474 
475 #endif /* KSZ8851SNL_REG_H_INCLUDED */
476