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Searched refs:ulCPSR (Results 1 – 2 of 2) sorted by relevance

/Kernel-v11.0.1/portable/IAR/ARM_CRx_No_GIC/
Dportmacro.h123 volatile uint32_t ulCPSR; in portINLINE_SET_INTERRUPT_MASK_FROM_ISR() local
125 __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR ) ); in portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
127 ulCPSR &= portINTERRUPT_ENABLE_BIT; in portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
129 return ulCPSR; in portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
/Kernel-v11.0.1/portable/GCC/ARM_CRx_No_GIC/
Dportmacro.h121 volatile uint32_t ulCPSR; in portINLINE_SET_INTERRUPT_MASK_FROM_ISR() local
123 __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR )::"memory" ); in portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
125 ulCPSR &= portINTERRUPT_ENABLE_BIT; in portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
127 return ulCPSR; in portINLINE_SET_INTERRUPT_MASK_FROM_ISR()