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/Kernel-v11.0.1/.github/workflows/
D	auto-release.yml	`1 name: Kernel-Auto-Release 11 description: 'Version Number (Ex. 10.4.4)' 15 description: "Version String for task.h on main branch (leave empty to leave as-is)." 20 release-packager: 22 runs-on: ubuntu-latest 25 - name: Tool Setup 26 uses: actions/setup-python@v2 33 - name: Checkout FreeRTOS Release Tools 40 - name: Checkout FreeRTOS Kernel 44 fetch-depth: 0 [all …]`
/Kernel-v11.0.1/
D	History.txt	10 Multiprocessing (AMP) support in 2017, FreeRTOS Version 11.0.0 is the 12 release. SMP enables one instance of the FreeRTOS Kernel to schedule tasks 22 developing a new FreeRTOS port. 35 was last assigned to the task - which due to priority inheritance, may not 42 FreeRTOSConfig.h. We thank @mdnr-g for their contribution. 46 vTaskResume or vTaskResumeFromISR. We thank @Moral-Hao for their 49 FreeRTOS handlers for PendSV and SVCall interrupts on Cortex-M devices. 54 + Add CMake support to allow the application writer to select the RISC-V 58 + Make taskYIELD available to unprivileged tasks for ARMv8-M ports. 59 + Update Cortex-M23 ports to not use PSPLIM_NS. We thank @urutva for their [all …]
D	README.md	1 …eRTOS-Kernel/actions/workflows/unit-tests.yml/badge.svg?branch=main&event=push)](https://github.co… 2 …tps://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTO… 6 This repository contains FreeRTOS kernel source/header files and kernel 9 repository, which contains pre-configured demo application projects under 12 The easiest way to use FreeRTOS is to start with one of the pre-configured demo 17 [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) 20 Additionally, for FreeRTOS kernel feature information refer to the 25 [the instructions here](.github/CONTRIBUTING.md#contributing-via-pull-request). 33 ## To consume FreeRTOS-Kernel 40 - Define the source and version/tag you want to use: [all …]
/Kernel-v11.0.1/.github/
D	CONTRIBUTING.md	3 Thank you for your interest in contributing to our project. Whether it's a bug report, new feature,… 9 This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-con… 10 For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or co… 11 opensource-codeofconduct@amazon.com with any additional questions or comments. 15 …[vulnerability reporting page](https://aws.amazon.com/security/vulnerability-reporting/). Please d… 21 2. If your search turns up empty, create a new topic in the [forums](https://forums.freertos.org/) … 24 When creating a new topic on the forums or filing an issue, please include as many relevant details… 26 * A clear description of the situation - what you observe, what you expect, and your view on how th… 28 * The version of our code being used. 38 3. You open an issue to discuss any significant work - we would hate for your time to be wasted. [all …]
/Kernel-v11.0.1/include/
D	message_buffer.h	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 56 * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit 57 * architecture, so writing a 10 byte message to a message buffer on a 32-bit 73 /* INDENT-OFF / 77 / INDENT-ON / 88 /-----------------------------------------------------------/ 97 Creates a new message buffer using dynamically allocated memory. See 98 * xMessageBufferCreateStatic() for a version that uses statically allocated 108 * 32-bit architecture, so on most 32-bit architectures a 10 byte message will [all …]
D	stream_buffer.h	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 59 /* INDENT-OFF / 63 / INDENT-ON / 88 Creates a new stream buffer using dynamically allocated memory. See 89 * xStreamBufferCreateStatic() for a version that uses statically allocated 124 * the stream buffer data structures and storage area. A non-NULL value being 125 * returned indicates that the stream buffer has been created successfully - 174 * Creates a new stream buffer using statically allocated memory. See 175 * xStreamBufferCreate() for a version that uses dynamically allocated memory. [all …]
D	list.h	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 41 * points to this marker - even though it is at the tail of the list. This 97 /* INDENT-OFF / 101 / INDENT-ON / 121 / Define macros that add new members into the list structures. / 127 / Define macros that set the new structure members to known values. */ 128 …#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrity… 129 …#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrity… 130 …#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValu… [all …]
D	task.h	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 39 /* INDENT-OFF / 43 / INDENT-ON / 45 /----------------------------------------------------------- 47 ----------------------------------------------------------/ 50 * If tskKERNEL_VERSION_NUMBER ends with + it represents the version in development 54 * values will reflect the last released version number. 91 struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware d… 168 …defined by the run time stats clock. See https://www.FreeRTOS.org/rtos-run-time-stats.html. Only… [all …]
D	queue.h	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 37 /* INDENT-OFF / 41 / INDENT-ON / 50 struct QueueDefinition; / Using old naming convention so as not to break kernel aware debuggers. / 89 Creates a new queue instance, and returns a handle by which the new queue 102 * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html 163 * Creates a new queue instance, and returns a handle by which the new queue 176 * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html 188 * one time - which is ( uxQueueLength * uxItemsSize ) bytes. If uxItemSize is [all …]
D	event_groups.h	`2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 59 /* INDENT-OFF / 63 / INDENT-ON / 85 be set and then tested atomically - as is the case where event groups are 106 * The type that holds event bits always matches TickType_t - therefore the 121 * Create a new event group. 178 * Create a new event group. 389 * A version of xEventGroupClearBits() that can be called from an interrupt. 459 * is a version that can be called from an interrupt. [all …]`
D	timers.h	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 40 /* INDENT-OFF / 44 / INDENT-ON / 46 /----------------------------------------------------------- 48 ----------------------------------------------------------/ 54 * or interrupt version of the queue send function should be used. / 55 #define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 ) 56 #define tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 ) 77 struct tmrTimerControl; / The old naming convention is used to prevent breaking kernel aware debug… [all …]
/Kernel-v11.0.1/portable/ThirdParty/XCC/Xtensa/
D	readme_xtensa.txt	4 FreeRTOS Kernel Version 10.0.0 8 ------------ 14 This port currently works with FreeRTOS kernel version 10.0.0. 18 -------------------------------------------------- 26 NOTE: It may be possible to build and run this with the open-source 27 xtensa-linux tools provided you have the correct overlay for your Xtensa 33 thread-safety on a per task basis (for use in tasks only, not interrupt 48 - Timer interrupt option with at least one interruptible timer. 49 - Interrupt option (implied by the timer interrupt option). 50 - Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported. [all …]
D	portasm.S	2 * FreeRTOS Kernel V11.0.1 3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc. 6 * SPDX-License-Identifier: MIT 96 /* Save a12-13 in the stack frame as required by _xt_context_save. / 103 / Save the rest of the interrupted context (preserves A12-13). / 123 s32i a1, a2, TOPOFSTACK_OFFS / pxCurrentTCB->pxTopOfStack = SP / 138 switching, restore the (possibly) new task's context, and return to the 157 addi a2, a2, -1 /* decrement nesting count / 164 l32i a1, a2, TOPOFSTACK_OFFS / SP = pxCurrentTCB->pxTopOfStack */ 174 Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption. [all …]
/Kernel-v11.0.1/portable/ThirdParty/GCC/ARM_TFM/
D	README.md	4 services in Trusted Firmware M(TF-M) through Platform Security Architecture 5 (PSA) API based on the ARM Cortex-M23, Cortex-M33, Cortex-M55 and Cortex-M85 10 …ource Page](https://developer.arm.com/architectures/security-architectures/platform-security-archi… 12 TF-M is an open source project. It provides a reference implementation of PSA 13 for Arm M-profile architecture. Please get the details from this [link](https://git.trustedfirmware… 18 …The implementation of APIs which are defined in ```\ns_interface\os_wrapper\mutex.h``` by tf-m-tes… 19 (tag: TF-Mv1.5.0 & TF-Mv1.6.0). The implementation is based on FreeRTOS mutex type semaphore. 25 * Step 2: build the nonsecure image. Please follow the Build the Non-Secure Side for details. 29 ### Get the TF-M source code 31 …firmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is supported by TF-M … [all …]
/Kernel-v11.0.1/portable/IAR/STR91x/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 32 ----------------------------------------------------------/ 62 #define abs( x ) ( ( x ) > 0 ? ( x ) : -( x ) ) 78 if( ( ( ( ( port )->DR[ ( pin ) << 2 ] ) ) & ( pin ) ) != Bit_RESET ) \ 80 ( port )->DR[ ( pin ) << 2 ] = 0x00; \ 84 ( port )->DR[ ( pin ) << 2 ] = ( pin ); \ 88 /-----------------------------------------------------------/ 95 during the kernel initialisation process. */ [all …]
/Kernel-v11.0.1/portable/IAR/STR71x/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 32 ----------------------------------------------------------/ 55 /-----------------------------------------------------------/ 62 during the kernel initialisation process. / 66 respectively. The preemptive version is not defined as __irq as it is called 71 /-----------------------------------------------------------/ 89 pxTopOfStack--; in pxPortInitialiseStack() 94 /* First on the stack is the return address - which in this case is the in pxPortInitialiseStack() [all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM4F_MPU/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 53 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 105 / Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure 152 /* The systick is a 24-bit counter. / 160 / For strict compliance with the Cortex-M spec the task start address should 161 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ 176 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) [all …]
/Kernel-v11.0.1/examples/template_configuration/
D	FreeRTOSConfig.h	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 56 /* configSYSTICK_CLOCK_HZ is an optional parameter for ARM Cortex-M ports only. 58 * By default ARM Cortex-M ports generate the RTOS tick interrupt from the 59 * Cortex-M SysTick timer. Most Cortex-M MCUs run the SysTick timer at the same 60 * frequency as the MCU itself - when that is the case configSYSTICK_CLOCK_HZ is 80 /* Set configUSE_PREEMPTION to 1 to use pre-emptive scheduling. Set 81 * configUSE_PREEMPTION to 0 to use co-operative scheduling. 82 * See https://www.freertos.org/single-core-amp-smp-rtos-scheduling.html. / 89 https://freertos.org/single-core-amp-smp-rtos-scheduling.html. */ [all …]
/Kernel-v11.0.1/portable/CCS/ARM_CM3/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 38 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 75 / The systick is a 24-bit counter. / 83 / For strict compliance with the Cortex-M spec the task start address should 84 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 121 /-----------------------------------------------------------/ 165 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.0.1/portable/RVDS/ARM_CM3/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 38 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 84 / The systick is a 24-bit counter. / 92 / For strict compliance with the Cortex-M spec the task start address should 93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 132 /-----------------------------------------------------------/ 172 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM7/r0p1/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 45 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 96 / The systick is a 24-bit counter. / 104 / For strict compliance with the Cortex-M spec the task start address should 105 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 152 /-----------------------------------------------------------/ 192 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.0.1/portable/CCS/ARM_CM4F/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 42 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 84 / The systick is a 24-bit counter. / 92 / For strict compliance with the Cortex-M spec the task start address should 93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 135 /-----------------------------------------------------------/ 179 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM3/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 41 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 87 / The systick is a 24-bit counter. / 95 / For strict compliance with the Cortex-M spec the task start address should 96 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 138 /-----------------------------------------------------------/ 178 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.0.1/portable/RVDS/ARM_CM4F/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 42 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 68 / Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 99 /* The systick is a 24-bit counter. / 107 / For strict compliance with the Cortex-M spec the task start address should 108 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 152 /-----------------------------------------------------------*/ [all …]
/Kernel-v11.0.1/portable/RVDS/ARM_CM7/r0p1/
D	port.c	2 * FreeRTOS Kernel V11.0.1 5 * SPDX-License-Identifier: MIT 29 /----------------------------------------------------------- 31 ----------------------------------------------------------/ 42 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /www.FreeRTOS.org/RTOS-Cortex-M3-M4.html / 93 / The systick is a 24-bit counter. / 101 / For strict compliance with the Cortex-M spec the task start address should 102 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. / 146 /-----------------------------------------------------------/ 186 /-----------------------------------------------------------*/ [all …]