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Searched refs:portasmADDITIONAL_CONTEXT_SIZE (Results 1 – 7 of 7) sorted by relevance

/Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/
Dfreertos_risc_v_chip_specific_extensions.h72 #define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */ macro
76 addi sp, sp, -( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Make room for the additional re…
105 addi sp, sp, ( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Remove space added for additiona…
/Kernel-v11.1.0/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/
Dfreertos_risc_v_chip_specific_extensions.h59 #define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ macro
/Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/
Dfreertos_risc_v_chip_specific_extensions.h59 #define portasmADDITIONAL_CONTEXT_SIZE 0 macro
/Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/
Dfreertos_risc_v_chip_specific_extensions.h59 #define portasmADDITIONAL_CONTEXT_SIZE 0 macro
/Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/
Dfreertos_risc_v_chip_specific_extensions.h59 #define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ macro
/Kernel-v11.1.0/portable/IAR/RISC-V/
DportASM.s227 …addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
/Kernel-v11.1.0/portable/GCC/RISC-V/
DportASM.S219 …addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */