Searched refs:ISR (Results 1 – 17 of 17) sorted by relevance
753 ISR( portSCHEDULER_ISR, ISR_NAKED ) __attribute__( ( hot, flatten ) );757 ISR( portSCHEDULER_ISR ) in ISR() function771 ISR( portSCHEDULER_ISR ) __attribute__( ( hot, flatten ) );775 ISR( portSCHEDULER_ISR ) in ISR() function
49 The `NO_BLOCK` decorator will enable the global interrupt early in the handling of an ISR (in this …
78 ; Within an IRQ ISR the link register has an offset from the true return79 ; address, but an SWI ISR does not. Add the offset manually so the same80 ; ISR return code can be used in both cases.
49 ; Tick ISR Prototype103 ; Call: ISR122 COMMON INTVEC:CODE:ROOT(1) ; Set ISR location to the Interrupt vector table.127 COMMON INTVEC:CODE:ROOT(1) ; Set ISR location to the Interrupt vector table.
34 ; ISR functions63 ; To write an ISR, implement the ISR function using the __interrupt keyword65 ; Instead manually place the name of the ISR in the vector table using an73 jmp SIG_OUTPUT_COMPARE1A ; ISR76 jmp SIG_UART_RECV ; ISR79 jmp SIG_UART_DATA ; ISR
34 ; ISR functions60 ; To write an ISR, implement the ISR function using the __interrupt keyword62 ; Instead manually place the name of the ISR in the vector table using an69 jmp TICK_INT ; ISR
65 … ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR91 … ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR
73 ;* The RTOS tick ISR.
151 ; Within an IRQ ISR the link register has an offset from the true return
42 * The RTOS tick ISR.
69 * The RTOS tick ISR.
60 ; Tick ISR Prototype241 ; Call: ISR
69 ; Tick ISR Prototype250 ; Call: ISR
383 ISR's
18 stream buffer and message buffer from an Interrupt Service Routine (ISR).722 + Added a 'get task tag from ISR' function.1024 + If a task notification is used to unblock a task from an ISR, but the1160 + Fixed a potential issue related to the use of queue sets from an ISR.1171 + Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to1335 The 'clear bits from ISR' functionality is now implemented using a1590 the Cortex-M port layer "yield" and "yield" from ISR are now implemented1591 separately as the barrier instructions are not required in the ISR case.1689 + The last parameter in ISR safe FreeRTOS queue and semaphore functions2431 + Changed the method used to force a context switch within an ISR for the[all …]
