1 /**---------------------------------------------------------------------------- */
2 /** ATMEL Microcontroller Software Support - ROUSSET - */
3 /**---------------------------------------------------------------------------- */
4 /** The software is delivered "AS IS" without warranty or condition of any */
5 /** kind, either express, implied or statutory. This includes without */
6 /** limitation any warranty or condition with respect to merchantability or */
7 /** fitness for any particular purpose, or against the infringements of */
8 /** intellectual property rights of others. */
9 /**---------------------------------------------------------------------------- */
10 /** File Name : lib_AT91SAM7S64.h */
11 /** Object : AT91SAM7S64 inlined functions */
12 /** Generated : AT91 SW Application Group 07/16/2004 (07:43:09) */
13 /** */
14 /** CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// */
15 /** CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// */
16 /** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */
17 /** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */
18 /** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// */
19 /** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */
20 /** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */
21 /** CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */
22 /** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// */
23 /** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */
24 /** CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// */
25 /** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */
26 /** CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// */
27 /** CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// */
28 /**---------------------------------------------------------------------------- */
29
30 #ifndef lib_AT91SAM7S64_H
31 #define lib_AT91SAM7S64_H
32
33 /* *****************************************************************************
34 * SOFTWARE API FOR MC
35 ***************************************************************************** */
36
37 #define AT91C_MC_CORRECT_KEY ( ( unsigned int ) 0x5A << 24 ) /* (MC) Correct Protect Key */
38
39 /**---------------------------------------------------------------------------- */
40 /** \fn AT91F_MC_Remap */
41 /** \brief Make Remap */
42 /**---------------------------------------------------------------------------- */
AT91F_MC_Remap(void)43 __inline void AT91F_MC_Remap( void ) /* */
44 {
45 AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC;
46
47 pMC->MC_RCR = AT91C_MC_RCB;
48 }
49
50 /**---------------------------------------------------------------------------- */
51 /** \fn AT91F_MC_EFC_CfgModeReg */
52 /** \brief Configure the EFC Mode Register of the MC controller */
53 /**---------------------------------------------------------------------------- */
AT91F_MC_EFC_CfgModeReg(AT91PS_MC pMC,unsigned int mode)54 __inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC controller */
55 unsigned int mode ) /* mode register */
56 {
57 /* Write to the FMR register */
58 pMC->MC_FMR = mode;
59 }
60
61 /**---------------------------------------------------------------------------- */
62 /** \fn AT91F_MC_EFC_GetModeReg */
63 /** \brief Return MC EFC Mode Regsiter */
64 /**---------------------------------------------------------------------------- */
AT91F_MC_EFC_GetModeReg(AT91PS_MC pMC)65 __inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */
66 {
67 return pMC->MC_FMR;
68 }
69
70 /**---------------------------------------------------------------------------- */
71 /** \fn AT91F_MC_EFC_ComputeFMCN */
72 /** \brief Return MC EFC Mode Regsiter */
73 /**---------------------------------------------------------------------------- */
AT91F_MC_EFC_ComputeFMCN(int master_clock)74 __inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */
75 {
76 return( master_clock / 1000000 + 2 );
77 }
78
79 /**---------------------------------------------------------------------------- */
80 /** \fn AT91F_MC_EFC_PerformCmd */
81 /** \brief Perform EFC Command */
82 /**---------------------------------------------------------------------------- */
AT91F_MC_EFC_PerformCmd(AT91PS_MC pMC,unsigned int transfer_cmd)83 __inline void AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, /* pointer to a MC controller */
84 unsigned int transfer_cmd )
85 {
86 pMC->MC_FCR = transfer_cmd;
87 }
88
89 /**---------------------------------------------------------------------------- */
90 /** \fn AT91F_MC_EFC_GetStatus */
91 /** \brief Return MC EFC Status */
92 /**---------------------------------------------------------------------------- */
AT91F_MC_EFC_GetStatus(AT91PS_MC pMC)93 __inline unsigned int AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) /* pointer to a MC controller */
94 {
95 return pMC->MC_FSR;
96 }
97
98 /**---------------------------------------------------------------------------- */
99 /** \fn AT91F_MC_EFC_IsInterruptMasked */
100 /** \brief Test if EFC MC Interrupt is Masked */
101 /**---------------------------------------------------------------------------- */
AT91F_MC_EFC_IsInterruptMasked(AT91PS_MC pMC,unsigned int flag)102 __inline unsigned int AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC, /* \arg pointer to a MC controller */
103 unsigned int flag ) /* \arg flag to be tested */
104 {
105 return( AT91F_MC_EFC_GetModeReg( pMC ) & flag );
106 }
107
108 /**---------------------------------------------------------------------------- */
109 /** \fn AT91F_MC_EFC_IsInterruptSet */
110 /** \brief Test if EFC MC Interrupt is Set */
111 /**---------------------------------------------------------------------------- */
AT91F_MC_EFC_IsInterruptSet(AT91PS_MC pMC,unsigned int flag)112 __inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg pointer to a MC controller */
113 unsigned int flag ) /* \arg flag to be tested */
114 {
115 return( AT91F_MC_EFC_GetStatus( pMC ) & flag );
116 }
117
118 /* *****************************************************************************
119 * SOFTWARE API FOR PDC
120 ***************************************************************************** */
121 /**---------------------------------------------------------------------------- */
122 /** \fn AT91F_PDC_SetNextRx */
123 /** \brief Set the next receive transfer descriptor */
124 /**---------------------------------------------------------------------------- */
AT91F_PDC_SetNextRx(AT91PS_PDC pPDC,char * address,unsigned int bytes)125 __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
126 char * address, /* \arg address to the next bloc to be received */
127 unsigned int bytes ) /* \arg number of bytes to be received */
128 {
129 pPDC->PDC_RNPR = ( unsigned int ) address;
130 pPDC->PDC_RNCR = bytes;
131 }
132
133 /**---------------------------------------------------------------------------- */
134 /** \fn AT91F_PDC_SetNextTx */
135 /** \brief Set the next transmit transfer descriptor */
136 /**---------------------------------------------------------------------------- */
AT91F_PDC_SetNextTx(AT91PS_PDC pPDC,char * address,unsigned int bytes)137 __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
138 char * address, /* \arg address to the next bloc to be transmitted */
139 unsigned int bytes ) /* \arg number of bytes to be transmitted */
140 {
141 pPDC->PDC_TNPR = ( unsigned int ) address;
142 pPDC->PDC_TNCR = bytes;
143 }
144
145 /**---------------------------------------------------------------------------- */
146 /** \fn AT91F_PDC_SetRx */
147 /** \brief Set the receive transfer descriptor */
148 /**---------------------------------------------------------------------------- */
AT91F_PDC_SetRx(AT91PS_PDC pPDC,char * address,unsigned int bytes)149 __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
150 char * address, /* \arg address to the next bloc to be received */
151 unsigned int bytes ) /* \arg number of bytes to be received */
152 {
153 pPDC->PDC_RPR = ( unsigned int ) address;
154 pPDC->PDC_RCR = bytes;
155 }
156
157 /**---------------------------------------------------------------------------- */
158 /** \fn AT91F_PDC_SetTx */
159 /** \brief Set the transmit transfer descriptor */
160 /**---------------------------------------------------------------------------- */
AT91F_PDC_SetTx(AT91PS_PDC pPDC,char * address,unsigned int bytes)161 __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
162 char * address, /* \arg address to the next bloc to be transmitted */
163 unsigned int bytes ) /* \arg number of bytes to be transmitted */
164 {
165 pPDC->PDC_TPR = ( unsigned int ) address;
166 pPDC->PDC_TCR = bytes;
167 }
168
169 /**---------------------------------------------------------------------------- */
170 /** \fn AT91F_PDC_EnableTx */
171 /** \brief Enable transmit */
172 /**---------------------------------------------------------------------------- */
AT91F_PDC_EnableTx(AT91PS_PDC pPDC)173 __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
174 {
175 pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
176 }
177
178 /**---------------------------------------------------------------------------- */
179 /** \fn AT91F_PDC_EnableRx */
180 /** \brief Enable receive */
181 /**---------------------------------------------------------------------------- */
AT91F_PDC_EnableRx(AT91PS_PDC pPDC)182 __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
183 {
184 pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
185 }
186
187 /**---------------------------------------------------------------------------- */
188 /** \fn AT91F_PDC_DisableTx */
189 /** \brief Disable transmit */
190 /**---------------------------------------------------------------------------- */
AT91F_PDC_DisableTx(AT91PS_PDC pPDC)191 __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
192 {
193 pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
194 }
195
196 /**---------------------------------------------------------------------------- */
197 /** \fn AT91F_PDC_DisableRx */
198 /** \brief Disable receive */
199 /**---------------------------------------------------------------------------- */
AT91F_PDC_DisableRx(AT91PS_PDC pPDC)200 __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
201 {
202 pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
203 }
204
205 /**---------------------------------------------------------------------------- */
206 /** \fn AT91F_PDC_IsTxEmpty */
207 /** \brief Test if the current transfer descriptor has been sent */
208 /**---------------------------------------------------------------------------- */
AT91F_PDC_IsTxEmpty(AT91PS_PDC pPDC)209 __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */
210 AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
211 {
212 return !( pPDC->PDC_TCR );
213 }
214
215 /**---------------------------------------------------------------------------- */
216 /** \fn AT91F_PDC_IsNextTxEmpty */
217 /** \brief Test if the next transfer descriptor has been moved to the current td */
218 /**---------------------------------------------------------------------------- */
AT91F_PDC_IsNextTxEmpty(AT91PS_PDC pPDC)219 __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */
220 AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
221 {
222 return !( pPDC->PDC_TNCR );
223 }
224
225 /**---------------------------------------------------------------------------- */
226 /** \fn AT91F_PDC_IsRxEmpty */
227 /** \brief Test if the current transfer descriptor has been filled */
228 /**---------------------------------------------------------------------------- */
AT91F_PDC_IsRxEmpty(AT91PS_PDC pPDC)229 __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */
230 AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
231 {
232 return !( pPDC->PDC_RCR );
233 }
234
235 /**---------------------------------------------------------------------------- */
236 /** \fn AT91F_PDC_IsNextRxEmpty */
237 /** \brief Test if the next transfer descriptor has been moved to the current td */
238 /**---------------------------------------------------------------------------- */
AT91F_PDC_IsNextRxEmpty(AT91PS_PDC pPDC)239 __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */
240 AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
241 {
242 return !( pPDC->PDC_RNCR );
243 }
244
245 /**---------------------------------------------------------------------------- */
246 /** \fn AT91F_PDC_Open */
247 /** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */
248 /**---------------------------------------------------------------------------- */
AT91F_PDC_Open(AT91PS_PDC pPDC)249 __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
250 {
251 /** Disable the RX and TX PDC transfer requests */
252 AT91F_PDC_DisableRx( pPDC );
253 AT91F_PDC_DisableTx( pPDC );
254
255 /** Reset all Counter register Next buffer first */
256 AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
257 AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
258 AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
259 AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
260
261 /** Enable the RX and TX PDC transfer requests */
262 AT91F_PDC_EnableRx( pPDC );
263 AT91F_PDC_EnableTx( pPDC );
264 }
265
266 /**---------------------------------------------------------------------------- */
267 /** \fn AT91F_PDC_Close */
268 /** \brief Close PDC: disable TX and RX reset transfer descriptors */
269 /**---------------------------------------------------------------------------- */
AT91F_PDC_Close(AT91PS_PDC pPDC)270 __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */
271 {
272 /** Disable the RX and TX PDC transfer requests */
273 AT91F_PDC_DisableRx( pPDC );
274 AT91F_PDC_DisableTx( pPDC );
275
276 /** Reset all Counter register Next buffer first */
277 AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 );
278 AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 );
279 AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 );
280 AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 );
281 }
282
283 /**---------------------------------------------------------------------------- */
284 /** \fn AT91F_PDC_SendFrame */
285 /** \brief Close PDC: disable TX and RX reset transfer descriptors */
286 /**---------------------------------------------------------------------------- */
AT91F_PDC_SendFrame(AT91PS_PDC pPDC,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)287 __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC,
288 char * pBuffer,
289 unsigned int szBuffer,
290 char * pNextBuffer,
291 unsigned int szNextBuffer )
292 {
293 if( AT91F_PDC_IsTxEmpty( pPDC ) )
294 {
295 /** Buffer and next buffer can be initialized */
296 AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer );
297 AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer );
298 return 2;
299 }
300 else if( AT91F_PDC_IsNextTxEmpty( pPDC ) )
301 {
302 /** Only one buffer can be initialized */
303 AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer );
304 return 1;
305 }
306 else
307 {
308 /** All buffer are in use... */
309 return 0;
310 }
311 }
312
313 /**---------------------------------------------------------------------------- */
314 /** \fn AT91F_PDC_ReceiveFrame */
315 /** \brief Close PDC: disable TX and RX reset transfer descriptors */
316 /**---------------------------------------------------------------------------- */
AT91F_PDC_ReceiveFrame(AT91PS_PDC pPDC,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)317 __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC,
318 char * pBuffer,
319 unsigned int szBuffer,
320 char * pNextBuffer,
321 unsigned int szNextBuffer )
322 {
323 if( AT91F_PDC_IsRxEmpty( pPDC ) )
324 {
325 /** Buffer and next buffer can be initialized */
326 AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer );
327 AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer );
328 return 2;
329 }
330 else if( AT91F_PDC_IsNextRxEmpty( pPDC ) )
331 {
332 /** Only one buffer can be initialized */
333 AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer );
334 return 1;
335 }
336 else
337 {
338 /** All buffer are in use... */
339 return 0;
340 }
341 }
342
343 /* *****************************************************************************
344 * SOFTWARE API FOR DBGU
345 ***************************************************************************** */
346 /**---------------------------------------------------------------------------- */
347 /** \fn AT91F_DBGU_InterruptEnable */
348 /** \brief Enable DBGU Interrupt */
349 /**---------------------------------------------------------------------------- */
AT91F_DBGU_InterruptEnable(AT91PS_DBGU pDbgu,unsigned int flag)350 __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
351 unsigned int flag ) /* \arg dbgu interrupt to be enabled */
352 {
353 pDbgu->DBGU_IER = flag;
354 }
355
356 /**---------------------------------------------------------------------------- */
357 /** \fn AT91F_DBGU_InterruptDisable */
358 /** \brief Disable DBGU Interrupt */
359 /**---------------------------------------------------------------------------- */
AT91F_DBGU_InterruptDisable(AT91PS_DBGU pDbgu,unsigned int flag)360 __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
361 unsigned int flag ) /* \arg dbgu interrupt to be disabled */
362 {
363 pDbgu->DBGU_IDR = flag;
364 }
365
366 /**---------------------------------------------------------------------------- */
367 /** \fn AT91F_DBGU_GetInterruptMaskStatus */
368 /** \brief Return DBGU Interrupt Mask Status */
369 /**---------------------------------------------------------------------------- */
AT91F_DBGU_GetInterruptMaskStatus(AT91PS_DBGU pDbgu)370 __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */
371 AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */
372 {
373 return pDbgu->DBGU_IMR;
374 }
375
376 /**---------------------------------------------------------------------------- */
377 /** \fn AT91F_DBGU_IsInterruptMasked */
378 /** \brief Test if DBGU Interrupt is Masked */
379 /**---------------------------------------------------------------------------- */
AT91F_DBGU_IsInterruptMasked(AT91PS_DBGU pDbgu,unsigned int flag)380 __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */
381 unsigned int flag ) /* \arg flag to be tested */
382 {
383 return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag );
384 }
385
386 /* *****************************************************************************
387 * SOFTWARE API FOR SSC
388 ***************************************************************************** */
389 /** Define the standard I2S mode configuration */
390
391 /** Configuration to set in the SSC Transmit Clock Mode Register */
392 /** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
393 /** nb_slot_by_frame : number of channels */
394 #define AT91C_I2S_ASY_MASTER_TX_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
395 ( + \
396 AT91C_SSC_CKS_DIV + \
397 AT91C_SSC_CKO_CONTINUOUS + \
398 AT91C_SSC_CKG_NONE + \
399 AT91C_SSC_START_FALL_RF + \
400 AT91C_SSC_STTOUT + \
401 ( ( 1 << 16 ) & AT91C_SSC_STTDLY ) + \
402 ( ( ( ( nb_bit_by_slot * nb_slot_by_frame ) / 2 ) - 1 ) << 24 ) )
403
404
405 /** Configuration to set in the SSC Transmit Frame Mode Register */
406 /** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */
407 /** nb_slot_by_frame : number of channels */
408 #define AT91C_I2S_ASY_TX_FRAME_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \
409 ( + \
410 ( nb_bit_by_slot - 1 ) + \
411 AT91C_SSC_MSBF + \
412 ( ( ( nb_slot_by_frame - 1 ) << 8 ) & AT91C_SSC_DATNB ) + \
413 ( ( ( nb_bit_by_slot - 1 ) << 16 ) & AT91C_SSC_FSLEN ) + \
414 AT91C_SSC_FSOS_NEGATIVE )
415
416
417 /**---------------------------------------------------------------------------- */
418 /** \fn AT91F_SSC_SetBaudrate */
419 /** \brief Set the baudrate according to the CPU clock */
420 /**---------------------------------------------------------------------------- */
AT91F_SSC_SetBaudrate(AT91PS_SSC pSSC,unsigned int mainClock,unsigned int speed)421 __inline void AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
422 unsigned int mainClock, /* \arg peripheral clock */
423 unsigned int speed ) /* \arg SSC baudrate */
424 {
425 unsigned int baud_value;
426
427 /** Define the baud rate divisor register */
428 if( speed == 0 )
429 {
430 baud_value = 0;
431 }
432 else
433 {
434 baud_value = ( unsigned int ) ( mainClock * 10 ) / ( 2 * speed );
435
436 if( ( baud_value % 10 ) >= 5 )
437 {
438 baud_value = ( baud_value / 10 ) + 1;
439 }
440 else
441 {
442 baud_value /= 10;
443 }
444 }
445
446 pSSC->SSC_CMR = baud_value;
447 }
448
449 /**---------------------------------------------------------------------------- */
450 /** \fn AT91F_SSC_Configure */
451 /** \brief Configure SSC */
452 /**---------------------------------------------------------------------------- */
AT91F_SSC_Configure(AT91PS_SSC pSSC,unsigned int syst_clock,unsigned int baud_rate,unsigned int clock_rx,unsigned int mode_rx,unsigned int clock_tx,unsigned int mode_tx)453 __inline void AT91F_SSC_Configure( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
454 unsigned int syst_clock, /* \arg System Clock Frequency */
455 unsigned int baud_rate, /* \arg Expected Baud Rate Frequency */
456 unsigned int clock_rx, /* \arg Receiver Clock Parameters */
457 unsigned int mode_rx, /* \arg mode Register to be programmed */
458 unsigned int clock_tx, /* \arg Transmitter Clock Parameters */
459 unsigned int mode_tx ) /* \arg mode Register to be programmed */
460 {
461 /** Disable interrupts */
462 pSSC->SSC_IDR = ( unsigned int ) -1;
463
464 /** Reset receiver and transmitter */
465 pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS;
466
467 /** Define the Clock Mode Register */
468 AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate );
469
470 /** Write the Receive Clock Mode Register */
471 pSSC->SSC_RCMR = clock_rx;
472
473 /** Write the Transmit Clock Mode Register */
474 pSSC->SSC_TCMR = clock_tx;
475
476 /** Write the Receive Frame Mode Register */
477 pSSC->SSC_RFMR = mode_rx;
478
479 /** Write the Transmit Frame Mode Register */
480 pSSC->SSC_TFMR = mode_tx;
481
482 /** Clear Transmit and Receive Counters */
483 AT91F_PDC_Open( ( AT91PS_PDC ) &( pSSC->SSC_RPR ) );
484 }
485
486 /**---------------------------------------------------------------------------- */
487 /** \fn AT91F_SSC_EnableRx */
488 /** \brief Enable receiving data */
489 /**---------------------------------------------------------------------------- */
AT91F_SSC_EnableRx(AT91PS_SSC pSSC)490 __inline void AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
491 {
492 /** Enable receiver */
493 pSSC->SSC_CR = AT91C_SSC_RXEN;
494 }
495
496 /**---------------------------------------------------------------------------- */
497 /** \fn AT91F_SSC_DisableRx */
498 /** \brief Disable receiving data */
499 /**---------------------------------------------------------------------------- */
AT91F_SSC_DisableRx(AT91PS_SSC pSSC)500 __inline void AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
501 {
502 /** Disable receiver */
503 pSSC->SSC_CR = AT91C_SSC_RXDIS;
504 }
505
506 /**---------------------------------------------------------------------------- */
507 /** \fn AT91F_SSC_EnableTx */
508 /** \brief Enable sending data */
509 /**---------------------------------------------------------------------------- */
AT91F_SSC_EnableTx(AT91PS_SSC pSSC)510 __inline void AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
511 {
512 /** Enable transmitter */
513 pSSC->SSC_CR = AT91C_SSC_TXEN;
514 }
515
516 /**---------------------------------------------------------------------------- */
517 /** \fn AT91F_SSC_DisableTx */
518 /** \brief Disable sending data */
519 /**---------------------------------------------------------------------------- */
AT91F_SSC_DisableTx(AT91PS_SSC pSSC)520 __inline void AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */
521 {
522 /** Disable transmitter */
523 pSSC->SSC_CR = AT91C_SSC_TXDIS;
524 }
525
526 /**---------------------------------------------------------------------------- */
527 /** \fn AT91F_SSC_EnableIt */
528 /** \brief Enable SSC IT */
529 /**---------------------------------------------------------------------------- */
AT91F_SSC_EnableIt(AT91PS_SSC pSSC,unsigned int flag)530 __inline void AT91F_SSC_EnableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
531 unsigned int flag ) /* \arg IT to be enabled */
532 {
533 /** Write to the IER register */
534 pSSC->SSC_IER = flag;
535 }
536
537 /**---------------------------------------------------------------------------- */
538 /** \fn AT91F_SSC_DisableIt */
539 /** \brief Disable SSC IT */
540 /**---------------------------------------------------------------------------- */
AT91F_SSC_DisableIt(AT91PS_SSC pSSC,unsigned int flag)541 __inline void AT91F_SSC_DisableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */
542 unsigned int flag ) /* \arg IT to be disabled */
543 {
544 /** Write to the IDR register */
545 pSSC->SSC_IDR = flag;
546 }
547
548 /**---------------------------------------------------------------------------- */
549 /** \fn AT91F_SSC_ReceiveFrame */
550 /** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
551 /**---------------------------------------------------------------------------- */
AT91F_SSC_ReceiveFrame(AT91PS_SSC pSSC,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)552 __inline unsigned int AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC,
553 char * pBuffer,
554 unsigned int szBuffer,
555 char * pNextBuffer,
556 unsigned int szNextBuffer )
557 {
558 return AT91F_PDC_ReceiveFrame(
559 ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
560 pBuffer,
561 szBuffer,
562 pNextBuffer,
563 szNextBuffer );
564 }
565
566 /**---------------------------------------------------------------------------- */
567 /** \fn AT91F_SSC_SendFrame */
568 /** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
569 /**---------------------------------------------------------------------------- */
AT91F_SSC_SendFrame(AT91PS_SSC pSSC,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)570 __inline unsigned int AT91F_SSC_SendFrame( AT91PS_SSC pSSC,
571 char * pBuffer,
572 unsigned int szBuffer,
573 char * pNextBuffer,
574 unsigned int szNextBuffer )
575 {
576 return AT91F_PDC_SendFrame(
577 ( AT91PS_PDC ) &( pSSC->SSC_RPR ),
578 pBuffer,
579 szBuffer,
580 pNextBuffer,
581 szNextBuffer );
582 }
583
584 /**---------------------------------------------------------------------------- */
585 /** \fn AT91F_SSC_GetInterruptMaskStatus */
586 /** \brief Return SSC Interrupt Mask Status */
587 /**---------------------------------------------------------------------------- */
AT91F_SSC_GetInterruptMaskStatus(AT91PS_SSC pSsc)588 __inline unsigned int AT91F_SSC_GetInterruptMaskStatus( /* \return SSC Interrupt Mask Status */
589 AT91PS_SSC pSsc ) /* \arg pointer to a SSC controller */
590 {
591 return pSsc->SSC_IMR;
592 }
593
594 /**---------------------------------------------------------------------------- */
595 /** \fn AT91F_SSC_IsInterruptMasked */
596 /** \brief Test if SSC Interrupt is Masked */
597 /**---------------------------------------------------------------------------- */
AT91F_SSC_IsInterruptMasked(AT91PS_SSC pSsc,unsigned int flag)598 __inline int AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, /* \arg pointer to a SSC controller */
599 unsigned int flag ) /* \arg flag to be tested */
600 {
601 return( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag );
602 }
603
604 /* *****************************************************************************
605 * SOFTWARE API FOR SPI
606 ***************************************************************************** */
607 /**---------------------------------------------------------------------------- */
608 /** \fn AT91F_SPI_Open */
609 /** \brief Open a SPI Port */
610 /**---------------------------------------------------------------------------- */
AT91F_SPI_Open(const unsigned int null)611 __inline unsigned int AT91F_SPI_Open( const unsigned int null ) /* \arg */
612 {
613 /* NOT DEFINED AT THIS MOMENT */
614 return( 0 );
615 }
616
617 /**---------------------------------------------------------------------------- */
618 /** \fn AT91F_SPI_CfgCs */
619 /** \brief Configure SPI chip select register */
620 /**---------------------------------------------------------------------------- */
AT91F_SPI_CfgCs(AT91PS_SPI pSPI,int cs,int val)621 __inline void AT91F_SPI_CfgCs( AT91PS_SPI pSPI, /* pointer to a SPI controller */
622 int cs, /* SPI cs number (0 to 3) */
623 int val ) /* chip select register */
624 {
625 /** Write to the CSR register */
626 *( pSPI->SPI_CSR + cs ) = val;
627 }
628
629 /**---------------------------------------------------------------------------- */
630 /** \fn AT91F_SPI_EnableIt */
631 /** \brief Enable SPI interrupt */
632 /**---------------------------------------------------------------------------- */
AT91F_SPI_EnableIt(AT91PS_SPI pSPI,unsigned int flag)633 __inline void AT91F_SPI_EnableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
634 unsigned int flag ) /* IT to be enabled */
635 {
636 /** Write to the IER register */
637 pSPI->SPI_IER = flag;
638 }
639
640 /**---------------------------------------------------------------------------- */
641 /** \fn AT91F_SPI_DisableIt */
642 /** \brief Disable SPI interrupt */
643 /**---------------------------------------------------------------------------- */
AT91F_SPI_DisableIt(AT91PS_SPI pSPI,unsigned int flag)644 __inline void AT91F_SPI_DisableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */
645 unsigned int flag ) /* IT to be disabled */
646 {
647 /** Write to the IDR register */
648 pSPI->SPI_IDR = flag;
649 }
650
651 /**---------------------------------------------------------------------------- */
652 /** \fn AT91F_SPI_Reset */
653 /** \brief Reset the SPI controller */
654 /**---------------------------------------------------------------------------- */
AT91F_SPI_Reset(AT91PS_SPI pSPI)655 __inline void AT91F_SPI_Reset( AT91PS_SPI pSPI /* pointer to a SPI controller */
656 )
657 {
658 /** Write to the CR register */
659 pSPI->SPI_CR = AT91C_SPI_SWRST;
660 }
661
662 /**---------------------------------------------------------------------------- */
663 /** \fn AT91F_SPI_Enable */
664 /** \brief Enable the SPI controller */
665 /**---------------------------------------------------------------------------- */
AT91F_SPI_Enable(AT91PS_SPI pSPI)666 __inline void AT91F_SPI_Enable( AT91PS_SPI pSPI /* pointer to a SPI controller */
667 )
668 {
669 /** Write to the CR register */
670 pSPI->SPI_CR = AT91C_SPI_SPIEN;
671 }
672
673 /**---------------------------------------------------------------------------- */
674 /** \fn AT91F_SPI_Disable */
675 /** \brief Disable the SPI controller */
676 /**---------------------------------------------------------------------------- */
AT91F_SPI_Disable(AT91PS_SPI pSPI)677 __inline void AT91F_SPI_Disable( AT91PS_SPI pSPI /* pointer to a SPI controller */
678 )
679 {
680 /** Write to the CR register */
681 pSPI->SPI_CR = AT91C_SPI_SPIDIS;
682 }
683
684 /**---------------------------------------------------------------------------- */
685 /** \fn AT91F_SPI_CfgMode */
686 /** \brief Enable the SPI controller */
687 /**---------------------------------------------------------------------------- */
AT91F_SPI_CfgMode(AT91PS_SPI pSPI,int mode)688 __inline void AT91F_SPI_CfgMode( AT91PS_SPI pSPI, /* pointer to a SPI controller */
689 int mode ) /* mode register */
690 {
691 /** Write to the MR register */
692 pSPI->SPI_MR = mode;
693 }
694
695 /**---------------------------------------------------------------------------- */
696 /** \fn AT91F_SPI_CfgPCS */
697 /** \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected */
698 /**---------------------------------------------------------------------------- */
AT91F_SPI_CfgPCS(AT91PS_SPI pSPI,char PCS_Device)699 __inline void AT91F_SPI_CfgPCS( AT91PS_SPI pSPI, /* pointer to a SPI controller */
700 char PCS_Device ) /* PCS of the Device */
701 {
702 /** Write to the MR register */
703 pSPI->SPI_MR &= 0xFFF0FFFF;
704 pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS );
705 }
706
707 /**---------------------------------------------------------------------------- */
708 /** \fn AT91F_SPI_ReceiveFrame */
709 /** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
710 /**---------------------------------------------------------------------------- */
AT91F_SPI_ReceiveFrame(AT91PS_SPI pSPI,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)711 __inline unsigned int AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI,
712 char * pBuffer,
713 unsigned int szBuffer,
714 char * pNextBuffer,
715 unsigned int szNextBuffer )
716 {
717 return AT91F_PDC_ReceiveFrame(
718 ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
719 pBuffer,
720 szBuffer,
721 pNextBuffer,
722 szNextBuffer );
723 }
724
725 /**---------------------------------------------------------------------------- */
726 /** \fn AT91F_SPI_SendFrame */
727 /** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is bSPIy */
728 /**---------------------------------------------------------------------------- */
AT91F_SPI_SendFrame(AT91PS_SPI pSPI,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)729 __inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI,
730 char * pBuffer,
731 unsigned int szBuffer,
732 char * pNextBuffer,
733 unsigned int szNextBuffer )
734 {
735 return AT91F_PDC_SendFrame(
736 ( AT91PS_PDC ) &( pSPI->SPI_RPR ),
737 pBuffer,
738 szBuffer,
739 pNextBuffer,
740 szNextBuffer );
741 }
742
743 /**---------------------------------------------------------------------------- */
744 /** \fn AT91F_SPI_Close */
745 /** \brief Close SPI: disable IT disable transfert, close PDC */
746 /**---------------------------------------------------------------------------- */
AT91F_SPI_Close(AT91PS_SPI pSPI)747 __inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */
748 {
749 /** Reset all the Chip Select register */
750 pSPI->SPI_CSR[ 0 ] = 0;
751 pSPI->SPI_CSR[ 1 ] = 0;
752 pSPI->SPI_CSR[ 2 ] = 0;
753 pSPI->SPI_CSR[ 3 ] = 0;
754
755 /** Reset the SPI mode */
756 pSPI->SPI_MR = 0;
757
758 /** Disable all interrupts */
759 pSPI->SPI_IDR = 0xFFFFFFFF;
760
761 /** Abort the Peripheral Data Transfers */
762 AT91F_PDC_Close( ( AT91PS_PDC ) &( pSPI->SPI_RPR ) );
763
764 /** Disable receiver and transmitter and stop any activity immediately */
765 pSPI->SPI_CR = AT91C_SPI_SPIDIS;
766 }
767
768 /**---------------------------------------------------------------------------- */
769 /** \fn AT91F_SPI_PutChar */
770 /** \brief Send a character,does not check if ready to send */
771 /**---------------------------------------------------------------------------- */
AT91F_SPI_PutChar(AT91PS_SPI pSPI,unsigned int character,unsigned int cs_number)772 __inline void AT91F_SPI_PutChar( AT91PS_SPI pSPI,
773 unsigned int character,
774 unsigned int cs_number )
775 {
776 unsigned int value_for_cs;
777
778 value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */
779 pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 );
780 }
781
782 /**---------------------------------------------------------------------------- */
783 /** \fn AT91F_SPI_GetChar */
784 /** \brief Receive a character,does not check if a character is available */
785 /**---------------------------------------------------------------------------- */
AT91F_SPI_GetChar(const AT91PS_SPI pSPI)786 __inline int AT91F_SPI_GetChar( const AT91PS_SPI pSPI )
787 {
788 return( ( pSPI->SPI_RDR ) & 0xFFFF );
789 }
790
791 /**---------------------------------------------------------------------------- */
792 /** \fn AT91F_SPI_GetInterruptMaskStatus */
793 /** \brief Return SPI Interrupt Mask Status */
794 /**---------------------------------------------------------------------------- */
AT91F_SPI_GetInterruptMaskStatus(AT91PS_SPI pSpi)795 __inline unsigned int AT91F_SPI_GetInterruptMaskStatus( /* \return SPI Interrupt Mask Status */
796 AT91PS_SPI pSpi ) /* \arg pointer to a SPI controller */
797 {
798 return pSpi->SPI_IMR;
799 }
800
801 /**---------------------------------------------------------------------------- */
802 /** \fn AT91F_SPI_IsInterruptMasked */
803 /** \brief Test if SPI Interrupt is Masked */
804 /**---------------------------------------------------------------------------- */
AT91F_SPI_IsInterruptMasked(AT91PS_SPI pSpi,unsigned int flag)805 __inline int AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, /* \arg pointer to a SPI controller */
806 unsigned int flag ) /* \arg flag to be tested */
807 {
808 return( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag );
809 }
810
811 /* *****************************************************************************
812 * SOFTWARE API FOR PWMC
813 ***************************************************************************** */
814 /**---------------------------------------------------------------------------- */
815 /** \fn AT91F_PWM_GetStatus */
816 /** \brief Return PWM Interrupt Status */
817 /**---------------------------------------------------------------------------- */
AT91F_PWMC_GetStatus(AT91PS_PWMC pPWM)818 __inline unsigned int AT91F_PWMC_GetStatus( /* \return PWM Interrupt Status */
819 AT91PS_PWMC pPWM ) /* pointer to a PWM controller */
820 {
821 return pPWM->PWMC_SR;
822 }
823
824 /**---------------------------------------------------------------------------- */
825 /** \fn AT91F_PWM_InterruptEnable */
826 /** \brief Enable PWM Interrupt */
827 /**---------------------------------------------------------------------------- */
AT91F_PWMC_InterruptEnable(AT91PS_PWMC pPwm,unsigned int flag)828 __inline void AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
829 unsigned int flag ) /* \arg PWM interrupt to be enabled */
830 {
831 pPwm->PWMC_IER = flag;
832 }
833
834 /**---------------------------------------------------------------------------- */
835 /** \fn AT91F_PWM_InterruptDisable */
836 /** \brief Disable PWM Interrupt */
837 /**---------------------------------------------------------------------------- */
AT91F_PWMC_InterruptDisable(AT91PS_PWMC pPwm,unsigned int flag)838 __inline void AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */
839 unsigned int flag ) /* \arg PWM interrupt to be disabled */
840 {
841 pPwm->PWMC_IDR = flag;
842 }
843
844 /**---------------------------------------------------------------------------- */
845 /** \fn AT91F_PWM_GetInterruptMaskStatus */
846 /** \brief Return PWM Interrupt Mask Status */
847 /**---------------------------------------------------------------------------- */
AT91F_PWMC_GetInterruptMaskStatus(AT91PS_PWMC pPwm)848 __inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( /* \return PWM Interrupt Mask Status */
849 AT91PS_PWMC pPwm ) /* \arg pointer to a PWM controller */
850 {
851 return pPwm->PWMC_IMR;
852 }
853
854 /**---------------------------------------------------------------------------- */
855 /** \fn AT91F_PWM_IsInterruptMasked */
856 /** \brief Test if PWM Interrupt is Masked */
857 /**---------------------------------------------------------------------------- */
AT91F_PWMC_IsInterruptMasked(AT91PS_PWMC pPWM,unsigned int flag)858 __inline unsigned int AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
859 unsigned int flag ) /* \arg flag to be tested */
860 {
861 return( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag );
862 }
863
864 /**---------------------------------------------------------------------------- */
865 /** \fn AT91F_PWM_IsStatusSet */
866 /** \brief Test if PWM Interrupt is Set */
867 /**---------------------------------------------------------------------------- */
AT91F_PWMC_IsStatusSet(AT91PS_PWMC pPWM,unsigned int flag)868 __inline unsigned int AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
869 unsigned int flag ) /* \arg flag to be tested */
870 {
871 return( AT91F_PWMC_GetStatus( pPWM ) & flag );
872 }
873
874 /**---------------------------------------------------------------------------- */
875 /** \fn AT91F_PWM_CfgChannel */
876 /** \brief Test if PWM Interrupt is Set */
877 /**---------------------------------------------------------------------------- */
AT91F_PWMC_CfgChannel(AT91PS_PWMC pPWM,unsigned int channelId,unsigned int mode,unsigned int period,unsigned int duty)878 __inline void AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
879 unsigned int channelId, /* \arg PWM channel ID */
880 unsigned int mode, /* \arg PWM mode */
881 unsigned int period, /* \arg PWM period */
882 unsigned int duty ) /* \arg PWM duty cycle */
883 {
884 pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode;
885 pPWM->PWMC_CH[ channelId ].PWMC_CDTYR = duty;
886 pPWM->PWMC_CH[ channelId ].PWMC_CPRDR = period;
887 }
888
889 /**---------------------------------------------------------------------------- */
890 /** \fn AT91F_PWM_StartChannel */
891 /** \brief Enable channel */
892 /**---------------------------------------------------------------------------- */
AT91F_PWMC_StartChannel(AT91PS_PWMC pPWM,unsigned int flag)893 __inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
894 unsigned int flag ) /* \arg Channels IDs to be enabled */
895 {
896 pPWM->PWMC_ENA = flag;
897 }
898
899 /**---------------------------------------------------------------------------- */
900 /** \fn AT91F_PWM_StopChannel */
901 /** \brief Disable channel */
902 /**---------------------------------------------------------------------------- */
AT91F_PWMC_StopChannel(AT91PS_PWMC pPWM,unsigned int flag)903 __inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
904 unsigned int flag ) /* \arg Channels IDs to be enabled */
905 {
906 pPWM->PWMC_DIS = flag;
907 }
908
909 /**---------------------------------------------------------------------------- */
910 /** \fn AT91F_PWM_UpdateChannel */
911 /** \brief Update Period or Duty Cycle */
912 /**---------------------------------------------------------------------------- */
AT91F_PWMC_UpdateChannel(AT91PS_PWMC pPWM,unsigned int channelId,unsigned int update)913 __inline void AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */
914 unsigned int channelId, /* \arg PWM channel ID */
915 unsigned int update ) /* \arg Channels IDs to be enabled */
916 {
917 pPWM->PWMC_CH[ channelId ].PWMC_CUPDR = update;
918 }
919
920 /* *****************************************************************************
921 * SOFTWARE API FOR TC
922 ***************************************************************************** */
923 /**---------------------------------------------------------------------------- */
924 /** \fn AT91F_TC_InterruptEnable */
925 /** \brief Enable TC Interrupt */
926 /**---------------------------------------------------------------------------- */
AT91F_TC_InterruptEnable(AT91PS_TC pTc,unsigned int flag)927 __inline void AT91F_TC_InterruptEnable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
928 unsigned int flag ) /* \arg TC interrupt to be enabled */
929 {
930 pTc->TC_IER = flag;
931 }
932
933 /**---------------------------------------------------------------------------- */
934 /** \fn AT91F_TC_InterruptDisable */
935 /** \brief Disable TC Interrupt */
936 /**---------------------------------------------------------------------------- */
AT91F_TC_InterruptDisable(AT91PS_TC pTc,unsigned int flag)937 __inline void AT91F_TC_InterruptDisable( AT91PS_TC pTc, /* \arg pointer to a TC controller */
938 unsigned int flag ) /* \arg TC interrupt to be disabled */
939 {
940 pTc->TC_IDR = flag;
941 }
942
943 /**---------------------------------------------------------------------------- */
944 /** \fn AT91F_TC_GetInterruptMaskStatus */
945 /** \brief Return TC Interrupt Mask Status */
946 /**---------------------------------------------------------------------------- */
AT91F_TC_GetInterruptMaskStatus(AT91PS_TC pTc)947 __inline unsigned int AT91F_TC_GetInterruptMaskStatus( /* \return TC Interrupt Mask Status */
948 AT91PS_TC pTc ) /* \arg pointer to a TC controller */
949 {
950 return pTc->TC_IMR;
951 }
952
953 /**---------------------------------------------------------------------------- */
954 /** \fn AT91F_TC_IsInterruptMasked */
955 /** \brief Test if TC Interrupt is Masked */
956 /**---------------------------------------------------------------------------- */
AT91F_TC_IsInterruptMasked(AT91PS_TC pTc,unsigned int flag)957 __inline int AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, /* \arg pointer to a TC controller */
958 unsigned int flag ) /* \arg flag to be tested */
959 {
960 return( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag );
961 }
962
963 /* *****************************************************************************
964 * SOFTWARE API FOR PMC
965 ***************************************************************************** */
966 /**---------------------------------------------------------------------------- */
967 /** \fn AT91F_PMC_CfgSysClkEnableReg */
968 /** \brief Configure the System Clock Enable Register of the PMC controller */
969 /**---------------------------------------------------------------------------- */
AT91F_PMC_CfgSysClkEnableReg(AT91PS_PMC pPMC,unsigned int mode)970 __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
971 unsigned int mode )
972 {
973 /** Write to the SCER register */
974 pPMC->PMC_SCER = mode;
975 }
976
977 /**---------------------------------------------------------------------------- */
978 /** \fn AT91F_PMC_CfgSysClkDisableReg */
979 /** \brief Configure the System Clock Disable Register of the PMC controller */
980 /**---------------------------------------------------------------------------- */
AT91F_PMC_CfgSysClkDisableReg(AT91PS_PMC pPMC,unsigned int mode)981 __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
982 unsigned int mode )
983 {
984 /** Write to the SCDR register */
985 pPMC->PMC_SCDR = mode;
986 }
987
988 /**---------------------------------------------------------------------------- */
989 /** \fn AT91F_PMC_GetSysClkStatusReg */
990 /** \brief Return the System Clock Status Register of the PMC controller */
991 /**---------------------------------------------------------------------------- */
AT91F_PMC_GetSysClkStatusReg(AT91PS_PMC pPMC)992 __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */
993 )
994 {
995 return pPMC->PMC_SCSR;
996 }
997
998 /**---------------------------------------------------------------------------- */
999 /** \fn AT91F_PMC_EnablePeriphClock */
1000 /** \brief Enable peripheral clock */
1001 /**---------------------------------------------------------------------------- */
AT91F_PMC_EnablePeriphClock(AT91PS_PMC pPMC,unsigned int periphIds)1002 __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
1003 unsigned int periphIds ) /* \arg IDs of peripherals to enable */
1004 {
1005 pPMC->PMC_PCER = periphIds;
1006 }
1007
1008 /**---------------------------------------------------------------------------- */
1009 /** \fn AT91F_PMC_DisablePeriphClock */
1010 /** \brief Disable peripheral clock */
1011 /**---------------------------------------------------------------------------- */
AT91F_PMC_DisablePeriphClock(AT91PS_PMC pPMC,unsigned int periphIds)1012 __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
1013 unsigned int periphIds ) /* \arg IDs of peripherals to enable */
1014 {
1015 pPMC->PMC_PCDR = periphIds;
1016 }
1017
1018 /**---------------------------------------------------------------------------- */
1019 /** \fn AT91F_PMC_GetPeriphClock */
1020 /** \brief Get peripheral clock status */
1021 /**---------------------------------------------------------------------------- */
AT91F_PMC_GetPeriphClock(AT91PS_PMC pPMC)1022 __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
1023 {
1024 return pPMC->PMC_PCSR;
1025 }
1026
1027 /**---------------------------------------------------------------------------- */
1028 /** \fn AT91F_CKGR_CfgMainOscillatorReg */
1029 /** \brief Cfg the main oscillator */
1030 /**---------------------------------------------------------------------------- */
AT91F_CKGR_CfgMainOscillatorReg(AT91PS_CKGR pCKGR,unsigned int mode)1031 __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
1032 unsigned int mode )
1033 {
1034 pCKGR->CKGR_MOR = mode;
1035 }
1036
1037 /**---------------------------------------------------------------------------- */
1038 /** \fn AT91F_CKGR_GetMainOscillatorReg */
1039 /** \brief Cfg the main oscillator */
1040 /**---------------------------------------------------------------------------- */
AT91F_CKGR_GetMainOscillatorReg(AT91PS_CKGR pCKGR)1041 __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
1042 {
1043 return pCKGR->CKGR_MOR;
1044 }
1045
1046 /**---------------------------------------------------------------------------- */
1047 /** \fn AT91F_CKGR_EnableMainOscillator */
1048 /** \brief Enable the main oscillator */
1049 /**---------------------------------------------------------------------------- */
AT91F_CKGR_EnableMainOscillator(AT91PS_CKGR pCKGR)1050 __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
1051 {
1052 pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
1053 }
1054
1055 /**---------------------------------------------------------------------------- */
1056 /** \fn AT91F_CKGR_DisableMainOscillator */
1057 /** \brief Disable the main oscillator */
1058 /**---------------------------------------------------------------------------- */
AT91F_CKGR_DisableMainOscillator(AT91PS_CKGR pCKGR)1059 __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
1060 {
1061 pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
1062 }
1063
1064 /**---------------------------------------------------------------------------- */
1065 /** \fn AT91F_CKGR_CfgMainOscStartUpTime */
1066 /** \brief Cfg MOR Register according to the main osc startup time */
1067 /**---------------------------------------------------------------------------- */
AT91F_CKGR_CfgMainOscStartUpTime(AT91PS_CKGR pCKGR,unsigned int startup_time,unsigned int slowClock)1068 __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
1069 unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
1070 unsigned int slowClock ) /* \arg slowClock in Hz */
1071 {
1072 pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
1073 pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8;
1074 }
1075
1076 /**---------------------------------------------------------------------------- */
1077 /** \fn AT91F_CKGR_GetMainClockFreqReg */
1078 /** \brief Cfg the main oscillator */
1079 /**---------------------------------------------------------------------------- */
AT91F_CKGR_GetMainClockFreqReg(AT91PS_CKGR pCKGR)1080 __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */
1081 {
1082 return pCKGR->CKGR_MCFR;
1083 }
1084
1085 /**---------------------------------------------------------------------------- */
1086 /** \fn AT91F_CKGR_GetMainClock */
1087 /** \brief Return Main clock in Hz */
1088 /**---------------------------------------------------------------------------- */
AT91F_CKGR_GetMainClock(AT91PS_CKGR pCKGR,unsigned int slowClock)1089 __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
1090 unsigned int slowClock ) /* \arg slowClock in Hz */
1091 {
1092 return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4;
1093 }
1094
1095 /**---------------------------------------------------------------------------- */
1096 /** \fn AT91F_PMC_CfgMCKReg */
1097 /** \brief Cfg Master Clock Register */
1098 /**---------------------------------------------------------------------------- */
AT91F_PMC_CfgMCKReg(AT91PS_PMC pPMC,unsigned int mode)1099 __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
1100 unsigned int mode )
1101 {
1102 pPMC->PMC_MCKR = mode;
1103 }
1104
1105 /**---------------------------------------------------------------------------- */
1106 /** \fn AT91F_PMC_GetMCKReg */
1107 /** \brief Return Master Clock Register */
1108 /**---------------------------------------------------------------------------- */
AT91F_PMC_GetMCKReg(AT91PS_PMC pPMC)1109 __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */
1110 {
1111 return pPMC->PMC_MCKR;
1112 }
1113
1114 /**------------------------------------------------------------------------------ */
1115 /** \fn AT91F_PMC_GetMasterClock */
1116 /** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */
1117 /**------------------------------------------------------------------------------ */
AT91F_PMC_GetMasterClock(AT91PS_PMC pPMC,AT91PS_CKGR pCKGR,unsigned int slowClock)1118 __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
1119 AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
1120 unsigned int slowClock ) /* \arg slowClock in Hz */
1121 {
1122 unsigned int reg = pPMC->PMC_MCKR;
1123 unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) );
1124 unsigned int pllDivider, pllMultiplier;
1125
1126 switch( reg & AT91C_PMC_CSS )
1127 {
1128 case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */
1129 return slowClock / prescaler;
1130
1131 case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */
1132 return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler;
1133
1134 case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */
1135 reg = pCKGR->CKGR_PLLR;
1136 pllDivider = ( reg & AT91C_CKGR_DIV );
1137 pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1;
1138 return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler;
1139 }
1140
1141 return 0;
1142 }
1143
1144 /**---------------------------------------------------------------------------- */
1145 /** \fn AT91F_PMC_EnablePCK */
1146 /** \brief Enable peripheral clock */
1147 /**---------------------------------------------------------------------------- */
AT91F_PMC_EnablePCK(AT91PS_PMC pPMC,unsigned int pck,unsigned int mode)1148 __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
1149 unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */
1150 unsigned int mode )
1151 {
1152 pPMC->PMC_PCKR[ pck ] = mode;
1153 pPMC->PMC_SCER = ( 1 << pck ) << 8;
1154 }
1155
1156 /**---------------------------------------------------------------------------- */
1157 /** \fn AT91F_PMC_DisablePCK */
1158 /** \brief Enable peripheral clock */
1159 /**---------------------------------------------------------------------------- */
AT91F_PMC_DisablePCK(AT91PS_PMC pPMC,unsigned int pck)1160 __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */
1161 unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */
1162 {
1163 pPMC->PMC_SCDR = ( 1 << pck ) << 8;
1164 }
1165
1166 /**---------------------------------------------------------------------------- */
1167 /** \fn AT91F_PMC_EnableIt */
1168 /** \brief Enable PMC interrupt */
1169 /**---------------------------------------------------------------------------- */
AT91F_PMC_EnableIt(AT91PS_PMC pPMC,unsigned int flag)1170 __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
1171 unsigned int flag ) /* IT to be enabled */
1172 {
1173 /** Write to the IER register */
1174 pPMC->PMC_IER = flag;
1175 }
1176
1177 /**---------------------------------------------------------------------------- */
1178 /** \fn AT91F_PMC_DisableIt */
1179 /** \brief Disable PMC interrupt */
1180 /**---------------------------------------------------------------------------- */
AT91F_PMC_DisableIt(AT91PS_PMC pPMC,unsigned int flag)1181 __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */
1182 unsigned int flag ) /* IT to be disabled */
1183 {
1184 /** Write to the IDR register */
1185 pPMC->PMC_IDR = flag;
1186 }
1187
1188 /**---------------------------------------------------------------------------- */
1189 /** \fn AT91F_PMC_GetStatus */
1190 /** \brief Return PMC Interrupt Status */
1191 /**---------------------------------------------------------------------------- */
AT91F_PMC_GetStatus(AT91PS_PMC pPMC)1192 __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */
1193 AT91PS_PMC pPMC ) /* pointer to a PMC controller */
1194 {
1195 return pPMC->PMC_SR;
1196 }
1197
1198 /**---------------------------------------------------------------------------- */
1199 /** \fn AT91F_PMC_GetInterruptMaskStatus */
1200 /** \brief Return PMC Interrupt Mask Status */
1201 /**---------------------------------------------------------------------------- */
AT91F_PMC_GetInterruptMaskStatus(AT91PS_PMC pPMC)1202 __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */
1203 AT91PS_PMC pPMC ) /* pointer to a PMC controller */
1204 {
1205 return pPMC->PMC_IMR;
1206 }
1207
1208 /**---------------------------------------------------------------------------- */
1209 /** \fn AT91F_PMC_IsInterruptMasked */
1210 /** \brief Test if PMC Interrupt is Masked */
1211 /**---------------------------------------------------------------------------- */
AT91F_PMC_IsInterruptMasked(AT91PS_PMC pPMC,unsigned int flag)1212 __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
1213 unsigned int flag ) /* \arg flag to be tested */
1214 {
1215 return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag );
1216 }
1217
1218 /**---------------------------------------------------------------------------- */
1219 /** \fn AT91F_PMC_IsStatusSet */
1220 /** \brief Test if PMC Status is Set */
1221 /**---------------------------------------------------------------------------- */
AT91F_PMC_IsStatusSet(AT91PS_PMC pPMC,unsigned int flag)1222 __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */
1223 unsigned int flag ) /* \arg flag to be tested */
1224 {
1225 return( AT91F_PMC_GetStatus( pPMC ) & flag );
1226 } /* *****************************************************************************
1227 * SOFTWARE API FOR ADC
1228 ***************************************************************************** */
1229 /**---------------------------------------------------------------------------- */
1230 /** \fn AT91F_ADC_EnableIt */
1231 /** \brief Enable ADC interrupt */
1232 /**---------------------------------------------------------------------------- */
AT91F_ADC_EnableIt(AT91PS_ADC pADC,unsigned int flag)1233 __inline void AT91F_ADC_EnableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
1234 unsigned int flag ) /* IT to be enabled */
1235 {
1236 /** Write to the IER register */
1237 pADC->ADC_IER = flag;
1238 }
1239
1240 /**---------------------------------------------------------------------------- */
1241 /** \fn AT91F_ADC_DisableIt */
1242 /** \brief Disable ADC interrupt */
1243 /**---------------------------------------------------------------------------- */
AT91F_ADC_DisableIt(AT91PS_ADC pADC,unsigned int flag)1244 __inline void AT91F_ADC_DisableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */
1245 unsigned int flag ) /* IT to be disabled */
1246 {
1247 /** Write to the IDR register */
1248 pADC->ADC_IDR = flag;
1249 }
1250
1251 /**---------------------------------------------------------------------------- */
1252 /** \fn AT91F_ADC_GetStatus */
1253 /** \brief Return ADC Interrupt Status */
1254 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetStatus(AT91PS_ADC pADC)1255 __inline unsigned int AT91F_ADC_GetStatus( /* \return ADC Interrupt Status */
1256 AT91PS_ADC pADC ) /* pointer to a ADC controller */
1257 {
1258 return pADC->ADC_SR;
1259 }
1260
1261 /**---------------------------------------------------------------------------- */
1262 /** \fn AT91F_ADC_GetInterruptMaskStatus */
1263 /** \brief Return ADC Interrupt Mask Status */
1264 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetInterruptMaskStatus(AT91PS_ADC pADC)1265 __inline unsigned int AT91F_ADC_GetInterruptMaskStatus( /* \return ADC Interrupt Mask Status */
1266 AT91PS_ADC pADC ) /* pointer to a ADC controller */
1267 {
1268 return pADC->ADC_IMR;
1269 }
1270
1271 /**---------------------------------------------------------------------------- */
1272 /** \fn AT91F_ADC_IsInterruptMasked */
1273 /** \brief Test if ADC Interrupt is Masked */
1274 /**---------------------------------------------------------------------------- */
AT91F_ADC_IsInterruptMasked(AT91PS_ADC pADC,unsigned int flag)1275 __inline unsigned int AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
1276 unsigned int flag ) /* \arg flag to be tested */
1277 {
1278 return( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag );
1279 }
1280
1281 /**---------------------------------------------------------------------------- */
1282 /** \fn AT91F_ADC_IsStatusSet */
1283 /** \brief Test if ADC Status is Set */
1284 /**---------------------------------------------------------------------------- */
AT91F_ADC_IsStatusSet(AT91PS_ADC pADC,unsigned int flag)1285 __inline unsigned int AT91F_ADC_IsStatusSet( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */
1286 unsigned int flag ) /* \arg flag to be tested */
1287 {
1288 return( AT91F_ADC_GetStatus( pADC ) & flag );
1289 }
1290
1291 /**---------------------------------------------------------------------------- */
1292 /** \fn AT91F_ADC_CfgModeReg */
1293 /** \brief Configure the Mode Register of the ADC controller */
1294 /**---------------------------------------------------------------------------- */
AT91F_ADC_CfgModeReg(AT91PS_ADC pADC,unsigned int mode)1295 __inline void AT91F_ADC_CfgModeReg( AT91PS_ADC pADC, /* pointer to a ADC controller */
1296 unsigned int mode ) /* mode register */
1297 {
1298 /** Write to the MR register */
1299 pADC->ADC_MR = mode;
1300 }
1301
1302 /**---------------------------------------------------------------------------- */
1303 /** \fn AT91F_ADC_GetModeReg */
1304 /** \brief Return the Mode Register of the ADC controller value */
1305 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetModeReg(AT91PS_ADC pADC)1306 __inline unsigned int AT91F_ADC_GetModeReg( AT91PS_ADC pADC /* pointer to a ADC controller */
1307 )
1308 {
1309 return pADC->ADC_MR;
1310 }
1311
1312 /**---------------------------------------------------------------------------- */
1313 /** \fn AT91F_ADC_CfgTimings */
1314 /** \brief Configure the different necessary timings of the ADC controller */
1315 /**---------------------------------------------------------------------------- */
AT91F_ADC_CfgTimings(AT91PS_ADC pADC,unsigned int mck_clock,unsigned int adc_clock,unsigned int startup_time,unsigned int sample_and_hold_time)1316 __inline void AT91F_ADC_CfgTimings( AT91PS_ADC pADC, /* pointer to a ADC controller */
1317 unsigned int mck_clock, /* in MHz */
1318 unsigned int adc_clock, /* in MHz */
1319 unsigned int startup_time, /* in us */
1320 unsigned int sample_and_hold_time ) /* in ns */
1321 {
1322 unsigned int prescal, startup, shtim;
1323
1324 prescal = mck_clock / ( 2 * adc_clock ) - 1;
1325 startup = adc_clock * startup_time / 8 - 1;
1326 shtim = adc_clock * sample_and_hold_time / 1000 - 1;
1327
1328 /** Write to the MR register */
1329 pADC->ADC_MR = ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & AT91C_ADC_SHTIM );
1330 }
1331
1332 /**---------------------------------------------------------------------------- */
1333 /** \fn AT91F_ADC_EnableChannel */
1334 /** \brief Return ADC Timer Register Value */
1335 /**---------------------------------------------------------------------------- */
AT91F_ADC_EnableChannel(AT91PS_ADC pADC,unsigned int channel)1336 __inline void AT91F_ADC_EnableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
1337 unsigned int channel ) /* mode register */
1338 {
1339 /** Write to the CHER register */
1340 pADC->ADC_CHER = channel;
1341 }
1342
1343 /**---------------------------------------------------------------------------- */
1344 /** \fn AT91F_ADC_DisableChannel */
1345 /** \brief Return ADC Timer Register Value */
1346 /**---------------------------------------------------------------------------- */
AT91F_ADC_DisableChannel(AT91PS_ADC pADC,unsigned int channel)1347 __inline void AT91F_ADC_DisableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */
1348 unsigned int channel ) /* mode register */
1349 {
1350 /** Write to the CHDR register */
1351 pADC->ADC_CHDR = channel;
1352 }
1353
1354 /**---------------------------------------------------------------------------- */
1355 /** \fn AT91F_ADC_GetChannelStatus */
1356 /** \brief Return ADC Timer Register Value */
1357 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetChannelStatus(AT91PS_ADC pADC)1358 __inline unsigned int AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC /* pointer to a ADC controller */
1359 )
1360 {
1361 return pADC->ADC_CHSR;
1362 }
1363
1364 /**---------------------------------------------------------------------------- */
1365 /** \fn AT91F_ADC_StartConversion */
1366 /** \brief Software request for a analog to digital conversion */
1367 /**---------------------------------------------------------------------------- */
AT91F_ADC_StartConversion(AT91PS_ADC pADC)1368 __inline void AT91F_ADC_StartConversion( AT91PS_ADC pADC /* pointer to a ADC controller */
1369 )
1370 {
1371 pADC->ADC_CR = AT91C_ADC_START;
1372 }
1373
1374 /**---------------------------------------------------------------------------- */
1375 /** \fn AT91F_ADC_SoftReset */
1376 /** \brief Software reset */
1377 /**---------------------------------------------------------------------------- */
AT91F_ADC_SoftReset(AT91PS_ADC pADC)1378 __inline void AT91F_ADC_SoftReset( AT91PS_ADC pADC /* pointer to a ADC controller */
1379 )
1380 {
1381 pADC->ADC_CR = AT91C_ADC_SWRST;
1382 }
1383
1384 /**---------------------------------------------------------------------------- */
1385 /** \fn AT91F_ADC_GetLastConvertedData */
1386 /** \brief Return the Last Converted Data */
1387 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetLastConvertedData(AT91PS_ADC pADC)1388 __inline unsigned int AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC /* pointer to a ADC controller */
1389 )
1390 {
1391 return pADC->ADC_LCDR;
1392 }
1393
1394 /**---------------------------------------------------------------------------- */
1395 /** \fn AT91F_ADC_GetConvertedDataCH0 */
1396 /** \brief Return the Channel 0 Converted Data */
1397 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetConvertedDataCH0(AT91PS_ADC pADC)1398 __inline unsigned int AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC /* pointer to a ADC controller */
1399 )
1400 {
1401 return pADC->ADC_CDR0;
1402 }
1403
1404 /**---------------------------------------------------------------------------- */
1405 /** \fn AT91F_ADC_GetConvertedDataCH1 */
1406 /** \brief Return the Channel 1 Converted Data */
1407 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetConvertedDataCH1(AT91PS_ADC pADC)1408 __inline unsigned int AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC /* pointer to a ADC controller */
1409 )
1410 {
1411 return pADC->ADC_CDR1;
1412 }
1413
1414 /**---------------------------------------------------------------------------- */
1415 /** \fn AT91F_ADC_GetConvertedDataCH2 */
1416 /** \brief Return the Channel 2 Converted Data */
1417 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetConvertedDataCH2(AT91PS_ADC pADC)1418 __inline unsigned int AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC /* pointer to a ADC controller */
1419 )
1420 {
1421 return pADC->ADC_CDR2;
1422 }
1423
1424 /**---------------------------------------------------------------------------- */
1425 /** \fn AT91F_ADC_GetConvertedDataCH3 */
1426 /** \brief Return the Channel 3 Converted Data */
1427 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetConvertedDataCH3(AT91PS_ADC pADC)1428 __inline unsigned int AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC /* pointer to a ADC controller */
1429 )
1430 {
1431 return pADC->ADC_CDR3;
1432 }
1433
1434 /**---------------------------------------------------------------------------- */
1435 /** \fn AT91F_ADC_GetConvertedDataCH4 */
1436 /** \brief Return the Channel 4 Converted Data */
1437 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetConvertedDataCH4(AT91PS_ADC pADC)1438 __inline unsigned int AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC /* pointer to a ADC controller */
1439 )
1440 {
1441 return pADC->ADC_CDR4;
1442 }
1443
1444 /**---------------------------------------------------------------------------- */
1445 /** \fn AT91F_ADC_GetConvertedDataCH5 */
1446 /** \brief Return the Channel 5 Converted Data */
1447 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetConvertedDataCH5(AT91PS_ADC pADC)1448 __inline unsigned int AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC /* pointer to a ADC controller */
1449 )
1450 {
1451 return pADC->ADC_CDR5;
1452 }
1453
1454 /**---------------------------------------------------------------------------- */
1455 /** \fn AT91F_ADC_GetConvertedDataCH6 */
1456 /** \brief Return the Channel 6 Converted Data */
1457 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetConvertedDataCH6(AT91PS_ADC pADC)1458 __inline unsigned int AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC /* pointer to a ADC controller */
1459 )
1460 {
1461 return pADC->ADC_CDR6;
1462 }
1463
1464 /**---------------------------------------------------------------------------- */
1465 /** \fn AT91F_ADC_GetConvertedDataCH7 */
1466 /** \brief Return the Channel 7 Converted Data */
1467 /**---------------------------------------------------------------------------- */
AT91F_ADC_GetConvertedDataCH7(AT91PS_ADC pADC)1468 __inline unsigned int AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC /* pointer to a ADC controller */
1469 )
1470 {
1471 return pADC->ADC_CDR7;
1472 }
1473
1474 /* *****************************************************************************
1475 * SOFTWARE API FOR PIO
1476 ***************************************************************************** */
1477 /**---------------------------------------------------------------------------- */
1478 /** \fn AT91F_PIO_CfgPeriph */
1479 /** \brief Enable pins to be derived by peripheral */
1480 /**---------------------------------------------------------------------------- */
AT91F_PIO_CfgPeriph(AT91PS_PIO pPio,unsigned int periphAEnable,unsigned int periphBEnable)1481 __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1482 unsigned int periphAEnable, /* \arg PERIPH A to enable */
1483 unsigned int periphBEnable ) /* \arg PERIPH B to enable */
1484
1485 {
1486 pPio->PIO_ASR = periphAEnable;
1487 pPio->PIO_BSR = periphBEnable;
1488 pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */
1489 }
1490
1491 /**---------------------------------------------------------------------------- */
1492 /** \fn AT91F_PIO_CfgOutput */
1493 /** \brief Enable PIO in output mode */
1494 /**---------------------------------------------------------------------------- */
AT91F_PIO_CfgOutput(AT91PS_PIO pPio,unsigned int pioEnable)1495 __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1496 unsigned int pioEnable ) /* \arg PIO to be enabled */
1497 {
1498 pPio->PIO_PER = pioEnable; /* Set in PIO mode */
1499 pPio->PIO_OER = pioEnable; /* Configure in Output */
1500 }
1501
1502 /**---------------------------------------------------------------------------- */
1503 /** \fn AT91F_PIO_CfgInput */
1504 /** \brief Enable PIO in input mode */
1505 /**---------------------------------------------------------------------------- */
AT91F_PIO_CfgInput(AT91PS_PIO pPio,unsigned int inputEnable)1506 __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1507 unsigned int inputEnable ) /* \arg PIO to be enabled */
1508 {
1509 /* Disable output */
1510 pPio->PIO_ODR = inputEnable;
1511 pPio->PIO_PER = inputEnable;
1512 }
1513
1514 /**---------------------------------------------------------------------------- */
1515 /** \fn AT91F_PIO_CfgOpendrain */
1516 /** \brief Configure PIO in open drain */
1517 /**---------------------------------------------------------------------------- */
AT91F_PIO_CfgOpendrain(AT91PS_PIO pPio,unsigned int multiDrvEnable)1518 __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1519 unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */
1520 {
1521 /* Configure the multi-drive option */
1522 pPio->PIO_MDDR = ~multiDrvEnable;
1523 pPio->PIO_MDER = multiDrvEnable;
1524 }
1525
1526 /**---------------------------------------------------------------------------- */
1527 /** \fn AT91F_PIO_CfgPullup */
1528 /** \brief Enable pullup on PIO */
1529 /**---------------------------------------------------------------------------- */
AT91F_PIO_CfgPullup(AT91PS_PIO pPio,unsigned int pullupEnable)1530 __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1531 unsigned int pullupEnable ) /* \arg enable pullup on PIO */
1532 {
1533 /* Connect or not Pullup */
1534 pPio->PIO_PPUDR = ~pullupEnable;
1535 pPio->PIO_PPUER = pullupEnable;
1536 }
1537
1538 /**---------------------------------------------------------------------------- */
1539 /** \fn AT91F_PIO_CfgDirectDrive */
1540 /** \brief Enable direct drive on PIO */
1541 /**---------------------------------------------------------------------------- */
AT91F_PIO_CfgDirectDrive(AT91PS_PIO pPio,unsigned int directDrive)1542 __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1543 unsigned int directDrive ) /* \arg PIO to be configured with direct drive */
1544
1545 {
1546 /* Configure the Direct Drive */
1547 pPio->PIO_OWDR = ~directDrive;
1548 pPio->PIO_OWER = directDrive;
1549 }
1550
1551 /**---------------------------------------------------------------------------- */
1552 /** \fn AT91F_PIO_CfgInputFilter */
1553 /** \brief Enable input filter on input PIO */
1554 /**---------------------------------------------------------------------------- */
AT91F_PIO_CfgInputFilter(AT91PS_PIO pPio,unsigned int inputFilter)1555 __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1556 unsigned int inputFilter ) /* \arg PIO to be configured with input filter */
1557
1558 {
1559 /* Configure the Direct Drive */
1560 pPio->PIO_IFDR = ~inputFilter;
1561 pPio->PIO_IFER = inputFilter;
1562 }
1563
1564 /**---------------------------------------------------------------------------- */
1565 /** \fn AT91F_PIO_GetInput */
1566 /** \brief Return PIO input value */
1567 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetInput(AT91PS_PIO pPio)1568 __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */
1569 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1570 {
1571 return pPio->PIO_PDSR;
1572 }
1573
1574 /**---------------------------------------------------------------------------- */
1575 /** \fn AT91F_PIO_IsInputSet */
1576 /** \brief Test if PIO is input flag is active */
1577 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsInputSet(AT91PS_PIO pPio,unsigned int flag)1578 __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1579 unsigned int flag ) /* \arg flag to be tested */
1580 {
1581 return( AT91F_PIO_GetInput( pPio ) & flag );
1582 }
1583
1584
1585 /**---------------------------------------------------------------------------- */
1586 /** \fn AT91F_PIO_SetOutput */
1587 /** \brief Set to 1 output PIO */
1588 /**---------------------------------------------------------------------------- */
AT91F_PIO_SetOutput(AT91PS_PIO pPio,unsigned int flag)1589 __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1590 unsigned int flag ) /* \arg output to be set */
1591 {
1592 pPio->PIO_SODR = flag;
1593 }
1594
1595 /**---------------------------------------------------------------------------- */
1596 /** \fn AT91F_PIO_ClearOutput */
1597 /** \brief Set to 0 output PIO */
1598 /**---------------------------------------------------------------------------- */
AT91F_PIO_ClearOutput(AT91PS_PIO pPio,unsigned int flag)1599 __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1600 unsigned int flag ) /* \arg output to be cleared */
1601 {
1602 pPio->PIO_CODR = flag;
1603 }
1604
1605 /**---------------------------------------------------------------------------- */
1606 /** \fn AT91F_PIO_ForceOutput */
1607 /** \brief Force output when Direct drive option is enabled */
1608 /**---------------------------------------------------------------------------- */
AT91F_PIO_ForceOutput(AT91PS_PIO pPio,unsigned int flag)1609 __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1610 unsigned int flag ) /* \arg output to be forced */
1611 {
1612 pPio->PIO_ODSR = flag;
1613 }
1614
1615 /**---------------------------------------------------------------------------- */
1616 /** \fn AT91F_PIO_Enable */
1617 /** \brief Enable PIO */
1618 /**---------------------------------------------------------------------------- */
AT91F_PIO_Enable(AT91PS_PIO pPio,unsigned int flag)1619 __inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1620 unsigned int flag ) /* \arg pio to be enabled */
1621 {
1622 pPio->PIO_PER = flag;
1623 }
1624
1625 /**---------------------------------------------------------------------------- */
1626 /** \fn AT91F_PIO_Disable */
1627 /** \brief Disable PIO */
1628 /**---------------------------------------------------------------------------- */
AT91F_PIO_Disable(AT91PS_PIO pPio,unsigned int flag)1629 __inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1630 unsigned int flag ) /* \arg pio to be disabled */
1631 {
1632 pPio->PIO_PDR = flag;
1633 }
1634
1635 /**---------------------------------------------------------------------------- */
1636 /** \fn AT91F_PIO_GetStatus */
1637 /** \brief Return PIO Status */
1638 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetStatus(AT91PS_PIO pPio)1639 __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */
1640 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1641 {
1642 return pPio->PIO_PSR;
1643 }
1644
1645 /**---------------------------------------------------------------------------- */
1646 /** \fn AT91F_PIO_IsSet */
1647 /** \brief Test if PIO is Set */
1648 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsSet(AT91PS_PIO pPio,unsigned int flag)1649 __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1650 unsigned int flag ) /* \arg flag to be tested */
1651 {
1652 return( AT91F_PIO_GetStatus( pPio ) & flag );
1653 }
1654
1655 /**---------------------------------------------------------------------------- */
1656 /** \fn AT91F_PIO_OutputEnable */
1657 /** \brief Output Enable PIO */
1658 /**---------------------------------------------------------------------------- */
AT91F_PIO_OutputEnable(AT91PS_PIO pPio,unsigned int flag)1659 __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1660 unsigned int flag ) /* \arg pio output to be enabled */
1661 {
1662 pPio->PIO_OER = flag;
1663 }
1664
1665 /**---------------------------------------------------------------------------- */
1666 /** \fn AT91F_PIO_OutputDisable */
1667 /** \brief Output Enable PIO */
1668 /**---------------------------------------------------------------------------- */
AT91F_PIO_OutputDisable(AT91PS_PIO pPio,unsigned int flag)1669 __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1670 unsigned int flag ) /* \arg pio output to be disabled */
1671 {
1672 pPio->PIO_ODR = flag;
1673 }
1674
1675 /**---------------------------------------------------------------------------- */
1676 /** \fn AT91F_PIO_GetOutputStatus */
1677 /** \brief Return PIO Output Status */
1678 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetOutputStatus(AT91PS_PIO pPio)1679 __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */
1680 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1681 {
1682 return pPio->PIO_OSR;
1683 }
1684
1685 /**---------------------------------------------------------------------------- */
1686 /** \fn AT91F_PIO_IsOuputSet */
1687 /** \brief Test if PIO Output is Set */
1688 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsOutputSet(AT91PS_PIO pPio,unsigned int flag)1689 __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1690 unsigned int flag ) /* \arg flag to be tested */
1691 {
1692 return( AT91F_PIO_GetOutputStatus( pPio ) & flag );
1693 }
1694
1695 /**---------------------------------------------------------------------------- */
1696 /** \fn AT91F_PIO_InputFilterEnable */
1697 /** \brief Input Filter Enable PIO */
1698 /**---------------------------------------------------------------------------- */
AT91F_PIO_InputFilterEnable(AT91PS_PIO pPio,unsigned int flag)1699 __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1700 unsigned int flag ) /* \arg pio input filter to be enabled */
1701 {
1702 pPio->PIO_IFER = flag;
1703 }
1704
1705 /**---------------------------------------------------------------------------- */
1706 /** \fn AT91F_PIO_InputFilterDisable */
1707 /** \brief Input Filter Disable PIO */
1708 /**---------------------------------------------------------------------------- */
AT91F_PIO_InputFilterDisable(AT91PS_PIO pPio,unsigned int flag)1709 __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1710 unsigned int flag ) /* \arg pio input filter to be disabled */
1711 {
1712 pPio->PIO_IFDR = flag;
1713 }
1714
1715 /**---------------------------------------------------------------------------- */
1716 /** \fn AT91F_PIO_GetInputFilterStatus */
1717 /** \brief Return PIO Input Filter Status */
1718 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetInputFilterStatus(AT91PS_PIO pPio)1719 __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */
1720 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1721 {
1722 return pPio->PIO_IFSR;
1723 }
1724
1725 /**---------------------------------------------------------------------------- */
1726 /** \fn AT91F_PIO_IsInputFilterSet */
1727 /** \brief Test if PIO Input filter is Set */
1728 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsInputFilterSet(AT91PS_PIO pPio,unsigned int flag)1729 __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1730 unsigned int flag ) /* \arg flag to be tested */
1731 {
1732 return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag );
1733 }
1734
1735 /**---------------------------------------------------------------------------- */
1736 /** \fn AT91F_PIO_GetOutputDataStatus */
1737 /** \brief Return PIO Output Data Status */
1738 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetOutputDataStatus(AT91PS_PIO pPio)1739 __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */
1740 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1741 {
1742 return pPio->PIO_ODSR;
1743 }
1744
1745 /**---------------------------------------------------------------------------- */
1746 /** \fn AT91F_PIO_InterruptEnable */
1747 /** \brief Enable PIO Interrupt */
1748 /**---------------------------------------------------------------------------- */
AT91F_PIO_InterruptEnable(AT91PS_PIO pPio,unsigned int flag)1749 __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1750 unsigned int flag ) /* \arg pio interrupt to be enabled */
1751 {
1752 pPio->PIO_IER = flag;
1753 }
1754
1755 /**---------------------------------------------------------------------------- */
1756 /** \fn AT91F_PIO_InterruptDisable */
1757 /** \brief Disable PIO Interrupt */
1758 /**---------------------------------------------------------------------------- */
AT91F_PIO_InterruptDisable(AT91PS_PIO pPio,unsigned int flag)1759 __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1760 unsigned int flag ) /* \arg pio interrupt to be disabled */
1761 {
1762 pPio->PIO_IDR = flag;
1763 }
1764
1765 /**---------------------------------------------------------------------------- */
1766 /** \fn AT91F_PIO_GetInterruptMaskStatus */
1767 /** \brief Return PIO Interrupt Mask Status */
1768 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetInterruptMaskStatus(AT91PS_PIO pPio)1769 __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */
1770 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1771 {
1772 return pPio->PIO_IMR;
1773 }
1774
1775 /**---------------------------------------------------------------------------- */
1776 /** \fn AT91F_PIO_GetInterruptStatus */
1777 /** \brief Return PIO Interrupt Status */
1778 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetInterruptStatus(AT91PS_PIO pPio)1779 __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */
1780 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1781 {
1782 return pPio->PIO_ISR;
1783 }
1784
1785 /**---------------------------------------------------------------------------- */
1786 /** \fn AT91F_PIO_IsInterruptMasked */
1787 /** \brief Test if PIO Interrupt is Masked */
1788 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsInterruptMasked(AT91PS_PIO pPio,unsigned int flag)1789 __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1790 unsigned int flag ) /* \arg flag to be tested */
1791 {
1792 return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag );
1793 }
1794
1795 /**---------------------------------------------------------------------------- */
1796 /** \fn AT91F_PIO_IsInterruptSet */
1797 /** \brief Test if PIO Interrupt is Set */
1798 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsInterruptSet(AT91PS_PIO pPio,unsigned int flag)1799 __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1800 unsigned int flag ) /* \arg flag to be tested */
1801 {
1802 return( AT91F_PIO_GetInterruptStatus( pPio ) & flag );
1803 }
1804
1805 /**---------------------------------------------------------------------------- */
1806 /** \fn AT91F_PIO_MultiDriverEnable */
1807 /** \brief Multi Driver Enable PIO */
1808 /**---------------------------------------------------------------------------- */
AT91F_PIO_MultiDriverEnable(AT91PS_PIO pPio,unsigned int flag)1809 __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1810 unsigned int flag ) /* \arg pio to be enabled */
1811 {
1812 pPio->PIO_MDER = flag;
1813 }
1814
1815 /**---------------------------------------------------------------------------- */
1816 /** \fn AT91F_PIO_MultiDriverDisable */
1817 /** \brief Multi Driver Disable PIO */
1818 /**---------------------------------------------------------------------------- */
AT91F_PIO_MultiDriverDisable(AT91PS_PIO pPio,unsigned int flag)1819 __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1820 unsigned int flag ) /* \arg pio to be disabled */
1821 {
1822 pPio->PIO_MDDR = flag;
1823 }
1824
1825 /**---------------------------------------------------------------------------- */
1826 /** \fn AT91F_PIO_GetMultiDriverStatus */
1827 /** \brief Return PIO Multi Driver Status */
1828 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetMultiDriverStatus(AT91PS_PIO pPio)1829 __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */
1830 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1831 {
1832 return pPio->PIO_MDSR;
1833 }
1834
1835 /**---------------------------------------------------------------------------- */
1836 /** \fn AT91F_PIO_IsMultiDriverSet */
1837 /** \brief Test if PIO MultiDriver is Set */
1838 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsMultiDriverSet(AT91PS_PIO pPio,unsigned int flag)1839 __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1840 unsigned int flag ) /* \arg flag to be tested */
1841 {
1842 return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag );
1843 }
1844
1845 /**---------------------------------------------------------------------------- */
1846 /** \fn AT91F_PIO_A_RegisterSelection */
1847 /** \brief PIO A Register Selection */
1848 /**---------------------------------------------------------------------------- */
AT91F_PIO_A_RegisterSelection(AT91PS_PIO pPio,unsigned int flag)1849 __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1850 unsigned int flag ) /* \arg pio A register selection */
1851 {
1852 pPio->PIO_ASR = flag;
1853 }
1854
1855 /**---------------------------------------------------------------------------- */
1856 /** \fn AT91F_PIO_B_RegisterSelection */
1857 /** \brief PIO B Register Selection */
1858 /**---------------------------------------------------------------------------- */
AT91F_PIO_B_RegisterSelection(AT91PS_PIO pPio,unsigned int flag)1859 __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1860 unsigned int flag ) /* \arg pio B register selection */
1861 {
1862 pPio->PIO_BSR = flag;
1863 }
1864
1865 /**---------------------------------------------------------------------------- */
1866 /** \fn AT91F_PIO_Get_AB_RegisterStatus */
1867 /** \brief Return PIO Interrupt Status */
1868 /**---------------------------------------------------------------------------- */
AT91F_PIO_Get_AB_RegisterStatus(AT91PS_PIO pPio)1869 __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */
1870 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1871 {
1872 return pPio->PIO_ABSR;
1873 }
1874
1875 /**---------------------------------------------------------------------------- */
1876 /** \fn AT91F_PIO_IsAB_RegisterSet */
1877 /** \brief Test if PIO AB Register is Set */
1878 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsAB_RegisterSet(AT91PS_PIO pPio,unsigned int flag)1879 __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1880 unsigned int flag ) /* \arg flag to be tested */
1881 {
1882 return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag );
1883 }
1884
1885 /**---------------------------------------------------------------------------- */
1886 /** \fn AT91F_PIO_OutputWriteEnable */
1887 /** \brief Output Write Enable PIO */
1888 /**---------------------------------------------------------------------------- */
AT91F_PIO_OutputWriteEnable(AT91PS_PIO pPio,unsigned int flag)1889 __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1890 unsigned int flag ) /* \arg pio output write to be enabled */
1891 {
1892 pPio->PIO_OWER = flag;
1893 }
1894
1895 /**---------------------------------------------------------------------------- */
1896 /** \fn AT91F_PIO_OutputWriteDisable */
1897 /** \brief Output Write Disable PIO */
1898 /**---------------------------------------------------------------------------- */
AT91F_PIO_OutputWriteDisable(AT91PS_PIO pPio,unsigned int flag)1899 __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1900 unsigned int flag ) /* \arg pio output write to be disabled */
1901 {
1902 pPio->PIO_OWDR = flag;
1903 }
1904
1905 /**---------------------------------------------------------------------------- */
1906 /** \fn AT91F_PIO_GetOutputWriteStatus */
1907 /** \brief Return PIO Output Write Status */
1908 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetOutputWriteStatus(AT91PS_PIO pPio)1909 __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */
1910 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1911 {
1912 return pPio->PIO_OWSR;
1913 }
1914
1915 /**---------------------------------------------------------------------------- */
1916 /** \fn AT91F_PIO_IsOutputWriteSet */
1917 /** \brief Test if PIO OutputWrite is Set */
1918 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsOutputWriteSet(AT91PS_PIO pPio,unsigned int flag)1919 __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1920 unsigned int flag ) /* \arg flag to be tested */
1921 {
1922 return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag );
1923 }
1924
1925 /**---------------------------------------------------------------------------- */
1926 /** \fn AT91F_PIO_GetCfgPullup */
1927 /** \brief Return PIO Configuration Pullup */
1928 /**---------------------------------------------------------------------------- */
AT91F_PIO_GetCfgPullup(AT91PS_PIO pPio)1929 __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */
1930 AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */
1931 {
1932 return pPio->PIO_PPUSR;
1933 }
1934
1935 /**---------------------------------------------------------------------------- */
1936 /** \fn AT91F_PIO_IsOutputDataStatusSet */
1937 /** \brief Test if PIO Output Data Status is Set */
1938 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsOutputDataStatusSet(AT91PS_PIO pPio,unsigned int flag)1939 __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1940 unsigned int flag ) /* \arg flag to be tested */
1941 {
1942 return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag );
1943 }
1944
1945 /**---------------------------------------------------------------------------- */
1946 /** \fn AT91F_PIO_IsCfgPullupStatusSet */
1947 /** \brief Test if PIO Configuration Pullup Status is Set */
1948 /**---------------------------------------------------------------------------- */
AT91F_PIO_IsCfgPullupStatusSet(AT91PS_PIO pPio,unsigned int flag)1949 __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */
1950 unsigned int flag ) /* \arg flag to be tested */
1951 {
1952 return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag );
1953 }
1954
1955 /* *****************************************************************************
1956 * SOFTWARE API FOR TWI
1957 ***************************************************************************** */
1958 /**---------------------------------------------------------------------------- */
1959 /** \fn AT91F_TWI_EnableIt */
1960 /** \brief Enable TWI IT */
1961 /**---------------------------------------------------------------------------- */
AT91F_TWI_EnableIt(AT91PS_TWI pTWI,unsigned int flag)1962 __inline void AT91F_TWI_EnableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
1963 unsigned int flag ) /* \arg IT to be enabled */
1964 {
1965 /** Write to the IER register */
1966 pTWI->TWI_IER = flag;
1967 }
1968
1969 /**---------------------------------------------------------------------------- */
1970 /** \fn AT91F_TWI_DisableIt */
1971 /** \brief Disable TWI IT */
1972 /**---------------------------------------------------------------------------- */
AT91F_TWI_DisableIt(AT91PS_TWI pTWI,unsigned int flag)1973 __inline void AT91F_TWI_DisableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */
1974 unsigned int flag ) /* \arg IT to be disabled */
1975 {
1976 /** Write to the IDR register */
1977 pTWI->TWI_IDR = flag;
1978 }
1979
1980 /**---------------------------------------------------------------------------- */
1981 /** \fn AT91F_TWI_Configure */
1982 /** \brief Configure TWI in master mode */
1983 /**---------------------------------------------------------------------------- */
AT91F_TWI_Configure(AT91PS_TWI pTWI)1984 __inline void AT91F_TWI_Configure( AT91PS_TWI pTWI ) /* \arg pointer to a TWI controller */
1985 {
1986 /** Disable interrupts */
1987 pTWI->TWI_IDR = ( unsigned int ) -1;
1988
1989 /** Reset peripheral */
1990 pTWI->TWI_CR = AT91C_TWI_SWRST;
1991
1992 /** Set Master mode */
1993 pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
1994 }
1995
1996 /**---------------------------------------------------------------------------- */
1997 /** \fn AT91F_TWI_GetInterruptMaskStatus */
1998 /** \brief Return TWI Interrupt Mask Status */
1999 /**---------------------------------------------------------------------------- */
AT91F_TWI_GetInterruptMaskStatus(AT91PS_TWI pTwi)2000 __inline unsigned int AT91F_TWI_GetInterruptMaskStatus( /* \return TWI Interrupt Mask Status */
2001 AT91PS_TWI pTwi ) /* \arg pointer to a TWI controller */
2002 {
2003 return pTwi->TWI_IMR;
2004 }
2005
2006 /**---------------------------------------------------------------------------- */
2007 /** \fn AT91F_TWI_IsInterruptMasked */
2008 /** \brief Test if TWI Interrupt is Masked */
2009 /**---------------------------------------------------------------------------- */
AT91F_TWI_IsInterruptMasked(AT91PS_TWI pTwi,unsigned int flag)2010 __inline int AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, /* \arg pointer to a TWI controller */
2011 unsigned int flag ) /* \arg flag to be tested */
2012 {
2013 return( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag );
2014 }
2015
2016 /* *****************************************************************************
2017 * SOFTWARE API FOR USART
2018 ***************************************************************************** */
2019 /**---------------------------------------------------------------------------- */
2020 /** \fn AT91F_US_Baudrate */
2021 /** \brief Calculate the baudrate */
2022 /** Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
2023 #define AT91C_US_ASYNC_MODE \
2024 ( AT91C_US_USMODE_NORMAL + \
2025 AT91C_US_NBSTOP_1_BIT + \
2026 AT91C_US_PAR_NONE + \
2027 AT91C_US_CHRL_8_BITS + \
2028 AT91C_US_CLKS_CLOCK )
2029
2030 /** Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
2031 #define AT91C_US_ASYNC_SCK_MODE \
2032 ( AT91C_US_USMODE_NORMAL + \
2033 AT91C_US_NBSTOP_1_BIT + \
2034 AT91C_US_PAR_NONE + \
2035 AT91C_US_CHRL_8_BITS + \
2036 AT91C_US_CLKS_EXT )
2037
2038 /** Standard Synchronous Mode : 8 bits , 1 stop , no parity */
2039 #define AT91C_US_SYNC_MODE \
2040 ( AT91C_US_SYNC + \
2041 AT91C_US_USMODE_NORMAL + \
2042 AT91C_US_NBSTOP_1_BIT + \
2043 AT91C_US_PAR_NONE + \
2044 AT91C_US_CHRL_8_BITS + \
2045 AT91C_US_CLKS_CLOCK )
2046
2047 /** SCK used Label */
2048 #define AT91C_US_SCK_USED ( AT91C_US_CKLO | AT91C_US_CLKS_EXT )
2049
2050 /** Standard ISO T=0 Mode : 8 bits , 1 stop , parity */
2051 #define AT91C_US_ISO_READER_MODE \
2052 ( AT91C_US_USMODE_ISO7816_0 + \
2053 AT91C_US_CLKS_CLOCK + \
2054 AT91C_US_NBSTOP_1_BIT + \
2055 AT91C_US_PAR_EVEN + \
2056 AT91C_US_CHRL_8_BITS + \
2057 AT91C_US_CKLO + \
2058 AT91C_US_OVER )
2059
2060 /** Standard IRDA mode */
2061 #define AT91C_US_ASYNC_IRDA_MODE \
2062 ( AT91C_US_USMODE_IRDA + \
2063 AT91C_US_NBSTOP_1_BIT + \
2064 AT91C_US_PAR_NONE + \
2065 AT91C_US_CHRL_8_BITS + \
2066 AT91C_US_CLKS_CLOCK )
2067
2068 /**---------------------------------------------------------------------------- */
2069 /** \fn AT91F_US_Baudrate */
2070 /** \brief Calculate baud_value according to the main clock and the baud rate */
2071 /**---------------------------------------------------------------------------- */
AT91F_US_Baudrate(const unsigned int main_clock,const unsigned int baud_rate)2072 __inline unsigned int AT91F_US_Baudrate( const unsigned int main_clock, /* \arg peripheral clock */
2073 const unsigned int baud_rate ) /* \arg UART baudrate */
2074 {
2075 unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) );
2076
2077 if( ( baud_value % 10 ) >= 5 )
2078 {
2079 baud_value = ( baud_value / 10 ) + 1;
2080 }
2081 else
2082 {
2083 baud_value /= 10;
2084 }
2085
2086 return baud_value;
2087 }
2088
2089 /**---------------------------------------------------------------------------- */
2090 /** \fn AT91F_US_SetBaudrate */
2091 /** \brief Set the baudrate according to the CPU clock */
2092 /**---------------------------------------------------------------------------- */
AT91F_US_SetBaudrate(AT91PS_USART pUSART,unsigned int mainClock,unsigned int speed)2093 __inline void AT91F_US_SetBaudrate( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
2094 unsigned int mainClock, /* \arg peripheral clock */
2095 unsigned int speed ) /* \arg UART baudrate */
2096 {
2097 /** Define the baud rate divisor register */
2098 pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed );
2099 }
2100
2101 /**---------------------------------------------------------------------------- */
2102 /** \fn AT91F_US_SetTimeguard */
2103 /** \brief Set USART timeguard */
2104 /**---------------------------------------------------------------------------- */
AT91F_US_SetTimeguard(AT91PS_USART pUSART,unsigned int timeguard)2105 __inline void AT91F_US_SetTimeguard( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
2106 unsigned int timeguard ) /* \arg timeguard value */
2107 {
2108 /** Write the Timeguard Register */
2109 pUSART->US_TTGR = timeguard;
2110 }
2111
2112 /**---------------------------------------------------------------------------- */
2113 /** \fn AT91F_US_EnableIt */
2114 /** \brief Enable USART IT */
2115 /**---------------------------------------------------------------------------- */
AT91F_US_EnableIt(AT91PS_USART pUSART,unsigned int flag)2116 __inline void AT91F_US_EnableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
2117 unsigned int flag ) /* \arg IT to be enabled */
2118 {
2119 /** Write to the IER register */
2120 pUSART->US_IER = flag;
2121 }
2122
2123 /**---------------------------------------------------------------------------- */
2124 /** \fn AT91F_US_DisableIt */
2125 /** \brief Disable USART IT */
2126 /**---------------------------------------------------------------------------- */
AT91F_US_DisableIt(AT91PS_USART pUSART,unsigned int flag)2127 __inline void AT91F_US_DisableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
2128 unsigned int flag ) /* \arg IT to be disabled */
2129 {
2130 /** Write to the IER register */
2131 pUSART->US_IDR = flag;
2132 }
2133
2134 /**---------------------------------------------------------------------------- */
2135 /** \fn AT91F_US_Configure */
2136 /** \brief Configure USART */
2137 /**---------------------------------------------------------------------------- */
AT91F_US_Configure(AT91PS_USART pUSART,unsigned int mainClock,unsigned int mode,unsigned int baudRate,unsigned int timeguard)2138 __inline void AT91F_US_Configure( AT91PS_USART pUSART, /* \arg pointer to a USART controller */
2139 unsigned int mainClock, /* \arg peripheral clock */
2140 unsigned int mode, /* \arg mode Register to be programmed */
2141 unsigned int baudRate, /* \arg baudrate to be programmed */
2142 unsigned int timeguard ) /* \arg timeguard to be programmed */
2143 {
2144 /** Disable interrupts */
2145 pUSART->US_IDR = ( unsigned int ) -1;
2146
2147 /** Reset receiver and transmitter */
2148 pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
2149
2150 /** Define the baud rate divisor register */
2151 AT91F_US_SetBaudrate( pUSART, mainClock, baudRate );
2152
2153 /** Write the Timeguard Register */
2154 AT91F_US_SetTimeguard( pUSART, timeguard );
2155
2156 /** Clear Transmit and Receive Counters */
2157 AT91F_PDC_Open( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
2158
2159 /** Define the USART mode */
2160 pUSART->US_MR = mode;
2161 }
2162
2163 /**---------------------------------------------------------------------------- */
2164 /** \fn AT91F_US_EnableRx */
2165 /** \brief Enable receiving characters */
2166 /**---------------------------------------------------------------------------- */
AT91F_US_EnableRx(AT91PS_USART pUSART)2167 __inline void AT91F_US_EnableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2168 {
2169 /** Enable receiver */
2170 pUSART->US_CR = AT91C_US_RXEN;
2171 }
2172
2173 /**---------------------------------------------------------------------------- */
2174 /** \fn AT91F_US_EnableTx */
2175 /** \brief Enable sending characters */
2176 /**---------------------------------------------------------------------------- */
AT91F_US_EnableTx(AT91PS_USART pUSART)2177 __inline void AT91F_US_EnableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2178 {
2179 /** Enable transmitter */
2180 pUSART->US_CR = AT91C_US_TXEN;
2181 }
2182
2183 /**---------------------------------------------------------------------------- */
2184 /** \fn AT91F_US_ResetRx */
2185 /** \brief Reset Receiver and re-enable it */
2186 /**---------------------------------------------------------------------------- */
AT91F_US_ResetRx(AT91PS_USART pUSART)2187 __inline void AT91F_US_ResetRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2188 {
2189 /** Reset receiver */
2190 pUSART->US_CR = AT91C_US_RSTRX;
2191 /** Re-Enable receiver */
2192 pUSART->US_CR = AT91C_US_RXEN;
2193 }
2194
2195 /**---------------------------------------------------------------------------- */
2196 /** \fn AT91F_US_ResetTx */
2197 /** \brief Reset Transmitter and re-enable it */
2198 /**---------------------------------------------------------------------------- */
AT91F_US_ResetTx(AT91PS_USART pUSART)2199 __inline void AT91F_US_ResetTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2200 {
2201 /** Reset transmitter */
2202 pUSART->US_CR = AT91C_US_RSTTX;
2203 /** Enable transmitter */
2204 pUSART->US_CR = AT91C_US_TXEN;
2205 }
2206
2207 /**---------------------------------------------------------------------------- */
2208 /** \fn AT91F_US_DisableRx */
2209 /** \brief Disable Receiver */
2210 /**---------------------------------------------------------------------------- */
AT91F_US_DisableRx(AT91PS_USART pUSART)2211 __inline void AT91F_US_DisableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2212 {
2213 /** Disable receiver */
2214 pUSART->US_CR = AT91C_US_RXDIS;
2215 }
2216
2217 /**---------------------------------------------------------------------------- */
2218 /** \fn AT91F_US_DisableTx */
2219 /** \brief Disable Transmitter */
2220 /**---------------------------------------------------------------------------- */
AT91F_US_DisableTx(AT91PS_USART pUSART)2221 __inline void AT91F_US_DisableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2222 {
2223 /** Disable transmitter */
2224 pUSART->US_CR = AT91C_US_TXDIS;
2225 }
2226
2227 /**---------------------------------------------------------------------------- */
2228 /** \fn AT91F_US_Close */
2229 /** \brief Close USART: disable IT disable receiver and transmitter, close PDC */
2230 /**---------------------------------------------------------------------------- */
AT91F_US_Close(AT91PS_USART pUSART)2231 __inline void AT91F_US_Close( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2232 {
2233 /** Reset the baud rate divisor register */
2234 pUSART->US_BRGR = 0;
2235
2236 /** Reset the USART mode */
2237 pUSART->US_MR = 0;
2238
2239 /** Reset the Timeguard Register */
2240 pUSART->US_TTGR = 0;
2241
2242 /** Disable all interrupts */
2243 pUSART->US_IDR = 0xFFFFFFFF;
2244
2245 /** Abort the Peripheral Data Transfers */
2246 AT91F_PDC_Close( ( AT91PS_PDC ) &( pUSART->US_RPR ) );
2247
2248 /** Disable receiver and transmitter and stop any activity immediately */
2249 pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX;
2250 }
2251
2252 /**---------------------------------------------------------------------------- */
2253 /** \fn AT91F_US_TxReady */
2254 /** \brief Return 1 if a character can be written in US_THR */
2255 /**---------------------------------------------------------------------------- */
AT91F_US_TxReady(AT91PS_USART pUSART)2256 __inline unsigned int AT91F_US_TxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2257 {
2258 return( pUSART->US_CSR & AT91C_US_TXRDY );
2259 }
2260
2261 /**---------------------------------------------------------------------------- */
2262 /** \fn AT91F_US_RxReady */
2263 /** \brief Return 1 if a character can be read in US_RHR */
2264 /**---------------------------------------------------------------------------- */
AT91F_US_RxReady(AT91PS_USART pUSART)2265 __inline unsigned int AT91F_US_RxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2266 {
2267 return( pUSART->US_CSR & AT91C_US_RXRDY );
2268 }
2269
2270 /**---------------------------------------------------------------------------- */
2271 /** \fn AT91F_US_Error */
2272 /** \brief Return the error flag */
2273 /**---------------------------------------------------------------------------- */
AT91F_US_Error(AT91PS_USART pUSART)2274 __inline unsigned int AT91F_US_Error( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */
2275 {
2276 return( pUSART->US_CSR &
2277 ( AT91C_US_OVRE | /* Overrun error */
2278 AT91C_US_FRAME | /* Framing error */
2279 AT91C_US_PARE ) ); /* Parity error */
2280 }
2281
2282 /**---------------------------------------------------------------------------- */
2283 /** \fn AT91F_US_PutChar */
2284 /** \brief Send a character,does not check if ready to send */
2285 /**---------------------------------------------------------------------------- */
AT91F_US_PutChar(AT91PS_USART pUSART,int character)2286 __inline void AT91F_US_PutChar( AT91PS_USART pUSART,
2287 int character )
2288 {
2289 pUSART->US_THR = ( character & 0x1FF );
2290 }
2291
2292 /**---------------------------------------------------------------------------- */
2293 /** \fn AT91F_US_GetChar */
2294 /** \brief Receive a character,does not check if a character is available */
2295 /**---------------------------------------------------------------------------- */
AT91F_US_GetChar(const AT91PS_USART pUSART)2296 __inline int AT91F_US_GetChar( const AT91PS_USART pUSART )
2297 {
2298 return( ( pUSART->US_RHR ) & 0x1FF );
2299 }
2300
2301 /**---------------------------------------------------------------------------- */
2302 /** \fn AT91F_US_SendFrame */
2303 /** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
2304 /**---------------------------------------------------------------------------- */
AT91F_US_SendFrame(AT91PS_USART pUSART,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)2305 __inline unsigned int AT91F_US_SendFrame( AT91PS_USART pUSART,
2306 char * pBuffer,
2307 unsigned int szBuffer,
2308 char * pNextBuffer,
2309 unsigned int szNextBuffer )
2310 {
2311 return AT91F_PDC_SendFrame(
2312 ( AT91PS_PDC ) &( pUSART->US_RPR ),
2313 pBuffer,
2314 szBuffer,
2315 pNextBuffer,
2316 szNextBuffer );
2317 }
2318
2319 /**---------------------------------------------------------------------------- */
2320 /** \fn AT91F_US_ReceiveFrame */
2321 /** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */
2322 /**---------------------------------------------------------------------------- */
AT91F_US_ReceiveFrame(AT91PS_USART pUSART,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)2323 __inline unsigned int AT91F_US_ReceiveFrame( AT91PS_USART pUSART,
2324 char * pBuffer,
2325 unsigned int szBuffer,
2326 char * pNextBuffer,
2327 unsigned int szNextBuffer )
2328 {
2329 return AT91F_PDC_ReceiveFrame(
2330 ( AT91PS_PDC ) &( pUSART->US_RPR ),
2331 pBuffer,
2332 szBuffer,
2333 pNextBuffer,
2334 szNextBuffer );
2335 }
2336
2337 /**---------------------------------------------------------------------------- */
2338 /** \fn AT91F_US_SetIrdaFilter */
2339 /** \brief Set the value of IrDa filter register */
2340 /**---------------------------------------------------------------------------- */
AT91F_US_SetIrdaFilter(AT91PS_USART pUSART,unsigned char value)2341 __inline void AT91F_US_SetIrdaFilter( AT91PS_USART pUSART,
2342 unsigned char value )
2343 {
2344 pUSART->US_IF = value;
2345 }
2346
2347 /* *****************************************************************************
2348 * SOFTWARE API FOR UDP
2349 ***************************************************************************** */
2350 /**---------------------------------------------------------------------------- */
2351 /** \fn AT91F_UDP_EnableIt */
2352 /** \brief Enable UDP IT */
2353 /**---------------------------------------------------------------------------- */
AT91F_UDP_EnableIt(AT91PS_UDP pUDP,unsigned int flag)2354 __inline void AT91F_UDP_EnableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2355 unsigned int flag ) /* \arg IT to be enabled */
2356 {
2357 /** Write to the IER register */
2358 pUDP->UDP_IER = flag;
2359 }
2360
2361 /**---------------------------------------------------------------------------- */
2362 /** \fn AT91F_UDP_DisableIt */
2363 /** \brief Disable UDP IT */
2364 /**---------------------------------------------------------------------------- */
AT91F_UDP_DisableIt(AT91PS_UDP pUDP,unsigned int flag)2365 __inline void AT91F_UDP_DisableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2366 unsigned int flag ) /* \arg IT to be disabled */
2367 {
2368 /** Write to the IDR register */
2369 pUDP->UDP_IDR = flag;
2370 }
2371
2372 /**---------------------------------------------------------------------------- */
2373 /** \fn AT91F_UDP_SetAddress */
2374 /** \brief Set UDP functional address */
2375 /**---------------------------------------------------------------------------- */
AT91F_UDP_SetAddress(AT91PS_UDP pUDP,unsigned char address)2376 __inline void AT91F_UDP_SetAddress( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2377 unsigned char address ) /* \arg new UDP address */
2378 {
2379 pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address );
2380 }
2381
2382 /**---------------------------------------------------------------------------- */
2383 /** \fn AT91F_UDP_EnableEp */
2384 /** \brief Enable Endpoint */
2385 /**---------------------------------------------------------------------------- */
AT91F_UDP_EnableEp(AT91PS_UDP pUDP,unsigned int flag)2386 __inline void AT91F_UDP_EnableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2387 unsigned int flag ) /* \arg endpoints to be enabled */
2388 {
2389 pUDP->UDP_GLBSTATE |= flag;
2390 }
2391
2392 /**---------------------------------------------------------------------------- */
2393 /** \fn AT91F_UDP_DisableEp */
2394 /** \brief Enable Endpoint */
2395 /**---------------------------------------------------------------------------- */
AT91F_UDP_DisableEp(AT91PS_UDP pUDP,unsigned int flag)2396 __inline void AT91F_UDP_DisableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2397 unsigned int flag ) /* \arg endpoints to be enabled */
2398 {
2399 pUDP->UDP_GLBSTATE &= ~( flag );
2400 }
2401
2402 /**---------------------------------------------------------------------------- */
2403 /** \fn AT91F_UDP_SetState */
2404 /** \brief Set UDP Device state */
2405 /**---------------------------------------------------------------------------- */
AT91F_UDP_SetState(AT91PS_UDP pUDP,unsigned int flag)2406 __inline void AT91F_UDP_SetState( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2407 unsigned int flag ) /* \arg new UDP address */
2408 {
2409 pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG );
2410 pUDP->UDP_GLBSTATE |= flag;
2411 }
2412
2413 /**---------------------------------------------------------------------------- */
2414 /** \fn AT91F_UDP_GetState */
2415 /** \brief return UDP Device state */
2416 /**---------------------------------------------------------------------------- */
AT91F_UDP_GetState(AT91PS_UDP pUDP)2417 __inline unsigned int AT91F_UDP_GetState( /* \return the UDP device state */
2418 AT91PS_UDP pUDP ) /* \arg pointer to a UDP controller */
2419 {
2420 return( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) );
2421 }
2422
2423 /**---------------------------------------------------------------------------- */
2424 /** \fn AT91F_UDP_ResetEp */
2425 /** \brief Reset UDP endpoint */
2426 /**---------------------------------------------------------------------------- */
AT91F_UDP_ResetEp(AT91PS_UDP pUDP,unsigned int flag)2427 __inline void AT91F_UDP_ResetEp( /* \return the UDP device state */
2428 AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2429 unsigned int flag ) /* \arg Endpoints to be reset */
2430 {
2431 pUDP->UDP_RSTEP = flag;
2432 }
2433
2434 /**---------------------------------------------------------------------------- */
2435 /** \fn AT91F_UDP_EpStall */
2436 /** \brief Endpoint will STALL requests */
2437 /**---------------------------------------------------------------------------- */
AT91F_UDP_EpStall(AT91PS_UDP pUDP,unsigned char endpoint)2438 __inline void AT91F_UDP_EpStall( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2439 unsigned char endpoint ) /* \arg endpoint number */
2440 {
2441 pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_FORCESTALL;
2442 }
2443
2444 /**---------------------------------------------------------------------------- */
2445 /** \fn AT91F_UDP_EpWrite */
2446 /** \brief Write value in the DPR */
2447 /**---------------------------------------------------------------------------- */
AT91F_UDP_EpWrite(AT91PS_UDP pUDP,unsigned char endpoint,unsigned char value)2448 __inline void AT91F_UDP_EpWrite( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2449 unsigned char endpoint, /* \arg endpoint number */
2450 unsigned char value ) /* \arg value to be written in the DPR */
2451 {
2452 pUDP->UDP_FDR[ endpoint ] = value;
2453 }
2454
2455 /**---------------------------------------------------------------------------- */
2456 /** \fn AT91F_UDP_EpRead */
2457 /** \brief Return value from the DPR */
2458 /**---------------------------------------------------------------------------- */
AT91F_UDP_EpRead(AT91PS_UDP pUDP,unsigned char endpoint)2459 __inline unsigned int AT91F_UDP_EpRead( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2460 unsigned char endpoint ) /* \arg endpoint number */
2461 {
2462 return pUDP->UDP_FDR[ endpoint ];
2463 }
2464
2465 /**---------------------------------------------------------------------------- */
2466 /** \fn AT91F_UDP_EpEndOfWr */
2467 /** \brief Notify the UDP that values in DPR are ready to be sent */
2468 /**---------------------------------------------------------------------------- */
AT91F_UDP_EpEndOfWr(AT91PS_UDP pUDP,unsigned char endpoint)2469 __inline void AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2470 unsigned char endpoint ) /* \arg endpoint number */
2471 {
2472 pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_TXPKTRDY;
2473 }
2474
2475 /**---------------------------------------------------------------------------- */
2476 /** \fn AT91F_UDP_EpClear */
2477 /** \brief Clear flag in the endpoint CSR register */
2478 /**---------------------------------------------------------------------------- */
AT91F_UDP_EpClear(AT91PS_UDP pUDP,unsigned char endpoint,unsigned int flag)2479 __inline void AT91F_UDP_EpClear( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2480 unsigned char endpoint, /* \arg endpoint number */
2481 unsigned int flag ) /* \arg flag to be cleared */
2482 {
2483 pUDP->UDP_CSR[ endpoint ] &= ~( flag );
2484 }
2485
2486 /**---------------------------------------------------------------------------- */
2487 /** \fn AT91F_UDP_EpSet */
2488 /** \brief Set flag in the endpoint CSR register */
2489 /**---------------------------------------------------------------------------- */
AT91F_UDP_EpSet(AT91PS_UDP pUDP,unsigned char endpoint,unsigned int flag)2490 __inline void AT91F_UDP_EpSet( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2491 unsigned char endpoint, /* \arg endpoint number */
2492 unsigned int flag ) /* \arg flag to be cleared */
2493 {
2494 pUDP->UDP_CSR[ endpoint ] |= flag;
2495 }
2496
2497 /**---------------------------------------------------------------------------- */
2498 /** \fn AT91F_UDP_EpStatus */
2499 /** \brief Return the endpoint CSR register */
2500 /**---------------------------------------------------------------------------- */
AT91F_UDP_EpStatus(AT91PS_UDP pUDP,unsigned char endpoint)2501 __inline unsigned int AT91F_UDP_EpStatus( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */
2502 unsigned char endpoint ) /* \arg endpoint number */
2503 {
2504 return pUDP->UDP_CSR[ endpoint ];
2505 }
2506
2507 /**---------------------------------------------------------------------------- */
2508 /** \fn AT91F_UDP_GetInterruptMaskStatus */
2509 /** \brief Return UDP Interrupt Mask Status */
2510 /**---------------------------------------------------------------------------- */
AT91F_UDP_GetInterruptMaskStatus(AT91PS_UDP pUdp)2511 __inline unsigned int AT91F_UDP_GetInterruptMaskStatus( /* \return UDP Interrupt Mask Status */
2512 AT91PS_UDP pUdp ) /* \arg pointer to a UDP controller */
2513 {
2514 return pUdp->UDP_IMR;
2515 }
2516
2517 /**---------------------------------------------------------------------------- */
2518 /** \fn AT91F_UDP_IsInterruptMasked */
2519 /** \brief Test if UDP Interrupt is Masked */
2520 /**---------------------------------------------------------------------------- */
AT91F_UDP_IsInterruptMasked(AT91PS_UDP pUdp,unsigned int flag)2521 __inline int AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, /* \arg pointer to a UDP controller */
2522 unsigned int flag ) /* \arg flag to be tested */
2523 {
2524 return( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag );
2525 }
2526
2527 /* *****************************************************************************
2528 * SOFTWARE API FOR AIC
2529 ***************************************************************************** */
2530 #define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */
2531
2532 /**---------------------------------------------------------------------------- */
2533 /** \fn AT91F_AIC_ConfigureIt */
2534 /** \brief Interrupt Handler Initialization */
2535 /**---------------------------------------------------------------------------- */
AT91F_AIC_ConfigureIt(AT91PS_AIC pAic,unsigned int irq_id,unsigned int priority,unsigned int src_type,void (* newHandler)(void))2536 __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
2537 unsigned int irq_id, /* \arg interrupt number to initialize */
2538 unsigned int priority, /* \arg priority to give to the interrupt */
2539 unsigned int src_type, /* \arg activation and sense of activation */
2540 void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */
2541 {
2542 unsigned int oldHandler;
2543 unsigned int mask;
2544
2545 oldHandler = pAic->AIC_SVR[ irq_id ];
2546
2547 mask = 0x1 << irq_id;
2548 /** Disable the interrupt on the interrupt controller */
2549 pAic->AIC_IDCR = mask;
2550 /** Save the interrupt handler routine pointer and the interrupt priority */
2551 pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler;
2552 /** Store the Source Mode Register */
2553 pAic->AIC_SMR[ irq_id ] = src_type | priority;
2554 /** Clear the interrupt on the interrupt controller */
2555 pAic->AIC_ICCR = mask;
2556
2557 return oldHandler;
2558 }
2559
2560 /**---------------------------------------------------------------------------- */
2561 /** \fn AT91F_AIC_EnableIt */
2562 /** \brief Enable corresponding IT number */
2563 /**---------------------------------------------------------------------------- */
AT91F_AIC_EnableIt(AT91PS_AIC pAic,unsigned int irq_id)2564 __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
2565 unsigned int irq_id ) /* \arg interrupt number to initialize */
2566 {
2567 /** Enable the interrupt on the interrupt controller */
2568 pAic->AIC_IECR = 0x1 << irq_id;
2569 }
2570
2571 /**---------------------------------------------------------------------------- */
2572 /** \fn AT91F_AIC_DisableIt */
2573 /** \brief Disable corresponding IT number */
2574 /**---------------------------------------------------------------------------- */
AT91F_AIC_DisableIt(AT91PS_AIC pAic,unsigned int irq_id)2575 __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
2576 unsigned int irq_id ) /* \arg interrupt number to initialize */
2577 {
2578 unsigned int mask = 0x1 << irq_id;
2579
2580 /** Disable the interrupt on the interrupt controller */
2581 pAic->AIC_IDCR = mask;
2582 /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
2583 pAic->AIC_ICCR = mask;
2584 }
2585
2586 /**---------------------------------------------------------------------------- */
2587 /** \fn AT91F_AIC_ClearIt */
2588 /** \brief Clear corresponding IT number */
2589 /**---------------------------------------------------------------------------- */
AT91F_AIC_ClearIt(AT91PS_AIC pAic,unsigned int irq_id)2590 __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
2591 unsigned int irq_id ) /* \arg interrupt number to initialize */
2592 {
2593 /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */
2594 pAic->AIC_ICCR = ( 0x1 << irq_id );
2595 }
2596
2597 /**---------------------------------------------------------------------------- */
2598 /** \fn AT91F_AIC_AcknowledgeIt */
2599 /** \brief Acknowledge corresponding IT number */
2600 /**---------------------------------------------------------------------------- */
AT91F_AIC_AcknowledgeIt(AT91PS_AIC pAic)2601 __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */
2602 {
2603 pAic->AIC_EOICR = pAic->AIC_EOICR;
2604 }
2605
2606 /**---------------------------------------------------------------------------- */
2607 /** \fn AT91F_AIC_SetExceptionVector */
2608 /** \brief Configure vector handler */
2609 /**---------------------------------------------------------------------------- */
AT91F_AIC_SetExceptionVector(unsigned int * pVector,void (* Handler)())2610 __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */
2611 void ( * Handler )() ) /* \arg Interrupt Handler */
2612 {
2613 unsigned int oldVector = *pVector;
2614
2615 if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE )
2616 {
2617 *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE;
2618 }
2619 else
2620 {
2621 *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000;
2622 }
2623
2624 return oldVector;
2625 }
2626
2627 /**---------------------------------------------------------------------------- */
2628 /** \fn AT91F_AIC_Trig */
2629 /** \brief Trig an IT */
2630 /**---------------------------------------------------------------------------- */
AT91F_AIC_Trig(AT91PS_AIC pAic,unsigned int irq_id)2631 __inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
2632 unsigned int irq_id ) /* \arg interrupt number */
2633 {
2634 pAic->AIC_ISCR = ( 0x1 << irq_id );
2635 }
2636
2637 /**---------------------------------------------------------------------------- */
2638 /** \fn AT91F_AIC_IsActive */
2639 /** \brief Test if an IT is active */
2640 /**---------------------------------------------------------------------------- */
AT91F_AIC_IsActive(AT91PS_AIC pAic,unsigned int irq_id)2641 __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
2642 unsigned int irq_id ) /* \arg Interrupt Number */
2643 {
2644 return( pAic->AIC_ISR & ( 0x1 << irq_id ) );
2645 }
2646
2647 /**---------------------------------------------------------------------------- */
2648 /** \fn AT91F_AIC_IsPending */
2649 /** \brief Test if an IT is pending */
2650 /**---------------------------------------------------------------------------- */
AT91F_AIC_IsPending(AT91PS_AIC pAic,unsigned int irq_id)2651 __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
2652 unsigned int irq_id ) /* \arg Interrupt Number */
2653 {
2654 return( pAic->AIC_IPR & ( 0x1 << irq_id ) );
2655 }
2656
2657 /**---------------------------------------------------------------------------- */
2658 /** \fn AT91F_AIC_Open */
2659 /** \brief Set exception vectors and AIC registers to default values */
2660 /**---------------------------------------------------------------------------- */
AT91F_AIC_Open(AT91PS_AIC pAic,void (* IrqHandler)(),void (* FiqHandler)(),void (* DefaultHandler)(),void (* SpuriousHandler)(),unsigned int protectMode)2661 __inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */
2662 void ( * IrqHandler )(), /* \arg Default IRQ vector exception */
2663 void ( * FiqHandler )(), /* \arg Default FIQ vector exception */
2664 void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */
2665 void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */
2666 unsigned int protectMode ) /* \arg Debug Control Register */
2667 {
2668 int i;
2669
2670 /* Disable all interrupts and set IVR to the default handler */
2671 for( i = 0; i < 32; ++i )
2672 {
2673 AT91F_AIC_DisableIt( pAic, i );
2674 AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler );
2675 }
2676
2677 /* Set the IRQ exception vector */
2678 AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler );
2679 /* Set the Fast Interrupt exception vector */
2680 AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler );
2681
2682 pAic->AIC_SPU = ( unsigned int ) SpuriousHandler;
2683 pAic->AIC_DCR = protectMode;
2684 }
2685 /**---------------------------------------------------------------------------- */
2686 /** \fn AT91F_MC_CfgPMC */
2687 /** \brief Enable Peripheral clock in PMC for MC */
2688 /**---------------------------------------------------------------------------- */
AT91F_MC_CfgPMC(void)2689 __inline void AT91F_MC_CfgPMC( void )
2690 {
2691 AT91F_PMC_EnablePeriphClock(
2692 AT91C_BASE_PMC, /* PIO controller base address */
2693 ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
2694 }
2695
2696 /**---------------------------------------------------------------------------- */
2697 /** \fn AT91F_DBGU_CfgPMC */
2698 /** \brief Enable Peripheral clock in PMC for DBGU */
2699 /**---------------------------------------------------------------------------- */
AT91F_DBGU_CfgPMC(void)2700 __inline void AT91F_DBGU_CfgPMC( void )
2701 {
2702 AT91F_PMC_EnablePeriphClock(
2703 AT91C_BASE_PMC, /* PIO controller base address */
2704 ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
2705 }
2706
2707 /**---------------------------------------------------------------------------- */
2708 /** \fn AT91F_DBGU_CfgPIO */
2709 /** \brief Configure PIO controllers to drive DBGU signals */
2710 /**---------------------------------------------------------------------------- */
AT91F_DBGU_CfgPIO(void)2711 __inline void AT91F_DBGU_CfgPIO( void )
2712 {
2713 /* Configure PIO controllers to periph mode */
2714 AT91F_PIO_CfgPeriph(
2715 AT91C_BASE_PIOA, /* PIO controller base address */
2716 ( ( unsigned int ) AT91C_PA10_DTXD ) |
2717 ( ( unsigned int ) AT91C_PA9_DRXD ), /* Peripheral A */
2718 0 ); /* Peripheral B */
2719 }
2720
2721 /**---------------------------------------------------------------------------- */
2722 /** \fn AT91F_PWMC_CH3_CfgPIO */
2723 /** \brief Configure PIO controllers to drive PWMC_CH3 signals */
2724 /**---------------------------------------------------------------------------- */
AT91F_PWMC_CH3_CfgPIO(void)2725 __inline void AT91F_PWMC_CH3_CfgPIO( void )
2726 {
2727 /* Configure PIO controllers to periph mode */
2728 AT91F_PIO_CfgPeriph(
2729 AT91C_BASE_PIOA, /* PIO controller base address */
2730 0, /* Peripheral A */
2731 ( ( unsigned int ) AT91C_PA14_PWM3 ) |
2732 ( ( unsigned int ) AT91C_PA7_PWM3 ) ); /* Peripheral B */
2733 }
2734
2735 /**---------------------------------------------------------------------------- */
2736 /** \fn AT91F_PWMC_CH2_CfgPIO */
2737 /** \brief Configure PIO controllers to drive PWMC_CH2 signals */
2738 /**---------------------------------------------------------------------------- */
AT91F_PWMC_CH2_CfgPIO(void)2739 __inline void AT91F_PWMC_CH2_CfgPIO( void )
2740 {
2741 /* Configure PIO controllers to periph mode */
2742 AT91F_PIO_CfgPeriph(
2743 AT91C_BASE_PIOA, /* PIO controller base address */
2744 ( ( unsigned int ) AT91C_PA2_PWM2 ), /* Peripheral A */
2745 ( ( unsigned int ) AT91C_PA25_PWM2 ) |
2746 ( ( unsigned int ) AT91C_PA13_PWM2 ) ); /* Peripheral B */
2747 }
2748
2749 /**---------------------------------------------------------------------------- */
2750 /** \fn AT91F_PWMC_CH1_CfgPIO */
2751 /** \brief Configure PIO controllers to drive PWMC_CH1 signals */
2752 /**---------------------------------------------------------------------------- */
AT91F_PWMC_CH1_CfgPIO(void)2753 __inline void AT91F_PWMC_CH1_CfgPIO( void )
2754 {
2755 /* Configure PIO controllers to periph mode */
2756 AT91F_PIO_CfgPeriph(
2757 AT91C_BASE_PIOA, /* PIO controller base address */
2758 ( ( unsigned int ) AT91C_PA1_PWM1 ), /* Peripheral A */
2759 ( ( unsigned int ) AT91C_PA24_PWM1 ) |
2760 ( ( unsigned int ) AT91C_PA12_PWM1 ) ); /* Peripheral B */
2761 }
2762
2763 /**---------------------------------------------------------------------------- */
2764 /** \fn AT91F_PWMC_CH0_CfgPIO */
2765 /** \brief Configure PIO controllers to drive PWMC_CH0 signals */
2766 /**---------------------------------------------------------------------------- */
AT91F_PWMC_CH0_CfgPIO(void)2767 __inline void AT91F_PWMC_CH0_CfgPIO( void )
2768 {
2769 /* Configure PIO controllers to periph mode */
2770 AT91F_PIO_CfgPeriph(
2771 AT91C_BASE_PIOA, /* PIO controller base address */
2772 ( ( unsigned int ) AT91C_PA0_PWM0 ), /* Peripheral A */
2773 ( ( unsigned int ) AT91C_PA23_PWM0 ) |
2774 ( ( unsigned int ) AT91C_PA11_PWM0 ) ); /* Peripheral B */
2775 }
2776
2777 /**---------------------------------------------------------------------------- */
2778 /** \fn AT91F_SSC_CfgPMC */
2779 /** \brief Enable Peripheral clock in PMC for SSC */
2780 /**---------------------------------------------------------------------------- */
AT91F_SSC_CfgPMC(void)2781 __inline void AT91F_SSC_CfgPMC( void )
2782 {
2783 AT91F_PMC_EnablePeriphClock(
2784 AT91C_BASE_PMC, /* PIO controller base address */
2785 ( ( unsigned int ) 1 << AT91C_ID_SSC ) );
2786 }
2787
2788 /**---------------------------------------------------------------------------- */
2789 /** \fn AT91F_SSC_CfgPIO */
2790 /** \brief Configure PIO controllers to drive SSC signals */
2791 /**---------------------------------------------------------------------------- */
AT91F_SSC_CfgPIO(void)2792 __inline void AT91F_SSC_CfgPIO( void )
2793 {
2794 /* Configure PIO controllers to periph mode */
2795 AT91F_PIO_CfgPeriph(
2796 AT91C_BASE_PIOA, /* PIO controller base address */
2797 ( ( unsigned int ) AT91C_PA17_TD ) |
2798 ( ( unsigned int ) AT91C_PA15_TF ) |
2799 ( ( unsigned int ) AT91C_PA19_RK ) |
2800 ( ( unsigned int ) AT91C_PA18_RD ) |
2801 ( ( unsigned int ) AT91C_PA20_RF ) |
2802 ( ( unsigned int ) AT91C_PA16_TK ), /* Peripheral A */
2803 0 ); /* Peripheral B */
2804 }
2805
2806 /**---------------------------------------------------------------------------- */
2807 /** \fn AT91F_SPI_CfgPMC */
2808 /** \brief Enable Peripheral clock in PMC for SPI */
2809 /**---------------------------------------------------------------------------- */
AT91F_SPI_CfgPMC(void)2810 __inline void AT91F_SPI_CfgPMC( void )
2811 {
2812 AT91F_PMC_EnablePeriphClock(
2813 AT91C_BASE_PMC, /* PIO controller base address */
2814 ( ( unsigned int ) 1 << AT91C_ID_SPI ) );
2815 }
2816
2817 /**---------------------------------------------------------------------------- */
2818 /** \fn AT91F_SPI_CfgPIO */
2819 /** \brief Configure PIO controllers to drive SPI signals */
2820 /**---------------------------------------------------------------------------- */
AT91F_SPI_CfgPIO(void)2821 __inline void AT91F_SPI_CfgPIO( void )
2822 {
2823 /* Configure PIO controllers to periph mode */
2824 AT91F_PIO_CfgPeriph(
2825 AT91C_BASE_PIOA, /* PIO controller base address */
2826 ( ( unsigned int ) AT91C_PA11_NPCS0 ) |
2827 ( ( unsigned int ) AT91C_PA13_MOSI ) |
2828 ( ( unsigned int ) AT91C_PA31_NPCS1 ) |
2829 ( ( unsigned int ) AT91C_PA12_MISO ) |
2830 ( ( unsigned int ) AT91C_PA14_SPCK ), /* Peripheral A */
2831 ( ( unsigned int ) AT91C_PA9_NPCS1 ) |
2832 ( ( unsigned int ) AT91C_PA30_NPCS2 ) |
2833 ( ( unsigned int ) AT91C_PA10_NPCS2 ) |
2834 ( ( unsigned int ) AT91C_PA22_NPCS3 ) |
2835 ( ( unsigned int ) AT91C_PA3_NPCS3 ) |
2836 ( ( unsigned int ) AT91C_PA5_NPCS3 ) ); /* Peripheral B */
2837 }
2838
2839 /**---------------------------------------------------------------------------- */
2840 /** \fn AT91F_PWMC_CfgPMC */
2841 /** \brief Enable Peripheral clock in PMC for PWMC */
2842 /**---------------------------------------------------------------------------- */
AT91F_PWMC_CfgPMC(void)2843 __inline void AT91F_PWMC_CfgPMC( void )
2844 {
2845 AT91F_PMC_EnablePeriphClock(
2846 AT91C_BASE_PMC, /* PIO controller base address */
2847 ( ( unsigned int ) 1 << AT91C_ID_PWMC ) );
2848 }
2849
2850 /**---------------------------------------------------------------------------- */
2851 /** \fn AT91F_TC2_CfgPMC */
2852 /** \brief Enable Peripheral clock in PMC for TC2 */
2853 /**---------------------------------------------------------------------------- */
AT91F_TC2_CfgPMC(void)2854 __inline void AT91F_TC2_CfgPMC( void )
2855 {
2856 AT91F_PMC_EnablePeriphClock(
2857 AT91C_BASE_PMC, /* PIO controller base address */
2858 ( ( unsigned int ) 1 << AT91C_ID_TC2 ) );
2859 }
2860
2861 /**---------------------------------------------------------------------------- */
2862 /** \fn AT91F_TC2_CfgPIO */
2863 /** \brief Configure PIO controllers to drive TC2 signals */
2864 /**---------------------------------------------------------------------------- */
AT91F_TC2_CfgPIO(void)2865 __inline void AT91F_TC2_CfgPIO( void )
2866 {
2867 /* Configure PIO controllers to periph mode */
2868 AT91F_PIO_CfgPeriph(
2869 AT91C_BASE_PIOA, /* PIO controller base address */
2870 0, /* Peripheral A */
2871 ( ( unsigned int ) AT91C_PA26_TIOA2 ) |
2872 ( ( unsigned int ) AT91C_PA27_TIOB2 ) |
2873 ( ( unsigned int ) AT91C_PA29_TCLK2 ) ); /* Peripheral B */
2874 }
2875
2876 /**---------------------------------------------------------------------------- */
2877 /** \fn AT91F_TC1_CfgPMC */
2878 /** \brief Enable Peripheral clock in PMC for TC1 */
2879 /**---------------------------------------------------------------------------- */
AT91F_TC1_CfgPMC(void)2880 __inline void AT91F_TC1_CfgPMC( void )
2881 {
2882 AT91F_PMC_EnablePeriphClock(
2883 AT91C_BASE_PMC, /* PIO controller base address */
2884 ( ( unsigned int ) 1 << AT91C_ID_TC1 ) );
2885 }
2886
2887 /**---------------------------------------------------------------------------- */
2888 /** \fn AT91F_TC1_CfgPIO */
2889 /** \brief Configure PIO controllers to drive TC1 signals */
2890 /**---------------------------------------------------------------------------- */
AT91F_TC1_CfgPIO(void)2891 __inline void AT91F_TC1_CfgPIO( void )
2892 {
2893 /* Configure PIO controllers to periph mode */
2894 AT91F_PIO_CfgPeriph(
2895 AT91C_BASE_PIOA, /* PIO controller base address */
2896 0, /* Peripheral A */
2897 ( ( unsigned int ) AT91C_PA15_TIOA1 ) |
2898 ( ( unsigned int ) AT91C_PA16_TIOB1 ) |
2899 ( ( unsigned int ) AT91C_PA28_TCLK1 ) ); /* Peripheral B */
2900 }
2901
2902 /**---------------------------------------------------------------------------- */
2903 /** \fn AT91F_TC0_CfgPMC */
2904 /** \brief Enable Peripheral clock in PMC for TC0 */
2905 /**---------------------------------------------------------------------------- */
AT91F_TC0_CfgPMC(void)2906 __inline void AT91F_TC0_CfgPMC( void )
2907 {
2908 AT91F_PMC_EnablePeriphClock(
2909 AT91C_BASE_PMC, /* PIO controller base address */
2910 ( ( unsigned int ) 1 << AT91C_ID_TC0 ) );
2911 }
2912
2913 /**---------------------------------------------------------------------------- */
2914 /** \fn AT91F_TC0_CfgPIO */
2915 /** \brief Configure PIO controllers to drive TC0 signals */
2916 /**---------------------------------------------------------------------------- */
AT91F_TC0_CfgPIO(void)2917 __inline void AT91F_TC0_CfgPIO( void )
2918 {
2919 /* Configure PIO controllers to periph mode */
2920 AT91F_PIO_CfgPeriph(
2921 AT91C_BASE_PIOA, /* PIO controller base address */
2922 0, /* Peripheral A */
2923 ( ( unsigned int ) AT91C_PA0_TIOA0 ) |
2924 ( ( unsigned int ) AT91C_PA1_TIOB0 ) |
2925 ( ( unsigned int ) AT91C_PA4_TCLK0 ) ); /* Peripheral B */
2926 }
2927
2928 /**---------------------------------------------------------------------------- */
2929 /** \fn AT91F_PMC_CfgPMC */
2930 /** \brief Enable Peripheral clock in PMC for PMC */
2931 /**---------------------------------------------------------------------------- */
AT91F_PMC_CfgPMC(void)2932 __inline void AT91F_PMC_CfgPMC( void )
2933 {
2934 AT91F_PMC_EnablePeriphClock(
2935 AT91C_BASE_PMC, /* PIO controller base address */
2936 ( ( unsigned int ) 1 << AT91C_ID_SYS ) );
2937 }
2938
2939 /**---------------------------------------------------------------------------- */
2940 /** \fn AT91F_PMC_CfgPIO */
2941 /** \brief Configure PIO controllers to drive PMC signals */
2942 /**---------------------------------------------------------------------------- */
AT91F_PMC_CfgPIO(void)2943 __inline void AT91F_PMC_CfgPIO( void )
2944 {
2945 /* Configure PIO controllers to periph mode */
2946 AT91F_PIO_CfgPeriph(
2947 AT91C_BASE_PIOA, /* PIO controller base address */
2948 0, /* Peripheral A */
2949 ( ( unsigned int ) AT91C_PA17_PCK1 ) |
2950 ( ( unsigned int ) AT91C_PA21_PCK1 ) |
2951 ( ( unsigned int ) AT91C_PA31_PCK2 ) |
2952 ( ( unsigned int ) AT91C_PA18_PCK2 ) |
2953 ( ( unsigned int ) AT91C_PA6_PCK0 ) ); /* Peripheral B */
2954 }
2955
2956 /**---------------------------------------------------------------------------- */
2957 /** \fn AT91F_ADC_CfgPMC */
2958 /** \brief Enable Peripheral clock in PMC for ADC */
2959 /**---------------------------------------------------------------------------- */
AT91F_ADC_CfgPMC(void)2960 __inline void AT91F_ADC_CfgPMC( void )
2961 {
2962 AT91F_PMC_EnablePeriphClock(
2963 AT91C_BASE_PMC, /* PIO controller base address */
2964 ( ( unsigned int ) 1 << AT91C_ID_ADC ) );
2965 }
2966
2967 /**---------------------------------------------------------------------------- */
2968 /** \fn AT91F_ADC_CfgPIO */
2969 /** \brief Configure PIO controllers to drive ADC signals */
2970 /**---------------------------------------------------------------------------- */
AT91F_ADC_CfgPIO(void)2971 __inline void AT91F_ADC_CfgPIO( void )
2972 {
2973 /* Configure PIO controllers to periph mode */
2974 AT91F_PIO_CfgPeriph(
2975 AT91C_BASE_PIOA, /* PIO controller base address */
2976 0, /* Peripheral A */
2977 ( ( unsigned int ) AT91C_PA8_ADTRG ) ); /* Peripheral B */
2978 }
2979
2980 /**---------------------------------------------------------------------------- */
2981 /** \fn AT91F_PIOA_CfgPMC */
2982 /** \brief Enable Peripheral clock in PMC for PIOA */
2983 /**---------------------------------------------------------------------------- */
AT91F_PIOA_CfgPMC(void)2984 __inline void AT91F_PIOA_CfgPMC( void )
2985 {
2986 AT91F_PMC_EnablePeriphClock(
2987 AT91C_BASE_PMC, /* PIO controller base address */
2988 ( ( unsigned int ) 1 << AT91C_ID_PIOA ) );
2989 }
2990
2991 /**---------------------------------------------------------------------------- */
2992 /** \fn AT91F_TWI_CfgPMC */
2993 /** \brief Enable Peripheral clock in PMC for TWI */
2994 /**---------------------------------------------------------------------------- */
AT91F_TWI_CfgPMC(void)2995 __inline void AT91F_TWI_CfgPMC( void )
2996 {
2997 AT91F_PMC_EnablePeriphClock(
2998 AT91C_BASE_PMC, /* PIO controller base address */
2999 ( ( unsigned int ) 1 << AT91C_ID_TWI ) );
3000 }
3001
3002 /**---------------------------------------------------------------------------- */
3003 /** \fn AT91F_TWI_CfgPIO */
3004 /** \brief Configure PIO controllers to drive TWI signals */
3005 /**---------------------------------------------------------------------------- */
AT91F_TWI_CfgPIO(void)3006 __inline void AT91F_TWI_CfgPIO( void )
3007 {
3008 /* Configure PIO controllers to periph mode */
3009 AT91F_PIO_CfgPeriph(
3010 AT91C_BASE_PIOA, /* PIO controller base address */
3011 ( ( unsigned int ) AT91C_PA3_TWD ) |
3012 ( ( unsigned int ) AT91C_PA4_TWCK ), /* Peripheral A */
3013 0 ); /* Peripheral B */
3014 }
3015
3016 /**---------------------------------------------------------------------------- */
3017 /** \fn AT91F_US1_CfgPMC */
3018 /** \brief Enable Peripheral clock in PMC for US1 */
3019 /**---------------------------------------------------------------------------- */
AT91F_US1_CfgPMC(void)3020 __inline void AT91F_US1_CfgPMC( void )
3021 {
3022 AT91F_PMC_EnablePeriphClock(
3023 AT91C_BASE_PMC, /* PIO controller base address */
3024 ( ( unsigned int ) 1 << AT91C_ID_US1 ) );
3025 }
3026
3027 /**---------------------------------------------------------------------------- */
3028 /** \fn AT91F_US1_CfgPIO */
3029 /** \brief Configure PIO controllers to drive US1 signals */
3030 /**---------------------------------------------------------------------------- */
AT91F_US1_CfgPIO(void)3031 __inline void AT91F_US1_CfgPIO( void )
3032 {
3033 /* Configure PIO controllers to periph mode */
3034 AT91F_PIO_CfgPeriph(
3035 AT91C_BASE_PIOA, /* PIO controller base address */
3036 ( ( unsigned int ) AT91C_PA21_RXD1 ) |
3037 ( ( unsigned int ) AT91C_PA27_DTR1 ) |
3038 ( ( unsigned int ) AT91C_PA26_DCD1 ) |
3039 ( ( unsigned int ) AT91C_PA22_TXD1 ) |
3040 ( ( unsigned int ) AT91C_PA24_RTS1 ) |
3041 ( ( unsigned int ) AT91C_PA23_SCK1 ) |
3042 ( ( unsigned int ) AT91C_PA28_DSR1 ) |
3043 ( ( unsigned int ) AT91C_PA29_RI1 ) |
3044 ( ( unsigned int ) AT91C_PA25_CTS1 ), /* Peripheral A */
3045 0 ); /* Peripheral B */
3046 }
3047
3048 /**---------------------------------------------------------------------------- */
3049 /** \fn AT91F_US0_CfgPMC */
3050 /** \brief Enable Peripheral clock in PMC for US0 */
3051 /**---------------------------------------------------------------------------- */
AT91F_US0_CfgPMC(void)3052 __inline void AT91F_US0_CfgPMC( void )
3053 {
3054 AT91F_PMC_EnablePeriphClock(
3055 AT91C_BASE_PMC, /* PIO controller base address */
3056 ( ( unsigned int ) 1 << AT91C_ID_US0 ) );
3057 }
3058
3059 /**---------------------------------------------------------------------------- */
3060 /** \fn AT91F_US0_CfgPIO */
3061 /** \brief Configure PIO controllers to drive US0 signals */
3062 /**---------------------------------------------------------------------------- */
AT91F_US0_CfgPIO(void)3063 __inline void AT91F_US0_CfgPIO( void )
3064 {
3065 /* Configure PIO controllers to periph mode */
3066 AT91F_PIO_CfgPeriph(
3067 AT91C_BASE_PIOA, /* PIO controller base address */
3068 ( ( unsigned int ) AT91C_PA5_RXD0 ) |
3069 ( ( unsigned int ) AT91C_PA6_TXD0 ) |
3070 ( ( unsigned int ) AT91C_PA7_RTS0 ) |
3071 ( ( unsigned int ) AT91C_PA8_CTS0 ), /* Peripheral A */
3072 ( ( unsigned int ) AT91C_PA2_SCK0 ) ); /* Peripheral B */
3073 }
3074
3075 /**---------------------------------------------------------------------------- */
3076 /** \fn AT91F_UDP_CfgPMC */
3077 /** \brief Enable Peripheral clock in PMC for UDP */
3078 /**---------------------------------------------------------------------------- */
AT91F_UDP_CfgPMC(void)3079 __inline void AT91F_UDP_CfgPMC( void )
3080 {
3081 AT91F_PMC_EnablePeriphClock(
3082 AT91C_BASE_PMC, /* PIO controller base address */
3083 ( ( unsigned int ) 1 << AT91C_ID_UDP ) );
3084 }
3085
3086 /**---------------------------------------------------------------------------- */
3087 /** \fn AT91F_AIC_CfgPMC */
3088 /** \brief Enable Peripheral clock in PMC for AIC */
3089 /**---------------------------------------------------------------------------- */
AT91F_AIC_CfgPMC(void)3090 __inline void AT91F_AIC_CfgPMC( void )
3091 {
3092 AT91F_PMC_EnablePeriphClock(
3093 AT91C_BASE_PMC, /* PIO controller base address */
3094 ( ( unsigned int ) 1 << AT91C_ID_IRQ0 ) |
3095 ( ( unsigned int ) 1 << AT91C_ID_FIQ ) |
3096 ( ( unsigned int ) 1 << AT91C_ID_IRQ1 ) );
3097 }
3098
3099 /**---------------------------------------------------------------------------- */
3100 /** \fn AT91F_AIC_CfgPIO */
3101 /** \brief Configure PIO controllers to drive AIC signals */
3102 /**---------------------------------------------------------------------------- */
AT91F_AIC_CfgPIO(void)3103 __inline void AT91F_AIC_CfgPIO( void )
3104 {
3105 /* Configure PIO controllers to periph mode */
3106 AT91F_PIO_CfgPeriph(
3107 AT91C_BASE_PIOA, /* PIO controller base address */
3108 ( ( unsigned int ) AT91C_PA30_IRQ1 ), /* Peripheral A */
3109 ( ( unsigned int ) AT91C_PA20_IRQ0 ) |
3110 ( ( unsigned int ) AT91C_PA19_FIQ ) ); /* Peripheral B */
3111 }
3112
3113 #endif // lib_AT91SAM7S64_H
3114
