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Searched refs:portWORD_SIZE (Results 1 – 5 of 5) sorted by relevance

/Kernel-v11.0.1/portable/IAR/RISC-V/
DportContext.h33 #define portWORD_SIZE 8 macro
39 #define portWORD_SIZE 4 macro
52 #define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
56 #define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
70 store_x x1, 1 * portWORD_SIZE( sp )
71 store_x x5, 2 * portWORD_SIZE( sp )
72 store_x x6, 3 * portWORD_SIZE( sp )
73 store_x x7, 4 * portWORD_SIZE( sp )
74 store_x x8, 5 * portWORD_SIZE( sp )
75 store_x x9, 6 * portWORD_SIZE( sp )
[all …]
DportASM.s214 addi a0, a0, -portWORD_SIZE
216 addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
219 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-15. */
221 addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */
224 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */
230 addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
235 addi a0, a0, -portWORD_SIZE
248 load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
249 load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
250 load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
[all …]
/Kernel-v11.0.1/portable/GCC/RISC-V/
DportContext.h33 #define portWORD_SIZE 8 macro
39 #define portWORD_SIZE 4 macro
52 #define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
56 #define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
71 store_x x1, 1 * portWORD_SIZE( sp )
72 store_x x5, 2 * portWORD_SIZE( sp )
73 store_x x6, 3 * portWORD_SIZE( sp )
74 store_x x7, 4 * portWORD_SIZE( sp )
75 store_x x8, 5 * portWORD_SIZE( sp )
76 store_x x9, 6 * portWORD_SIZE( sp )
[all …]
DportASM.S205 addi a0, a0, -portWORD_SIZE
207 addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
211 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-x15. */
213 addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */
216 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */
222 addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
227 addi a0, a0, -portWORD_SIZE
240 load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
241 load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
242 load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
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/Kernel-v11.0.1/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/
Dfreertos_risc_v_chip_specific_extensions.h76 addi sp, sp, -( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Make room for the additional re…
83 sw t0, 1 * portWORD_SIZE( sp )
84 sw t1, 2 * portWORD_SIZE( sp )
85 sw t2, 3 * portWORD_SIZE( sp )
86 sw t3, 4 * portWORD_SIZE( sp )
87 sw t4, 5 * portWORD_SIZE( sp )
88 sw t5, 6 * portWORD_SIZE( sp )
93 lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */
94 lw t1, 2 * portWORD_SIZE( sp )
95 lw t2, 3 * portWORD_SIZE( sp )
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