Searched refs:AT91C_CKGR_USBDIV_2 (Results 1 – 8 of 8) sorted by relevance
326 #define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output d… macro
241 #define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output d… macro
378 #define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is P… macro
430 #define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is P… macro
430 #define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is P… macro2924 AT91C_CKGR_USBDIV_2 EQU( 0x2 << 28 );