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/Kernel-v10.6.2/portable/GCC/IA32_flat/
DISR_Support.h34 .macro portFREERTOS_INTERRUPT_ENTRY
79 .macro portINTERRUPT_EPILOGUE
121 .macro portFREERTOS_INTERRUPT_EXIT
/Kernel-v10.6.2/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/
Dfreertos_risc_v_chip_specific_extensions.h61 .macro portasmSAVE_ADDITIONAL_REGISTERS
65 .macro portasmRESTORE_ADDITIONAL_REGISTERS
/Kernel-v10.6.2/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/
Dfreertos_risc_v_chip_specific_extensions.h61 .macro portasmSAVE_ADDITIONAL_REGISTERS
65 .macro portasmRESTORE_ADDITIONAL_REGISTERS
/Kernel-v10.6.2/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/
Dfreertos_risc_v_chip_specific_extensions.h61 .macro portasmSAVE_ADDITIONAL_REGISTERS
65 .macro portasmRESTORE_ADDITIONAL_REGISTERS
/Kernel-v10.6.2/portable/ThirdParty/GCC/ARM_TFM/
DREADME.md48 This macro should be configured as 0. In this port, TF-M runs in the Secure Side while FreeRTOS
52 The setting of this macro is decided by the setting in Secure Side which is platform-specific.
53 …ide enables Non-Secure access to FPU, then this macro can be configured as 0 or 1. Otherwise, this…
58 The setting of this macro is decided by the setting in Secure Side which is platform-specific.
59 …ide enables Non-Secure access to MVE, then this macro can be configured as 0 or 1. Otherwise, this…
64 This macro should be configured as 0 because TF-M doesn't use the secure context management functio…
/Kernel-v10.6.2/portable/Rowley/MSP430F449/
Dportasm.h32 portSAVE_CONTEXT macro
53 portRESTORE_CONTEXT macro
/Kernel-v10.6.2/portable/IAR/MSP430/
Dportasm.h32 portSAVE_CONTEXT macro
57 portRESTORE_CONTEXT macro
/Kernel-v10.6.2/portable/GCC/RISC-V/
DportContext.h69 .macro portcontextSAVE_CONTEXT_INTERNAL
118 .macro portcontextSAVE_EXCEPTION_CONTEXT
128 .macro portcontextSAVE_INTERRUPT_CONTEXT
137 .macro portcontextRESTORE_CONTEXT
/Kernel-v10.6.2/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/
Dfreertos_risc_v_chip_specific_extensions.h75 .macro portasmSAVE_ADDITIONAL_REGISTERS
92 .macro portasmRESTORE_ADDITIONAL_REGISTERS
/Kernel-v10.6.2/portable/GCC/ColdFire_V2/
Dportasm.S45 .macro portSAVE_CONTEXT
54 .macro portRESTORE_CONTEXT
/Kernel-v10.6.2/portable/GCC/RL78/
Disr_support.h39 .macro portSAVE_CONTEXT
88 .macro portRESTORE_CONTEXT MACRO
/Kernel-v10.6.2/portable/CodeWarrior/ColdFire_V1/
Dportasm.S51 .macro portSAVE_CONTEXT
60 .macro portRESTORE_CONTEXT
/Kernel-v10.6.2/portable/CodeWarrior/ColdFire_V2/
Dportasm.S51 .macro portSAVE_CONTEXT
60 .macro portRESTORE_CONTEXT
/Kernel-v10.6.2/portable/CCS/MSP430X/
Dportext.asm47 portSAVE_CONTEXT .macro
58 portRESTORE_CONTEXT .macro
115 ; Manual context switch called by the portYIELD() macro.
/Kernel-v10.6.2/portable/IAR/MSP430X/
Dportext.s4342 portSAVE_CONTEXT macro
53 portRESTORE_CONTEXT macro
98 * Manual context switch called by the portYIELD() macro.
/Kernel-v10.6.2/portable/IAR/ARM_CA5_No_GIC/
DportASM.h35 portSAVE_CONTEXT macro variable
74 portRESTORE_CONTEXT macro
/Kernel-v10.6.2/portable/IAR/ARM_CA9/
DportASM.h35 portSAVE_CONTEXT macro variable
72 portRESTORE_CONTEXT macro
/Kernel-v10.6.2/portable/ThirdParty/GCC/Xtensa_ESP32/include/
Dxt_asm_utils.h51 .macro SPILL_ALL_WINDOWS
/Kernel-v10.6.2/portable/GCC/ARM_CRx_No_GIC/
DportASM.S52 .macro portSAVE_CONTEXT
91 .macro portRESTORE_CONTEXT
/Kernel-v10.6.2/portable/MPLAB/PIC32MEC14xx/
DISR_Support.h38 .macro portSAVE_CONTEXT
144 .macro portRESTORE_CONTEXT
/Kernel-v10.6.2/portable/MPLAB/PIC32MX/
DISR_Support.h36 .macro portSAVE_CONTEXT
126 .macro portRESTORE_CONTEXT
/Kernel-v10.6.2/portable/GCC/MicroBlaze/
Dportasm.s39 .macro portSAVE_CONTEXT
84 .macro portRESTORE_CONTEXT
/Kernel-v10.6.2/portable/Renesas/SH2A_FPU/
DISR_Support.inc28 .macro portSAVE_CONTEXT
51 .macro portRESTORE_CONTEXT
/Kernel-v10.6.2/portable/CCS/ARM_Cortex-R4/
DportASM.asm40 portSAVE_CONTEXT .macro
98 portRESTORE_CONTEXT .macro
/Kernel-v10.6.2/portable/ThirdParty/XCC/Xtensa/
Dxtensa_context.h333 .macro entry1 size=0x10
339 .macro ret1 size=0x10

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