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Searched refs:AT91C_PWMC_CH0_CDTYR (Results 1 – 6 of 6) sorted by relevance

/Kernel-v10.6.2/portable/IAR/AtmelSAM7S64/
DAT91SAM7X128_inc.h1903 #define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register macro
DAT91SAM7X256_inc.h1903 #define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register macro
DAT91SAM7X128.h2172 #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register macro
DAT91SAM7X256.h2172 #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register macro
/Kernel-v10.6.2/portable/GCC/ARM7_AT91SAM7S/
DAT91SAM7X256.h2172 #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register macro
Dioat91sam7x256.h2172 #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register macro
4153 AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register