Searched refs:AT91C_CKGR_USBDIV_2 (Results 1 – 8 of 8) sorted by relevance
326 #define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL cloc… macro
241 #define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL cloc… macro
372 #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider out… macro
424 #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider out… macro
424 #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider out… macro2826 AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
