Searched refs:AT91C_CKGR_USBDIV_0 (Results 1 – 8 of 8) sorted by relevance
324 #define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL cloc… macro
239 #define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL cloc… macro
370 #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider out… macro
422 #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider out… macro
422 #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider out… macro2824 AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
