1 /* 2 * copyright (c) 2006-2016 ARM Limited 3 * SPDX-License-Identifier: BSD-3-Clause 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3. Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************* 32 * File: smm_mps2.h 33 * Release: Version 1.1 34 *******************************************************************************/ 35 36 #ifndef __SMM_MPS2_H 37 #define __SMM_MPS2_H 38 39 #if defined( __CC_ARM ) 40 #pragma anon_unions 41 #endif 42 43 44 45 /******************************************************************************/ 46 /* FPGA System Register declaration */ 47 /******************************************************************************/ 48 49 typedef struct 50 { 51 volatile uint32_t LED; /* Offset: 0x000 (R/W) LED connections */ 52 /* [31:2] : Reserved */ 53 /* [1:0] : LEDs */ 54 uint32_t RESERVED1[ 1 ]; 55 volatile uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons */ 56 /* [31:2] : Reserved */ 57 /* [1:0] : Buttons */ 58 uint32_t RESERVED2[ 1 ]; 59 volatile uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */ 60 volatile uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */ 61 volatile uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter */ 62 /* Increments when 32-bit prescale counter reach zero */ 63 uint32_t RESERVED3[ 1 ]; 64 volatile uint32_t PRESCALE; /* Offset: 0x020 (R/W) Prescaler */ 65 /* Bit[31:0] : reload value for prescale counter */ 66 volatile uint32_t PSCNTR; /* Offset: 0x024 (R/W) 32-bit Prescale counter */ 67 /* current value of the pre-scaler counter */ 68 /* The Cycle Up Counter increment when the prescale down counter reach 0 */ 69 /* The pre-scaler counter is reloaded with PRESCALE after reaching 0. */ 70 uint32_t RESERVED4[ 9 ]; 71 volatile uint32_t MISC; /* Offset: 0x04C (R/W) Misc control * / */ 72 /* [31:10] : Reserved */ 73 /* [9] : SHIELD_1_SPI_nCS */ 74 /* [8] : SHIELD_0_SPI_nCS */ 75 /* [7] : ADC_SPI_nCS */ 76 /* [6] : CLCD_BL_CTRL */ 77 /* [5] : CLCD_RD */ 78 /* [4] : CLCD_RS */ 79 /* [3] : CLCD_RESET */ 80 /* [2] : RESERVED */ 81 /* [1] : SPI_nSS */ 82 /* [0] : CLCD_CS */ 83 } MPS2_FPGAIO_TypeDef; 84 85 /* MISC register bit definitions */ 86 87 #define CLCD_CS_Pos 0 88 #define CLCD_CS_Msk ( 1UL << CLCD_CS_Pos ) 89 #define SPI_nSS_Pos 1 90 #define SPI_nSS_Msk ( 1UL << SPI_nSS_Pos ) 91 #define CLCD_RESET_Pos 3 92 #define CLCD_RESET_Msk ( 1UL << CLCD_RESET_Pos ) 93 #define CLCD_RS_Pos 4 94 #define CLCD_RS_Msk ( 1UL << CLCD_RS_Pos ) 95 #define CLCD_RD_Pos 5 96 #define CLCD_RD_Msk ( 1UL << CLCD_RD_Pos ) 97 #define CLCD_BL_Pos 6 98 #define CLCD_BL_Msk ( 1UL << CLCD_BL_Pos ) 99 #define ADC_nCS_Pos 7 100 #define ADC_nCS_Msk ( 1UL << ADC_nCS_Pos ) 101 #define SHIELD_0_nCS_Pos 8 102 #define SHIELD_0_nCS_Msk ( 1UL << SHIELD_0_nCS_Pos ) 103 #define SHIELD_1_nCS_Pos 9 104 #define SHIELD_1_nCS_Msk ( 1UL << SHIELD_1_nCS_Pos ) 105 106 /******************************************************************************/ 107 /* SCC Register declaration */ 108 /******************************************************************************/ 109 110 typedef struct /* */ 111 { 112 volatile uint32_t CFG_REG0; /* Offset: 0x000 (R/W) Remaps block RAM to ZBT */ 113 /* [31:1] : Reserved */ 114 /* [0] 1 : REMAP BlockRam to ZBT */ 115 volatile uint32_t LEDS; /* Offset: 0x004 (R/W) Controls the MCC user LEDs */ 116 /* [31:8] : Reserved */ 117 /* [7:0] : MCC LEDs */ 118 uint32_t RESERVED0[ 1 ]; 119 volatile uint32_t SWITCHES; /* Offset: 0x00C (R/ ) Denotes the state of the MCC user switches */ 120 /* [31:8] : Reserved */ 121 /* [7:0] : These bits indicate state of the MCC switches */ 122 volatile uint32_t CFG_REG4; /* Offset: 0x010 (R/ ) Denotes the board revision */ 123 /* [31:4] : Reserved */ 124 /* [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B */ 125 uint32_t RESERVED1[ 35 ]; 126 volatile uint32_t SYS_CFGDATA_RTN; /* Offset: 0x0A0 (R/W) User data register */ 127 /* [31:0] : Data */ 128 volatile uint32_t SYS_CFGDATA_OUT; /* Offset: 0x0A4 (R/W) User data register */ 129 /* [31:0] : Data */ 130 volatile uint32_t SYS_CFGCTRL; /* Offset: 0x0A8 (R/W) Control register */ 131 /* [31] : Start (generates interrupt on write to this bit) */ 132 /* [30] : R/W access */ 133 /* [29:26] : Reserved */ 134 /* [25:20] : Function value */ 135 /* [19:12] : Reserved */ 136 /* [11:0] : Device (value of 0/1/2 for supported clocks) */ 137 volatile uint32_t SYS_CFGSTAT; /* Offset: 0x0AC (R/W) Contains status information */ 138 /* [31:2] : Reserved */ 139 /* [1] : Error */ 140 /* [0] : Complete */ 141 volatile uint32_t RESERVED2[ 20 ]; 142 volatile uint32_t SCC_DLL; /* Offset: 0x100 (R/W) DLL Lock Register */ 143 /* [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked */ 144 /* [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked */ 145 /* [15:1] : Reserved */ 146 /* [0] : This bit indicates if all enabled DLLs are locked */ 147 uint32_t RESERVED3[ 957 ]; 148 volatile uint32_t SCC_AID; /* Offset: 0xFF8 (R/ ) SCC AID Register */ 149 /* [31:24] : FPGA build number */ 150 /* [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) */ 151 /* [19:11] : Reserved */ 152 /* [10] : if "1" SCC_SW register has been implemented */ 153 /* [9] : if "1" SCC_LED register has been implemented */ 154 /* [8] : if "1" DLL lock register has been implemented */ 155 /* [7:0] : number of SCC configuration register */ 156 volatile uint32_t SCC_ID; /* Offset: 0xFFC (R/ ) Contains information about the FPGA image */ 157 /* [31:24] : Implementer ID: 0x41 = ARM */ 158 /* [23:20] : Application note IP variant number */ 159 /* [19:16] : IP Architecture: 0x4 =AHB */ 160 /* [15:4] : Primary part number: 386 = AN386 */ 161 /* [3:0] : Application note IP revision number */ 162 } MPS2_SCC_TypeDef; 163 164 165 /******************************************************************************/ 166 /* SSP Peripheral declaration */ 167 /******************************************************************************/ 168 169 typedef struct /* Document DDI0194G_ssp_pl022_r1p3_trm.pdf */ 170 { 171 volatile uint32_t CR0; /* Offset: 0x000 (R/W) Control register 0 */ 172 /* [31:16] : Reserved */ 173 /* [15:8] : Serial clock rate */ 174 /* [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only */ 175 /* [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only */ 176 /* [5:4] : Frame format */ 177 /* [3:0] : Data Size Select */ 178 volatile uint32_t CR1; /* Offset: 0x004 (R/W) Control register 1 */ 179 /* [31:4] : Reserved */ 180 /* [3] : Slave-mode output disable */ 181 /* [2] : Master or slave mode select */ 182 /* [1] : Synchronous serial port enable */ 183 /* [0] : Loop back mode */ 184 volatile uint32_t DR; /* Offset: 0x008 (R/W) Data register */ 185 /* [31:16] : Reserved */ 186 /* [15:0] : Transmit/Receive FIFO */ 187 volatile uint32_t SR; /* Offset: 0x00C (R/ ) Status register */ 188 /* [31:5] : Reserved */ 189 /* [4] : PrimeCell SSP busy flag */ 190 /* [3] : Receive FIFO full */ 191 /* [2] : Receive FIFO not empty */ 192 /* [1] : Transmit FIFO not full */ 193 /* [0] : Transmit FIFO empty */ 194 volatile uint32_t CPSR; /* Offset: 0x010 (R/W) Clock prescale register */ 195 /* [31:8] : Reserved */ 196 /* [8:0] : Clock prescale divisor */ 197 volatile uint32_t IMSC; /* Offset: 0x014 (R/W) Interrupt mask set or clear register */ 198 /* [31:4] : Reserved */ 199 /* [3] : Transmit FIFO interrupt mask */ 200 /* [2] : Receive FIFO interrupt mask */ 201 /* [1] : Receive timeout interrupt mask */ 202 /* [0] : Receive overrun interrupt mask */ 203 volatile uint32_t RIS; /* Offset: 0x018 (R/ ) Raw interrupt status register */ 204 /* [31:4] : Reserved */ 205 /* [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt */ 206 /* [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt */ 207 /* [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt */ 208 /* [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt */ 209 volatile uint32_t MIS; /* Offset: 0x01C (R/ ) Masked interrupt status register */ 210 /* [31:4] : Reserved */ 211 /* [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt */ 212 /* [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt */ 213 /* [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt */ 214 /* [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt */ 215 volatile uint32_t ICR; /* Offset: 0x020 ( /W) Interrupt clear register */ 216 /* [31:2] : Reserved */ 217 /* [1] : Clears the SSPRTINTR interrupt */ 218 /* [0] : Clears the SSPRORINTR interrupt */ 219 volatile uint32_t DMACR; /* Offset: 0x024 (R/W) DMA control register */ 220 /* [31:2] : Reserved */ 221 /* [1] : Transmit DMA Enable */ 222 /* [0] : Receive DMA Enable */ 223 } MPS2_SSP_TypeDef; 224 225 226 /* SSP_CR0 Control register 0 */ 227 #define SSP_CR0_DSS_Pos 0 /* Data Size Select */ 228 #define SSP_CR0_DSS_Msk ( 0xF << SSP_CR0_DSS_Pos ) 229 #define SSP_CR0_FRF_Pos 4 /* Frame Format Select */ 230 #define SSP_CR0_FRF_Msk ( 3UL << SSP_CR0_FRM_Pos ) 231 #define SSP_CR0_SPO_Pos 6 /* SSPCLKOUT polarity */ 232 #define SSP_CR0_SPO_Msk ( 1UL << SSP_CR0_SPO_Pos ) 233 #define SSP_CR0_SPH_Pos 7 /* SSPCLKOUT phase */ 234 #define SSP_CR0_SPH_Msk ( 1UL << SSP_CR0_SPH_Pos ) 235 #define SSP_CR0_SCR_Pos 8 /* Serial Clock Rate (divide) */ 236 #define SSP_CR0_SCR_Msk ( 0xFF << SSP_CR0_SCR_Pos ) 237 238 #define SSP_CR0_SCR_DFLT 0x0300 /* Serial Clock Rate (divide), default set at 3 */ 239 #define SSP_CR0_FRF_MOT 0x0000 /* Frame format, Motorola */ 240 #define SSP_CR0_DSS_8 0x0007 /* Data packet size, 8bits */ 241 #define SSP_CR0_DSS_16 0x000F /* Data packet size, 16bits */ 242 243 /* SSP_CR1 Control register 1 */ 244 #define SSP_CR1_LBM_Pos 0 /* Loop Back Mode */ 245 #define SSP_CR1_LBM_Msk ( 1UL << SSP_CR1_LBM_Pos ) 246 #define SSP_CR1_SSE_Pos 1 /* Serial port enable */ 247 #define SSP_CR1_SSE_Msk ( 1UL << SSP_CR1_SSE_Pos ) 248 #define SSP_CR1_MS_Pos 2 /* Master or Slave mode */ 249 #define SSP_CR1_MS_Msk ( 1UL << SSP_CR1_MS_Pos ) 250 #define SSP_CR1_SOD_Pos 3 /* Slave Output mode Disable */ 251 #define SSP_CR1_SOD_Msk ( 1UL << SSP_CR1_SOD_Pos ) 252 253 /* SSP_SR Status register */ 254 #define SSP_SR_TFE_Pos 0 /* Transmit FIFO empty */ 255 #define SSP_SR_TFE_Msk ( 1UL << SSP_SR_TFE_Pos ) 256 #define SSP_SR_TNF_Pos 1 /* Transmit FIFO not full */ 257 #define SSP_SR_TNF_Msk ( 1UL << SSP_SR_TNF_Pos ) 258 #define SSP_SR_RNE_Pos 2 /* Receive FIFO not empty */ 259 #define SSP_SR_RNE_Msk ( 1UL << SSP_SR_RNE_Pos ) 260 #define SSP_SR_RFF_Pos 3 /* Receive FIFO full */ 261 #define SSP_SR_RFF_Msk ( 1UL << SSP_SR_RFF_Pos ) 262 #define SSP_SR_BSY_Pos 4 /* Busy */ 263 #define SSP_SR_BSY_Msk ( 1UL << SSP_SR_BSY_Pos ) 264 265 /* SSP_CPSR Clock prescale register */ 266 #define SSP_CPSR_CPD_Pos 0 /* Clock prescale divisor */ 267 #define SSP_CPSR_CPD_Msk ( 0xFF << SSP_CPSR_CDP_Pos ) 268 269 #define SSP_CPSR_DFLT 0x0008 /* Clock prescale (use with SCR), default set at 8 */ 270 271 /* SSPIMSC Interrupt mask set and clear register */ 272 #define SSP_IMSC_RORIM_Pos 0 /* Receive overrun not Masked */ 273 #define SSP_IMSC_RORIM_Msk ( 1UL << SSP_IMSC_RORIM_Pos ) 274 #define SSP_IMSC_RTIM_Pos 1 /* Receive timeout not Masked */ 275 #define SSP_IMSC_RTIM_Msk ( 1UL << SSP_IMSC_RTIM_Pos ) 276 #define SSP_IMSC_RXIM_Pos 2 /* Receive FIFO not Masked */ 277 #define SSP_IMSC_RXIM_Msk ( 1UL << SSP_IMSC_RXIM_Pos ) 278 #define SSP_IMSC_TXIM_Pos 3 /* Transmit FIFO not Masked */ 279 #define SSP_IMSC_TXIM_Msk ( 1UL << SSP_IMSC_TXIM_Pos ) 280 281 /* SSPRIS Raw interrupt status register */ 282 #define SSP_RIS_RORRIS_Pos 0 /* Raw Overrun interrupt flag */ 283 #define SSP_RIS_RORRIS_Msk ( 1UL << SSP_RIS_RORRIS_Pos ) 284 #define SSP_RIS_RTRIS_Pos 1 /* Raw Timemout interrupt flag */ 285 #define SSP_RIS_RTRIS_Msk ( 1UL << SSP_RIS_RTRIS_Pos ) 286 #define SSP_RIS_RXRIS_Pos 2 /* Raw Receive interrupt flag */ 287 #define SSP_RIS_RXRIS_Msk ( 1UL << SSP_RIS_RXRIS_Pos ) 288 #define SSP_RIS_TXRIS_Pos 3 /* Raw Transmit interrupt flag */ 289 #define SSP_RIS_TXRIS_Msk ( 1UL << SSP_RIS_TXRIS_Pos ) 290 291 /* SSPMIS Masked interrupt status register */ 292 #define SSP_MIS_RORMIS_Pos 0 /* Masked Overrun interrupt flag */ 293 #define SSP_MIS_RORMIS_Msk ( 1UL << SSP_MIS_RORMIS_Pos ) 294 #define SSP_MIS_RTMIS_Pos 1 /* Masked Timemout interrupt flag */ 295 #define SSP_MIS_RTMIS_Msk ( 1UL << SSP_MIS_RTMIS_Pos ) 296 #define SSP_MIS_RXMIS_Pos 2 /* Masked Receive interrupt flag */ 297 #define SSP_MIS_RXMIS_Msk ( 1UL << SSP_MIS_RXMIS_Pos ) 298 #define SSP_MIS_TXMIS_Pos 3 /* Masked Transmit interrupt flag */ 299 #define SSP_MIS_TXMIS_Msk ( 1UL << SSP_MIS_TXMIS_Pos ) 300 301 /* SSPICR Interrupt clear register */ 302 #define SSP_ICR_RORIC_Pos 0 /* Clears Overrun interrupt flag */ 303 #define SSP_ICR_RORIC_Msk ( 1UL << SSP_ICR_RORIC_Pos ) 304 #define SSP_ICR_RTIC_Pos 1 /* Clears Timemout interrupt flag */ 305 #define SSP_ICR_RTIC_Msk ( 1UL << SSP_ICR_RTIC_Pos ) 306 307 /* SSPDMACR DMA control register */ 308 #define SSP_DMACR_RXDMAE_Pos 0 /* Enable Receive FIFO DMA */ 309 #define SSP_DMACR_RXDMAE_Msk ( 1UL << SSP_DMACR_RXDMAE_Pos ) 310 #define SSP_DMACR_TXDMAE_Pos 1 /* Enable Transmit FIFO DMA */ 311 #define SSP_DMACR_TXDMAE_Msk ( 1UL << SSP_DMACR_TXDMAE_Pos ) 312 313 /******************************************************************************/ 314 /* Audio and Touch Screen (I2C) Peripheral declaration */ 315 /******************************************************************************/ 316 317 typedef struct 318 { 319 union 320 { 321 volatile uint32_t CONTROLS; /* Offset: 0x000 CONTROL Set Register ( /W) */ 322 volatile uint32_t CONTROL; /* Offset: 0x000 CONTROL Status Register (R/ ) */ 323 }; 324 volatile uint32_t CONTROLC; /* Offset: 0x004 CONTROL Clear Register ( /W) */ 325 } MPS2_I2C_TypeDef; 326 327 #define SDA 1 << 1 328 #define SCL 1 << 0 329 330 331 /******************************************************************************/ 332 /* Audio I2S Peripheral declaration */ 333 /******************************************************************************/ 334 335 typedef struct 336 { 337 /*!< Offset: 0x000 CONTROL Register (R/W) */ 338 volatile uint32_t CONTROL; /* <h> CONTROL </h> */ 339 /* <o.0> TX Enable */ 340 /* <0=> TX disabled */ 341 /* <1=> TX enabled */ 342 /* <o.1> TX IRQ Enable */ 343 /* <0=> TX IRQ disabled */ 344 /* <1=> TX IRQ enabled */ 345 /* <o.2> RX Enable */ 346 /* <0=> RX disabled */ 347 /* <1=> RX enabled */ 348 /* <o.3> RX IRQ Enable */ 349 /* <0=> RX IRQ disabled */ 350 /* <1=> RX IRQ enabled */ 351 /* <o.10..8> TX Buffer Water Level */ 352 /* <0=> / IRQ triggers when any space available */ 353 /* <1=> / IRQ triggers when more than 1 space available */ 354 /* <2=> / IRQ triggers when more than 2 space available */ 355 /* <3=> / IRQ triggers when more than 3 space available */ 356 /* <4=> Undefined! */ 357 /* <5=> Undefined! */ 358 /* <6=> Undefined! */ 359 /* <7=> Undefined! */ 360 /* <o.14..12> RX Buffer Water Level */ 361 /* <0=> Undefined! */ 362 /* <1=> / IRQ triggers when less than 1 space available */ 363 /* <2=> / IRQ triggers when less than 2 space available */ 364 /* <3=> / IRQ triggers when less than 3 space available */ 365 /* <4=> / IRQ triggers when less than 4 space available */ 366 /* <5=> Undefined! */ 367 /* <6=> Undefined! */ 368 /* <7=> Undefined! */ 369 /* <o.16> FIFO reset */ 370 /* <0=> Normal operation */ 371 /* <1=> FIFO reset */ 372 /* <o.17> Audio Codec reset */ 373 /* <0=> Normal operation */ 374 /* <1=> Assert audio Codec reset */ 375 /*!< Offset: 0x004 STATUS Register (R/ ) */ 376 volatile uint32_t STATUS; /* <h> STATUS </h> */ 377 /* <o.0> TX Buffer alert */ 378 /* <0=> TX buffer don't need service yet */ 379 /* <1=> TX buffer need service */ 380 /* <o.1> RX Buffer alert */ 381 /* <0=> RX buffer don't need service yet */ 382 /* <1=> RX buffer need service */ 383 /* <o.2> TX Buffer Empty */ 384 /* <0=> TX buffer have data */ 385 /* <1=> TX buffer empty */ 386 /* <o.3> TX Buffer Full */ 387 /* <0=> TX buffer not full */ 388 /* <1=> TX buffer full */ 389 /* <o.4> RX Buffer Empty */ 390 /* <0=> RX buffer have data */ 391 /* <1=> RX buffer empty */ 392 /* <o.5> RX Buffer Full */ 393 /* <0=> RX buffer not full */ 394 /* <1=> RX buffer full */ 395 union 396 { 397 /*!< Offset: 0x008 Error Status Register (R/ ) */ 398 volatile uint32_t ERROR; /* <h> ERROR </h> */ 399 /* <o.0> TX error */ 400 /* <0=> Okay */ 401 /* <1=> TX overrun/underrun */ 402 /* <o.1> RX error */ 403 /* <0=> Okay */ 404 /* <1=> RX overrun/underrun */ 405 /*!< Offset: 0x008 Error Clear Register ( /W) */ 406 volatile uint32_t ERRORCLR; /* <h> ERRORCLR </h> */ 407 /* <o.0> TX error */ 408 /* <0=> Okay */ 409 /* <1=> Clear TX error */ 410 /* <o.1> RX error */ 411 /* <0=> Okay */ 412 /* <1=> Clear RX error */ 413 }; 414 /*!< Offset: 0x00C Divide ratio Register (R/W) */ 415 volatile uint32_t DIVIDE; /* <h> Divide ratio for Left/Right clock </h> */ 416 /* <o.9..0> TX error (default 0x80) */ 417 /*!< Offset: 0x010 Transmit Buffer ( /W) */ 418 volatile uint32_t TXBUF; /* <h> Transmit buffer </h> */ 419 /* <o.15..0> Right channel */ 420 /* <o.31..16> Left channel */ 421 /*!< Offset: 0x014 Receive Buffer (R/ ) */ 422 volatile uint32_t RXBUF; /* <h> Receive buffer </h> */ 423 /* <o.15..0> Right channel */ 424 /* <o.31..16> Left channel */ 425 uint32_t RESERVED1[ 186 ]; 426 volatile uint32_t ITCR; /* <h> Integration Test Control Register </h> */ 427 /* <o.0> ITEN */ 428 /* <0=> Normal operation */ 429 /* <1=> Integration Test mode enable */ 430 volatile uint32_t ITIP1; /* <h> Integration Test Input Register 1</h> */ 431 /* <o.0> SDIN */ 432 volatile uint32_t ITOP1; /* <h> Integration Test Output Register 1</h> */ 433 /* <o.0> SDOUT */ 434 /* <o.1> SCLK */ 435 /* <o.2> LRCK */ 436 /* <o.3> IRQOUT */ 437 } MPS2_I2S_TypeDef; 438 439 #define I2S_CONTROL_TXEN_Pos 0 440 #define I2S_CONTROL_TXEN_Msk ( 1UL << I2S_CONTROL_TXEN_Pos ) 441 442 #define I2S_CONTROL_TXIRQEN_Pos 1 443 #define I2S_CONTROL_TXIRQEN_Msk ( 1UL << I2S_CONTROL_TXIRQEN_Pos ) 444 445 #define I2S_CONTROL_RXEN_Pos 2 446 #define I2S_CONTROL_RXEN_Msk ( 1UL << I2S_CONTROL_RXEN_Pos ) 447 448 #define I2S_CONTROL_RXIRQEN_Pos 3 449 #define I2S_CONTROL_RXIRQEN_Msk ( 1UL << I2S_CONTROL_RXIRQEN_Pos ) 450 451 #define I2S_CONTROL_TXWLVL_Pos 8 452 #define I2S_CONTROL_TXWLVL_Msk ( 7UL << I2S_CONTROL_TXWLVL_Pos ) 453 454 #define I2S_CONTROL_RXWLVL_Pos 12 455 #define I2S_CONTROL_RXWLVL_Msk ( 7UL << I2S_CONTROL_RXWLVL_Pos ) 456 /* FIFO reset*/ 457 #define I2S_CONTROL_FIFORST_Pos 16 458 #define I2S_CONTROL_FIFORST_Msk ( 1UL << I2S_CONTROL_FIFORST_Pos ) 459 /* Codec reset*/ 460 #define I2S_CONTROL_CODECRST_Pos 17 461 #define I2S_CONTROL_CODECRST_Msk ( 1UL << I2S_CONTROL_CODECRST_Pos ) 462 463 #define I2S_STATUS_TXIRQ_Pos 0 464 #define I2S_STATUS_TXIRQ_Msk ( 1UL << I2S_STATUS_TXIRQ_Pos ) 465 466 #define I2S_STATUS_RXIRQ_Pos 1 467 #define I2S_STATUS_RXIRQ_Msk ( 1UL << I2S_STATUS_RXIRQ_Pos ) 468 469 #define I2S_STATUS_TXEmpty_Pos 2 470 #define I2S_STATUS_TXEmpty_Msk ( 1UL << I2S_STATUS_TXEmpty_Pos ) 471 472 #define I2S_STATUS_TXFull_Pos 3 473 #define I2S_STATUS_TXFull_Msk ( 1UL << I2S_STATUS_TXFull_Pos ) 474 475 #define I2S_STATUS_RXEmpty_Pos 4 476 #define I2S_STATUS_RXEmpty_Msk ( 1UL << I2S_STATUS_RXEmpty_Pos ) 477 478 #define I2S_STATUS_RXFull_Pos 5 479 #define I2S_STATUS_RXFull_Msk ( 1UL << I2S_STATUS_RXFull_Pos ) 480 481 #define I2S_ERROR_TXERR_Pos 0 482 #define I2S_ERROR_TXERR_Msk ( 1UL << I2S_ERROR_TXERR_Pos ) 483 484 #define I2S_ERROR_RXERR_Pos 1 485 #define I2S_ERROR_RXERR_Msk ( 1UL << I2S_ERROR_RXERR_Pos ) 486 487 /******************************************************************************/ 488 /* SMSC9220 Register Definitions */ 489 /******************************************************************************/ 490 491 typedef struct /* SMSC LAN9220 */ 492 { 493 volatile uint32_t RX_DATA_PORT; /* Receive FIFO Ports (offset 0x0) */ 494 uint32_t RESERVED1[ 0x7 ]; 495 volatile uint32_t TX_DATA_PORT; /* Transmit FIFO Ports (offset 0x20) */ 496 uint32_t RESERVED2[ 0x7 ]; 497 498 volatile uint32_t RX_STAT_PORT; /* Receive FIFO status port (offset 0x40) */ 499 volatile uint32_t RX_STAT_PEEK; /* Receive FIFO status peek (offset 0x44) */ 500 volatile uint32_t TX_STAT_PORT; /* Transmit FIFO status port (offset 0x48) */ 501 volatile uint32_t TX_STAT_PEEK; /* Transmit FIFO status peek (offset 0x4C) */ 502 503 volatile uint32_t ID_REV; /* Chip ID and Revision (offset 0x50) */ 504 volatile uint32_t IRQ_CFG; /* Main Interrupt Configuration (offset 0x54) */ 505 volatile uint32_t INT_STS; /* Interrupt Status (offset 0x58) */ 506 volatile uint32_t INT_EN; /* Interrupt Enable Register (offset 0x5C) */ 507 uint32_t RESERVED3; /* Reserved for future use (offset 0x60) */ 508 volatile uint32_t BYTE_TEST; /* Read-only byte order testing register 87654321h (offset 0x64) */ 509 volatile uint32_t FIFO_INT; /* FIFO Level Interrupts (offset 0x68) */ 510 volatile uint32_t RX_CFG; /* Receive Configuration (offset 0x6C) */ 511 volatile uint32_t TX_CFG; /* Transmit Configuration (offset 0x70) */ 512 volatile uint32_t HW_CFG; /* Hardware Configuration (offset 0x74) */ 513 volatile uint32_t RX_DP_CTL; /* RX Datapath Control (offset 0x78) */ 514 volatile uint32_t RX_FIFO_INF; /* Receive FIFO Information (offset 0x7C) */ 515 volatile uint32_t TX_FIFO_INF; /* Transmit FIFO Information (offset 0x80) */ 516 volatile uint32_t PMT_CTRL; /* Power Management Control (offset 0x84) */ 517 volatile uint32_t GPIO_CFG; /* General Purpose IO Configuration (offset 0x88) */ 518 volatile uint32_t GPT_CFG; /* General Purpose Timer Configuration (offset 0x8C) */ 519 volatile uint32_t GPT_CNT; /* General Purpose Timer Count (offset 0x90) */ 520 uint32_t RESERVED4; /* Reserved for future use (offset 0x94) */ 521 volatile uint32_t ENDIAN; /* WORD SWAP Register (offset 0x98) */ 522 volatile uint32_t FREE_RUN; /* Free Run Counter (offset 0x9C) */ 523 volatile uint32_t RX_DROP; /* RX Dropped Frames Counter (offset 0xA0) */ 524 volatile uint32_t MAC_CSR_CMD; /* MAC CSR Synchronizer Command (offset 0xA4) */ 525 volatile uint32_t MAC_CSR_DATA; /* MAC CSR Synchronizer Data (offset 0xA8) */ 526 volatile uint32_t AFC_CFG; /* Automatic Flow Control Configuration (offset 0xAC) */ 527 volatile uint32_t E2P_CMD; /* EEPROM Command (offset 0xB0) */ 528 volatile uint32_t E2P_DATA; /* EEPROM Data (offset 0xB4) */ 529 } SMSC9220_TypeDef; 530 531 /* SMSC9220 MAC Registers Indices */ 532 #define SMSC9220_MAC_CR 0x1 533 #define SMSC9220_MAC_ADDRH 0x2 534 #define SMSC9220_MAC_ADDRL 0x3 535 #define SMSC9220_MAC_HASHH 0x4 536 #define SMSC9220_MAC_HASHL 0x5 537 #define SMSC9220_MAC_MII_ACC 0x6 538 #define SMSC9220_MAC_MII_DATA 0x7 539 #define SMSC9220_MAC_FLOW 0x8 540 #define SMSC9220_MAC_VLAN1 0x9 541 #define SMSC9220_MAC_VLAN2 0xA 542 #define SMSC9220_MAC_WUFF 0xB 543 #define SMSC9220_MAC_WUCSR 0xC 544 545 /* SMSC9220 PHY Registers Indices */ 546 #define SMSC9220_PHY_BCONTROL 0x0 547 #define SMSC9220_PHY_BSTATUS 0x1 548 #define SMSC9220_PHY_ID1 0x2 549 #define SMSC9220_PHY_ID2 0x3 550 #define SMSC9220_PHY_ANEG_ADV 0x4 551 #define SMSC9220_PHY_ANEG_LPA 0x5 552 #define SMSC9220_PHY_ANEG_EXP 0x6 553 #define SMSC9220_PHY_MCONTROL 0x17 554 #define SMSC9220_PHY_MSTATUS 0x18 555 #define SMSC9220_PHY_CSINDICATE 0x27 556 #define SMSC9220_PHY_INTSRC 0x29 557 #define SMSC9220_PHY_INTMASK 0x30 558 #define SMSC9220_PHY_CS 0x31 559 560 /******************************************************************************/ 561 /* Peripheral memory map */ 562 /******************************************************************************/ 563 564 #define MPS2_SSP1_BASE ( 0x40020000ul ) /* User SSP Base Address */ 565 #define MPS2_SSP0_BASE ( 0x40021000ul ) /* CLCD SSP Base Address */ 566 #define MPS2_TSC_I2C_BASE ( 0x40022000ul ) /* Touch Screen I2C Base Address */ 567 #define MPS2_AAIC_I2C_BASE ( 0x40023000ul ) /* Audio Interface I2C Base Address */ 568 #define MPS2_AAIC_I2S_BASE ( 0x40024000ul ) /* Audio Interface I2S Base Address */ 569 #define MPS2_SSP2_BASE ( 0x40025000ul ) /* adc SSP Base Address */ 570 #define MPS2_SSP3_BASE ( 0x40026000ul ) /* Shield 0 SSP Base Address */ 571 #define MPS2_SSP4_BASE ( 0x40027000ul ) /* Shield 1 SSP Base Address */ 572 #define MPS2_FPGAIO_BASE ( 0x40028000ul ) /* FPGAIO Base Address */ 573 #define MPS2_SHIELD0_I2C_BASE ( 0x40029000ul ) /* Shield 0 I2C Base Address */ 574 #define MPS2_SHIELD1_I2C_BASE ( 0x4002A000ul ) /* Shield 1 I2C Base Address */ 575 #define MPS2_SCC_BASE ( 0x4002F000ul ) /* SCC Base Address */ 576 577 #ifdef CORTEX_M7 578 #define SMSC9220_BASE ( 0xA0000000ul ) /* Ethernet SMSC9220 Base Address */ 579 #else 580 #define SMSC9220_BASE ( 0x40200000ul ) /* Ethernet SMSC9220 Base Address */ 581 #endif 582 583 #define MPS2_VGA_TEXT_BUFFER ( 0x41000000ul ) /* VGA Text Buffer Address */ 584 #define MPS2_VGA_BUFFER ( 0x41100000ul ) /* VGA Buffer Base Address */ 585 586 /******************************************************************************/ 587 /* Peripheral declaration */ 588 /******************************************************************************/ 589 590 #define SMSC9220 ( ( SMSC9220_TypeDef * ) SMSC9220_BASE ) 591 #define MPS2_TS_I2C ( ( MPS2_I2C_TypeDef * ) MPS2_TSC_I2C_BASE ) 592 #define MPS2_AAIC_I2C ( ( MPS2_I2C_TypeDef * ) MPS2_AAIC_I2C_BASE ) 593 #define MPS2_SHIELD0_I2C ( ( MPS2_I2C_TypeDef * ) MPS2_SHIELD0_I2C_BASE ) 594 #define MPS2_SHIELD1_I2C ( ( MPS2_I2C_TypeDef * ) MPS2_SHIELD1_I2C_BASE ) 595 #define MPS2_AAIC_I2S ( ( MPS2_I2S_TypeDef * ) MPS2_AAIC_I2S_BASE ) 596 #define MPS2_FPGAIO ( ( MPS2_FPGAIO_TypeDef * ) MPS2_FPGAIO_BASE ) 597 #define MPS2_SCC ( ( MPS2_SCC_TypeDef * ) MPS2_SCC_BASE ) 598 #define MPS2_SSP0 ( ( MPS2_SSP_TypeDef * ) MPS2_SSP0_BASE ) 599 #define MPS2_SSP1 ( ( MPS2_SSP_TypeDef * ) MPS2_SSP1_BASE ) 600 #define MPS2_SSP2 ( ( MPS2_SSP_TypeDef * ) MPS2_SSP2_BASE ) 601 #define MPS2_SSP3 ( ( MPS2_SSP_TypeDef * ) MPS2_SSP3_BASE ) 602 #define MPS2_SSP4 ( ( MPS2_SSP_TypeDef * ) MPS2_SSP4_BASE ) 603 604 /******************************************************************************/ 605 /* General Function Definitions */ 606 /******************************************************************************/ 607 608 609 /******************************************************************************/ 610 /* General MACRO Definitions */ 611 /******************************************************************************/ 612 613 614 615 #endif /* __SMM_MPS2_H */ 616
xref:
/FreeRTOS-Plus-TCP-v4.0.0/source/portable/NetworkInterface/MPS2_AN385/ether_lan9118/SMM_MPS2.h
(revision a4124602cc584fa0658448c229f48a459a84fbb1)