1 /** 2 * \file 3 * 4 * Copyright (c) 2012 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 42 #ifndef _SAM4E_GMAC_COMPONENT_ 43 #define _SAM4E_GMAC_COMPONENT_ 44 45 /* ============================================================================= */ 46 /** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ 47 /* ============================================================================= */ 48 /** \addtogroup SAM4E_GMAC Gigabit Ethernet MAC */ 49 /*@{*/ 50 51 #if !( defined( __ASSEMBLY__ ) || defined( __IAR_SYSTEMS_ASM__ ) ) 52 /** \brief GmacSa hardware registers */ 53 typedef struct 54 { 55 RwReg GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom [31:0] Register */ 56 RwReg GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top [47:32] Register */ 57 } GmacSa; 58 /** \brief Gmac hardware registers */ 59 #define GMACSA_NUMBER 4 60 typedef struct 61 { 62 RwReg GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ 63 RwReg GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ 64 RoReg GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ 65 RwReg GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ 66 RwReg GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ 67 RwReg GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ 68 RwReg GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address */ 69 RwReg GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address */ 70 RwReg GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ 71 RoReg GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ 72 WoReg GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ 73 WoReg GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ 74 RoReg GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ 75 RwReg GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ 76 RoReg GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ 77 RwReg GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ 78 RwReg GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ 79 RwReg GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ 80 RoReg Reserved1[ 14 ]; 81 RwReg GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom [31:0] */ 82 RwReg GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top [63:32] */ 83 GmacSa GMAC_SA[ GMACSA_NUMBER ]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ 84 RwReg GMAC_TIDM[ 4 ]; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ 85 RwReg GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ 86 RwReg GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ 87 RwReg GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ 88 RwReg GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ 89 RwReg GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register */ 90 RwReg GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register */ 91 RoReg Reserved2[ 12 ]; 92 RoReg GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted [31:0] Register */ 93 RoReg GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted [47:32] Register */ 94 RoReg GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ 95 RoReg GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ 96 RoReg GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ 97 RoReg GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ 98 RoReg GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ 99 RoReg GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ 100 RoReg GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ 101 RoReg GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ 102 RoReg GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ 103 RoReg GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ 104 RoReg GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ 105 RoReg GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Under Runs Register */ 106 RoReg GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ 107 RoReg GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ 108 RoReg GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ 109 RoReg GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ 110 RoReg GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ 111 RoReg GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ 112 RoReg GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received [31:0] Received */ 113 RoReg GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received [47:32] Received */ 114 RoReg GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ 115 RoReg GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ 116 RoReg GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ 117 RoReg GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ 118 RoReg GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ 119 RoReg GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ 120 RoReg GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ 121 RoReg GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511Byte Frames Received Register */ 122 RoReg GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ 123 RoReg GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ 124 RoReg GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ 125 RoReg GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ 126 RoReg GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ 127 RoReg GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ 128 RoReg GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ 129 RoReg GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ 130 RoReg GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ 131 RoReg GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ 132 RoReg GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ 133 RoReg GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ 134 RoReg GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ 135 RoReg GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ 136 RoReg GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ 137 RoReg Reserved3[ 5 ]; 138 RwReg GMAC_TSSS; /**< \brief (Gmac Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register */ 139 RwReg GMAC_TSSN; /**< \brief (Gmac Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register */ 140 RwReg GMAC_TS; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Register */ 141 RwReg GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ 142 WoReg GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ 143 RwReg GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ 144 RoReg GMAC_EFTS; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds */ 145 RoReg GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds */ 146 RoReg GMAC_EFRS; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds */ 147 RoReg GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds */ 148 RoReg GMAC_PEFTS; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds */ 149 RoReg GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds */ 150 RoReg GMAC_PEFRS; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds */ 151 RoReg GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds */ 152 RoReg Reserved4[ 128 ]; 153 RoReg GMAC_ISRPQ[ 7 ]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue */ 154 RoReg Reserved5[ 9 ]; 155 RwReg GMAC_TBQBAPQ[ 7 ]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue */ 156 RoReg Reserved6[ 9 ]; 157 RwReg GMAC_RBQBAPQ[ 7 ]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Priority Queue */ 158 RoReg Reserved7[ 1 ]; 159 RwReg GMAC_RBSRPQ[ 7 ]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue */ 160 RoReg Reserved8[ 17 ]; 161 RwReg GMAC_ST1RPQ[ 16 ]; /**< \brief (Gmac Offset: 0x500) Screening Type1 Register Priority Queue */ 162 RwReg GMAC_ST2RPQ[ 16 ]; /**< \brief (Gmac Offset: 0x540) Screening Type2 Register Priority Queue */ 163 RoReg Reserved9[ 32 ]; 164 WoReg GMAC_IERPQ[ 7 ]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue */ 165 RoReg Reserved10[ 1 ]; 166 WoReg GMAC_IDRPQ[ 7 ]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue */ 167 RoReg Reserved11[ 1 ]; 168 RwReg GMAC_IMRPQ[ 7 ]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue */ 169 } Gmac; 170 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 171 /* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ 172 #define GMAC_NCR_LB ( 0x1u << 0 ) /**< \brief (GMAC_NCR) Loop Back */ 173 #define GMAC_NCR_LBL ( 0x1u << 1 ) /**< \brief (GMAC_NCR) Loop Back Local */ 174 #define GMAC_NCR_RXEN ( 0x1u << 2 ) /**< \brief (GMAC_NCR) Receive Enable */ 175 #define GMAC_NCR_TXEN ( 0x1u << 3 ) /**< \brief (GMAC_NCR) Transmit Enable */ 176 #define GMAC_NCR_MPE ( 0x1u << 4 ) /**< \brief (GMAC_NCR) Management Port Enable */ 177 #define GMAC_NCR_CLRSTAT ( 0x1u << 5 ) /**< \brief (GMAC_NCR) Clear Statistics Registers */ 178 #define GMAC_NCR_INCSTAT ( 0x1u << 6 ) /**< \brief (GMAC_NCR) Increment Statistics Registers */ 179 #define GMAC_NCR_WESTAT ( 0x1u << 7 ) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ 180 #define GMAC_NCR_BP ( 0x1u << 8 ) /**< \brief (GMAC_NCR) Back pressure */ 181 #define GMAC_NCR_TSTART ( 0x1u << 9 ) /**< \brief (GMAC_NCR) Start Transmission */ 182 #define GMAC_NCR_THALT ( 0x1u << 10 ) /**< \brief (GMAC_NCR) Transmit Halt */ 183 #define GMAC_NCR_TXPF ( 0x1u << 11 ) /**< \brief (GMAC_NCR) Transmit Pause Frame */ 184 #define GMAC_NCR_TXZQPF ( 0x1u << 12 ) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ 185 #define GMAC_NCR_RDS ( 0x1u << 14 ) /**< \brief (GMAC_NCR) Read Snapshot */ 186 #define GMAC_NCR_SRTSM ( 0x1u << 15 ) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ 187 #define GMAC_NCR_ENPBPR ( 0x1u << 16 ) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ 188 #define GMAC_NCR_TXPBPF ( 0x1u << 17 ) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ 189 #define GMAC_NCR_FNP ( 0x1u << 18 ) /**< \brief (GMAC_NCR) Flush Next Packet */ 190 /* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ 191 #define GMAC_NCFGR_SPD ( 0x1u << 0 ) /**< \brief (GMAC_NCFGR) Speed */ 192 #define GMAC_NCFGR_FD ( 0x1u << 1 ) /**< \brief (GMAC_NCFGR) Full Duplex */ 193 #define GMAC_NCFGR_DNVLAN ( 0x1u << 2 ) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ 194 #define GMAC_NCFGR_JFRAME ( 0x1u << 3 ) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ 195 #define GMAC_NCFGR_CAF ( 0x1u << 4 ) /**< \brief (GMAC_NCFGR) Copy All Frames */ 196 #define GMAC_NCFGR_NBC ( 0x1u << 5 ) /**< \brief (GMAC_NCFGR) No Broadcast */ 197 #define GMAC_NCFGR_MTIHEN ( 0x1u << 6 ) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ 198 #define GMAC_NCFGR_UNIHEN ( 0x1u << 7 ) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ 199 #define GMAC_NCFGR_MAXFS ( 0x1u << 8 ) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ 200 #define GMAC_NCFGR_GBE ( 0x1u << 10 ) /**< \brief (GMAC_NCFGR) Gigabit Mode Enable */ 201 #define GMAC_NCFGR_PIS ( 0x1u << 11 ) /**< \brief (GMAC_NCFGR) Physical Interface Select */ 202 #define GMAC_NCFGR_RTY ( 0x1u << 12 ) /**< \brief (GMAC_NCFGR) Retry Test */ 203 #define GMAC_NCFGR_PEN ( 0x1u << 13 ) /**< \brief (GMAC_NCFGR) Pause Enable */ 204 #define GMAC_NCFGR_RXBUFO_Pos 14 205 #define GMAC_NCFGR_RXBUFO_Msk ( 0x3u << GMAC_NCFGR_RXBUFO_Pos ) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ 206 #define GMAC_NCFGR_RXBUFO( value ) ( ( GMAC_NCFGR_RXBUFO_Msk & ( ( value ) << GMAC_NCFGR_RXBUFO_Pos ) ) ) 207 #define GMAC_NCFGR_LFERD ( 0x1u << 16 ) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ 208 #define GMAC_NCFGR_RFCS ( 0x1u << 17 ) /**< \brief (GMAC_NCFGR) Remove FCS */ 209 #define GMAC_NCFGR_CLK_Pos 18 210 #define GMAC_NCFGR_CLK_Msk ( 0x7u << GMAC_NCFGR_CLK_Pos ) /**< \brief (GMAC_NCFGR) MDC CLock Division */ 211 #define GMAC_NCFGR_CLK_MCK_8 ( 0x0u << 18 ) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ 212 #define GMAC_NCFGR_CLK_MCK_16 ( 0x1u << 18 ) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ 213 #define GMAC_NCFGR_CLK_MCK_32 ( 0x2u << 18 ) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ 214 #define GMAC_NCFGR_CLK_MCK_48 ( 0x3u << 18 ) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120MHz) */ 215 #define GMAC_NCFGR_CLK_MCK_64 ( 0x4u << 18 ) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ 216 #define GMAC_NCFGR_CLK_MCK_96 ( 0x5u << 18 ) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ 217 #define GMAC_NCFGR_CLK_MCK_128 ( 0x6u << 18 ) /**< \brief (GMAC_NCFGR) MCK divided by 128 (MCK up to 320 MHz) */ 218 #define GMAC_NCFGR_CLK_MCK_224 ( 0x7u << 18 ) /**< \brief (GMAC_NCFGR) MCK divided by 224 (MCK up to 540 MHz) */ 219 #define GMAC_NCFGR_DBW_Pos 21 220 #define GMAC_NCFGR_DBW_Msk ( 0x3u << GMAC_NCFGR_DBW_Pos ) /**< \brief (GMAC_NCFGR) Data Bus Width */ 221 #define GMAC_NCFGR_DBW_DBW32 ( 0x0u << 21 ) /**< \brief (GMAC_NCFGR) 32-bit data bus width */ 222 #define GMAC_NCFGR_DBW_DBW64 ( 0x1u << 21 ) /**< \brief (GMAC_NCFGR) 64-bit data bus width */ 223 #define GMAC_NCFGR_DCPF ( 0x1u << 23 ) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ 224 #define GMAC_NCFGR_RXCOEN ( 0x1u << 24 ) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ 225 #define GMAC_NCFGR_EFRHD ( 0x1u << 25 ) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ 226 #define GMAC_NCFGR_IRXFCS ( 0x1u << 26 ) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ 227 #define GMAC_NCFGR_IPGSEN ( 0x1u << 28 ) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ 228 #define GMAC_NCFGR_RXBP ( 0x1u << 29 ) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ 229 #define GMAC_NCFGR_IRXER ( 0x1u << 30 ) /**< \brief (GMAC_NCFGR) Ignore IPG rx_er */ 230 /* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ 231 #define GMAC_NSR_MDIO ( 0x1u << 1 ) /**< \brief (GMAC_NSR) MDIO Input Status */ 232 #define GMAC_NSR_IDLE ( 0x1u << 2 ) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ 233 /* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ 234 #define GMAC_UR_RGMII ( 0x1u << 0 ) /**< \brief (GMAC_UR) RGMII Mode */ 235 #define GMAC_UR_HDFC ( 0x1u << 6 ) /**< \brief (GMAC_UR) Half Duplex Flow Control */ 236 #define GMAC_UR_BPDG ( 0x1u << 7 ) /**< \brief (GMAC_UR) BPDG Bypass Deglitchers */ 237 /* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ 238 #define GMAC_DCFGR_FBLDO_Pos 0 239 #define GMAC_DCFGR_FBLDO_Msk ( 0x1fu << GMAC_DCFGR_FBLDO_Pos ) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ 240 #define GMAC_DCFGR_FBLDO_SINGLE ( 0x1u << 0 ) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ 241 #define GMAC_DCFGR_FBLDO_INCR4 ( 0x4u << 0 ) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ 242 #define GMAC_DCFGR_FBLDO_INCR8 ( 0x8u << 0 ) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ 243 #define GMAC_DCFGR_FBLDO_INCR16 ( 0x10u << 0 ) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ 244 #define GMAC_DCFGR_ESMA ( 0x1u << 6 ) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ 245 #define GMAC_DCFGR_ESPA ( 0x1u << 7 ) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ 246 #define GMAC_DCFGR_RXBMS_Pos 8 247 #define GMAC_DCFGR_RXBMS_Msk ( 0x3u << GMAC_DCFGR_RXBMS_Pos ) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ 248 #define GMAC_DCFGR_RXBMS_EIGHTH ( 0x0u << 8 ) /**< \brief (GMAC_DCFGR) 1 Kbyte Memory Size */ 249 #define GMAC_DCFGR_RXBMS_QUARTER ( 0x1u << 8 ) /**< \brief (GMAC_DCFGR) 2 Kbytes Memory Size */ 250 #define GMAC_DCFGR_RXBMS_HALF ( 0x2u << 8 ) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ 251 #define GMAC_DCFGR_RXBMS_FULL ( 0x3u << 8 ) /**< \brief (GMAC_DCFGR) 8 Kbytes Memory Size */ 252 #define GMAC_DCFGR_TXPBMS ( 0x1u << 10 ) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ 253 #define GMAC_DCFGR_TXCOEN ( 0x1u << 11 ) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ 254 #define GMAC_DCFGR_DRBS_Pos 16 255 #define GMAC_DCFGR_DRBS_Msk ( 0xffu << GMAC_DCFGR_DRBS_Pos ) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ 256 #define GMAC_DCFGR_DRBS( value ) ( ( GMAC_DCFGR_DRBS_Msk & ( ( value ) << GMAC_DCFGR_DRBS_Pos ) ) ) 257 #define GMAC_DCFGR_DDRP ( 0x1u << 24 ) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ 258 /* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ 259 #define GMAC_TSR_UBR ( 0x1u << 0 ) /**< \brief (GMAC_TSR) Used Bit Read */ 260 #define GMAC_TSR_COL ( 0x1u << 1 ) /**< \brief (GMAC_TSR) Collision Occurred */ 261 #define GMAC_TSR_RLE ( 0x1u << 2 ) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ 262 #define GMAC_TSR_TXGO ( 0x1u << 3 ) /**< \brief (GMAC_TSR) Transmit Go */ 263 #define GMAC_TSR_TFC ( 0x1u << 4 ) /**< \brief (GMAC_TSR) Transmit Frame Corruption due to AHB error */ 264 #define GMAC_TSR_TXCOMP ( 0x1u << 5 ) /**< \brief (GMAC_TSR) Transmit Complete */ 265 #define GMAC_TSR_UND ( 0x1u << 6 ) /**< \brief (GMAC_TSR) Transmit Under Run */ 266 #define GMAC_TSR_LCO ( 0x1u << 7 ) /**< \brief (GMAC_TSR) Late Collision Occurred */ 267 #define GMAC_TSR_HRESP ( 0x1u << 8 ) /**< \brief (GMAC_TSR) HRESP Not OK */ 268 /* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address -------- */ 269 #define GMAC_RBQB_ADDR_Pos 2 270 #define GMAC_RBQB_ADDR_Msk ( 0x3fffffffu << GMAC_RBQB_ADDR_Pos ) /**< \brief (GMAC_RBQB) Receive buffer queue base address */ 271 #define GMAC_RBQB_ADDR( value ) ( ( GMAC_RBQB_ADDR_Msk & ( ( value ) << GMAC_RBQB_ADDR_Pos ) ) ) 272 /* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address -------- */ 273 #define GMAC_TBQB_ADDR_Pos 2 274 #define GMAC_TBQB_ADDR_Msk ( 0x3fffffffu << GMAC_TBQB_ADDR_Pos ) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ 275 #define GMAC_TBQB_ADDR( value ) ( ( GMAC_TBQB_ADDR_Msk & ( ( value ) << GMAC_TBQB_ADDR_Pos ) ) ) 276 /* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ 277 #define GMAC_RSR_BNA ( 0x1u << 0 ) /**< \brief (GMAC_RSR) Buffer Not Available */ 278 #define GMAC_RSR_REC ( 0x1u << 1 ) /**< \brief (GMAC_RSR) Frame Received */ 279 #define GMAC_RSR_RXOVR ( 0x1u << 2 ) /**< \brief (GMAC_RSR) Receive Overrun */ 280 #define GMAC_RSR_HNO ( 0x1u << 3 ) /**< \brief (GMAC_RSR) HRESP Not OK */ 281 /* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ 282 #define GMAC_ISR_MFS ( 0x1u << 0 ) /**< \brief (GMAC_ISR) Management Frame Sent */ 283 #define GMAC_ISR_RCOMP ( 0x1u << 1 ) /**< \brief (GMAC_ISR) Receive Complete */ 284 #define GMAC_ISR_RXUBR ( 0x1u << 2 ) /**< \brief (GMAC_ISR) RX Used Bit Read */ 285 #define GMAC_ISR_TXUBR ( 0x1u << 3 ) /**< \brief (GMAC_ISR) TX Used Bit Read */ 286 #define GMAC_ISR_TUR ( 0x1u << 4 ) /**< \brief (GMAC_ISR) Transmit Under Run */ 287 #define GMAC_ISR_RLEX ( 0x1u << 5 ) /**< \brief (GMAC_ISR) Retry Limit Exceeded or Late Collision */ 288 #define GMAC_ISR_TFC ( 0x1u << 6 ) /**< \brief (GMAC_ISR) Transmit Frame Corruption due to AHB error */ 289 #define GMAC_ISR_TCOMP ( 0x1u << 7 ) /**< \brief (GMAC_ISR) Transmit Complete */ 290 #define GMAC_ISR_ROVR ( 0x1u << 10 ) /**< \brief (GMAC_ISR) Receive Overrun */ 291 #define GMAC_ISR_HRESP ( 0x1u << 11 ) /**< \brief (GMAC_ISR) HRESP Not OK */ 292 #define GMAC_ISR_PFNZ ( 0x1u << 12 ) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ 293 #define GMAC_ISR_PTZ ( 0x1u << 13 ) /**< \brief (GMAC_ISR) Pause Time Zero */ 294 #define GMAC_ISR_PFTR ( 0x1u << 14 ) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ 295 #define GMAC_ISR_EXINT ( 0x1u << 15 ) /**< \brief (GMAC_ISR) External Interrupt */ 296 #define GMAC_ISR_DRQFR ( 0x1u << 18 ) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ 297 #define GMAC_ISR_SFR ( 0x1u << 19 ) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ 298 #define GMAC_ISR_DRQFT ( 0x1u << 20 ) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ 299 #define GMAC_ISR_SFT ( 0x1u << 21 ) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ 300 #define GMAC_ISR_PDRQFR ( 0x1u << 22 ) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ 301 #define GMAC_ISR_PDRSFR ( 0x1u << 23 ) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ 302 #define GMAC_ISR_PDRQFT ( 0x1u << 24 ) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ 303 #define GMAC_ISR_PDRSFT ( 0x1u << 25 ) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ 304 #define GMAC_ISR_SRI ( 0x1u << 26 ) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ 305 #define GMAC_ISR_WOL ( 0x1u << 28 ) /**< \brief (GMAC_ISR) Wake On LAN */ 306 /* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ 307 #define GMAC_IER_MFS ( 0x1u << 0 ) /**< \brief (GMAC_IER) Management Frame Sent */ 308 #define GMAC_IER_RCOMP ( 0x1u << 1 ) /**< \brief (GMAC_IER) Receive Complete */ 309 #define GMAC_IER_RXUBR ( 0x1u << 2 ) /**< \brief (GMAC_IER) RX Used Bit Read */ 310 #define GMAC_IER_TXUBR ( 0x1u << 3 ) /**< \brief (GMAC_IER) TX Used Bit Read */ 311 #define GMAC_IER_TUR ( 0x1u << 4 ) /**< \brief (GMAC_IER) Transmit Under Run */ 312 #define GMAC_IER_RLEX ( 0x1u << 5 ) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ 313 #define GMAC_IER_TFC ( 0x1u << 6 ) /**< \brief (GMAC_IER) Transmit Frame Corruption due to AHB error */ 314 #define GMAC_IER_TCOMP ( 0x1u << 7 ) /**< \brief (GMAC_IER) Transmit Complete */ 315 #define GMAC_IER_ROVR ( 0x1u << 10 ) /**< \brief (GMAC_IER) Receive Overrun */ 316 #define GMAC_IER_HRESP ( 0x1u << 11 ) /**< \brief (GMAC_IER) HRESP Not OK */ 317 #define GMAC_IER_PFNZ ( 0x1u << 12 ) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ 318 #define GMAC_IER_PTZ ( 0x1u << 13 ) /**< \brief (GMAC_IER) Pause Time Zero */ 319 #define GMAC_IER_PFTR ( 0x1u << 14 ) /**< \brief (GMAC_IER) Pause Frame Transmitted */ 320 #define GMAC_IER_EXINT ( 0x1u << 15 ) /**< \brief (GMAC_IER) External Interrupt */ 321 #define GMAC_IER_DRQFR ( 0x1u << 18 ) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ 322 #define GMAC_IER_SFR ( 0x1u << 19 ) /**< \brief (GMAC_IER) PTP Sync Frame Received */ 323 #define GMAC_IER_DRQFT ( 0x1u << 20 ) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ 324 #define GMAC_IER_SFT ( 0x1u << 21 ) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ 325 #define GMAC_IER_PDRQFR ( 0x1u << 22 ) /**< \brief (GMAC_IER) PDelay Request Frame Received */ 326 #define GMAC_IER_PDRSFR ( 0x1u << 23 ) /**< \brief (GMAC_IER) PDelay Response Frame Received */ 327 #define GMAC_IER_PDRQFT ( 0x1u << 24 ) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ 328 #define GMAC_IER_PDRSFT ( 0x1u << 25 ) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ 329 #define GMAC_IER_SRI ( 0x1u << 26 ) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ 330 #define GMAC_IER_WOL ( 0x1u << 28 ) /**< \brief (GMAC_IER) Wake On LAN */ 331 /* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ 332 #define GMAC_IDR_MFS ( 0x1u << 0 ) /**< \brief (GMAC_IDR) Management Frame Sent */ 333 #define GMAC_IDR_RCOMP ( 0x1u << 1 ) /**< \brief (GMAC_IDR) Receive Complete */ 334 #define GMAC_IDR_RXUBR ( 0x1u << 2 ) /**< \brief (GMAC_IDR) RX Used Bit Read */ 335 #define GMAC_IDR_TXUBR ( 0x1u << 3 ) /**< \brief (GMAC_IDR) TX Used Bit Read */ 336 #define GMAC_IDR_TUR ( 0x1u << 4 ) /**< \brief (GMAC_IDR) Transmit Under Run */ 337 #define GMAC_IDR_RLEX ( 0x1u << 5 ) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ 338 #define GMAC_IDR_TFC ( 0x1u << 6 ) /**< \brief (GMAC_IDR) Transmit Frame Corruption due to AHB error */ 339 #define GMAC_IDR_TCOMP ( 0x1u << 7 ) /**< \brief (GMAC_IDR) Transmit Complete */ 340 #define GMAC_IDR_ROVR ( 0x1u << 10 ) /**< \brief (GMAC_IDR) Receive Overrun */ 341 #define GMAC_IDR_HRESP ( 0x1u << 11 ) /**< \brief (GMAC_IDR) HRESP Not OK */ 342 #define GMAC_IDR_PFNZ ( 0x1u << 12 ) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ 343 #define GMAC_IDR_PTZ ( 0x1u << 13 ) /**< \brief (GMAC_IDR) Pause Time Zero */ 344 #define GMAC_IDR_PFTR ( 0x1u << 14 ) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ 345 #define GMAC_IDR_EXINT ( 0x1u << 15 ) /**< \brief (GMAC_IDR) External Interrupt */ 346 #define GMAC_IDR_DRQFR ( 0x1u << 18 ) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ 347 #define GMAC_IDR_SFR ( 0x1u << 19 ) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ 348 #define GMAC_IDR_DRQFT ( 0x1u << 20 ) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ 349 #define GMAC_IDR_SFT ( 0x1u << 21 ) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ 350 #define GMAC_IDR_PDRQFR ( 0x1u << 22 ) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ 351 #define GMAC_IDR_PDRSFR ( 0x1u << 23 ) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ 352 #define GMAC_IDR_PDRQFT ( 0x1u << 24 ) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ 353 #define GMAC_IDR_PDRSFT ( 0x1u << 25 ) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ 354 #define GMAC_IDR_SRI ( 0x1u << 26 ) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ 355 #define GMAC_IDR_WOL ( 0x1u << 28 ) /**< \brief (GMAC_IDR) Wake On LAN */ 356 /* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ 357 #define GMAC_IMR_MFS ( 0x1u << 0 ) /**< \brief (GMAC_IMR) Management Frame Sent */ 358 #define GMAC_IMR_RCOMP ( 0x1u << 1 ) /**< \brief (GMAC_IMR) Receive Complete */ 359 #define GMAC_IMR_RXUBR ( 0x1u << 2 ) /**< \brief (GMAC_IMR) RX Used Bit Read */ 360 #define GMAC_IMR_TXUBR ( 0x1u << 3 ) /**< \brief (GMAC_IMR) TX Used Bit Read */ 361 #define GMAC_IMR_TUR ( 0x1u << 4 ) /**< \brief (GMAC_IMR) Transmit Under Run */ 362 #define GMAC_IMR_RLEX ( 0x1u << 5 ) /**< \brief (GMAC_IMR) Retry Limit Exceeded or Late Collision */ 363 #define GMAC_IMR_TFC ( 0x1u << 6 ) /**< \brief (GMAC_IMR) Transmit Frame Corruption due to AHB error */ 364 #define GMAC_IMR_TCOMP ( 0x1u << 7 ) /**< \brief (GMAC_IMR) Transmit Complete */ 365 #define GMAC_IMR_ROVR ( 0x1u << 10 ) /**< \brief (GMAC_IMR) Receive Overrun */ 366 #define GMAC_IMR_HRESP ( 0x1u << 11 ) /**< \brief (GMAC_IMR) HRESP Not OK */ 367 #define GMAC_IMR_PFNZ ( 0x1u << 12 ) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ 368 #define GMAC_IMR_PTZ ( 0x1u << 13 ) /**< \brief (GMAC_IMR) Pause Time Zero */ 369 #define GMAC_IMR_PFTR ( 0x1u << 14 ) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ 370 #define GMAC_IMR_EXINT ( 0x1u << 15 ) /**< \brief (GMAC_IMR) External Interrupt */ 371 #define GMAC_IMR_DRQFR ( 0x1u << 18 ) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ 372 #define GMAC_IMR_SFR ( 0x1u << 19 ) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ 373 #define GMAC_IMR_DRQFT ( 0x1u << 20 ) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ 374 #define GMAC_IMR_SFT ( 0x1u << 21 ) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ 375 #define GMAC_IMR_PDRQFR ( 0x1u << 22 ) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ 376 #define GMAC_IMR_PDRSFR ( 0x1u << 23 ) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ 377 #define GMAC_IMR_PDRQFT ( 0x1u << 24 ) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ 378 #define GMAC_IMR_PDRSFT ( 0x1u << 25 ) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ 379 /* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ 380 #define GMAC_MAN_DATA_Pos 0 381 #define GMAC_MAN_DATA_Msk ( 0xffffu << GMAC_MAN_DATA_Pos ) /**< \brief (GMAC_MAN) PHY Data */ 382 #define GMAC_MAN_DATA( value ) ( ( GMAC_MAN_DATA_Msk & ( ( value ) << GMAC_MAN_DATA_Pos ) ) ) 383 #define GMAC_MAN_WTN_Pos 16 384 #define GMAC_MAN_WTN_Msk ( 0x3u << GMAC_MAN_WTN_Pos ) /**< \brief (GMAC_MAN) Write Ten */ 385 #define GMAC_MAN_WTN( value ) ( ( GMAC_MAN_WTN_Msk & ( ( value ) << GMAC_MAN_WTN_Pos ) ) ) 386 #define GMAC_MAN_REGA_Pos 18 387 #define GMAC_MAN_REGA_Msk ( 0x1fu << GMAC_MAN_REGA_Pos ) /**< \brief (GMAC_MAN) Register Address */ 388 #define GMAC_MAN_REGA( value ) ( ( GMAC_MAN_REGA_Msk & ( ( value ) << GMAC_MAN_REGA_Pos ) ) ) 389 #define GMAC_MAN_PHYA_Pos 23 390 #define GMAC_MAN_PHYA_Msk ( 0x1fu << GMAC_MAN_PHYA_Pos ) /**< \brief (GMAC_MAN) PHY Address */ 391 #define GMAC_MAN_PHYA( value ) ( ( GMAC_MAN_PHYA_Msk & ( ( value ) << GMAC_MAN_PHYA_Pos ) ) ) 392 #define GMAC_MAN_OP_Pos 28 393 #define GMAC_MAN_OP_Msk ( 0x3u << GMAC_MAN_OP_Pos ) /**< \brief (GMAC_MAN) Operation */ 394 #define GMAC_MAN_OP( value ) ( ( GMAC_MAN_OP_Msk & ( ( value ) << GMAC_MAN_OP_Pos ) ) ) 395 #define GMAC_MAN_CLTTO ( 0x1u << 30 ) /**< \brief (GMAC_MAN) Clause 22 Operation */ 396 #define GMAC_MAN_WZO ( 0x1u << 31 ) /**< \brief (GMAC_MAN) Write ZERO */ 397 /* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ 398 #define GMAC_RPQ_RPQ_Pos 0 399 #define GMAC_RPQ_RPQ_Msk ( 0xffffu << GMAC_RPQ_RPQ_Pos ) /**< \brief (GMAC_RPQ) Received Pause Quantum */ 400 /* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ 401 #define GMAC_TPQ_TPQ_Pos 0 402 #define GMAC_TPQ_TPQ_Msk ( 0xffffu << GMAC_TPQ_TPQ_Pos ) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ 403 #define GMAC_TPQ_TPQ( value ) ( ( GMAC_TPQ_TPQ_Msk & ( ( value ) << GMAC_TPQ_TPQ_Pos ) ) ) 404 /* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ 405 #define GMAC_TPSF_TPB1ADR_Pos 0 406 #define GMAC_TPSF_TPB1ADR_Msk ( 0xfffu << GMAC_TPSF_TPB1ADR_Pos ) /**< \brief (GMAC_TPSF) tx_pbuf_addr-1:0 */ 407 #define GMAC_TPSF_TPB1ADR( value ) ( ( GMAC_TPSF_TPB1ADR_Msk & ( ( value ) << GMAC_TPSF_TPB1ADR_Pos ) ) ) 408 #define GMAC_TPSF_ENTXP ( 0x1u << 31 ) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ 409 /* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ 410 #define GMAC_RPSF_RPB1ADR_Pos 0 411 #define GMAC_RPSF_RPB1ADR_Msk ( 0xfffu << GMAC_RPSF_RPB1ADR_Pos ) /**< \brief (GMAC_RPSF) rx_pbuf_addr-1:0 */ 412 #define GMAC_RPSF_RPB1ADR( value ) ( ( GMAC_RPSF_RPB1ADR_Msk & ( ( value ) << GMAC_RPSF_RPB1ADR_Pos ) ) ) 413 #define GMAC_RPSF_ENRXP ( 0x1u << 31 ) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ 414 /* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom [31:0] -------- */ 415 #define GMAC_HRB_ADDR_Pos 0 416 #define GMAC_HRB_ADDR_Msk ( 0xffffffffu << GMAC_HRB_ADDR_Pos ) /**< \brief (GMAC_HRB) Hash Address */ 417 #define GMAC_HRB_ADDR( value ) ( ( GMAC_HRB_ADDR_Msk & ( ( value ) << GMAC_HRB_ADDR_Pos ) ) ) 418 /* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top [63:32] -------- */ 419 #define GMAC_HRT_ADDR_Pos 0 420 #define GMAC_HRT_ADDR_Msk ( 0xffffffffu << GMAC_HRT_ADDR_Pos ) /**< \brief (GMAC_HRT) Hash Address */ 421 #define GMAC_HRT_ADDR( value ) ( ( GMAC_HRT_ADDR_Msk & ( ( value ) << GMAC_HRT_ADDR_Pos ) ) ) 422 /* -------- GMAC_SAB1 : (GMAC Offset: 0x088) Specific Address 1 Bottom [31:0] Register -------- */ 423 #define GMAC_SAB1_ADDR_Pos 0 424 #define GMAC_SAB1_ADDR_Msk ( 0xffffffffu << GMAC_SAB1_ADDR_Pos ) /**< \brief (GMAC_SAB1) Specific Address 1 */ 425 #define GMAC_SAB1_ADDR( value ) ( ( GMAC_SAB1_ADDR_Msk & ( ( value ) << GMAC_SAB1_ADDR_Pos ) ) ) 426 /* -------- GMAC_SAT1 : (GMAC Offset: 0x08C) Specific Address 1 Top [47:32] Register -------- */ 427 #define GMAC_SAT1_ADDR_Pos 0 428 #define GMAC_SAT1_ADDR_Msk ( 0xffffu << GMAC_SAT1_ADDR_Pos ) /**< \brief (GMAC_SAT1) Specific Address 1 */ 429 #define GMAC_SAT1_ADDR( value ) ( ( GMAC_SAT1_ADDR_Msk & ( ( value ) << GMAC_SAT1_ADDR_Pos ) ) ) 430 /* -------- GMAC_SAB2 : (GMAC Offset: 0x090) Specific Address 2 Bottom [31:0] Register -------- */ 431 #define GMAC_SAB2_ADDR_Pos 0 432 #define GMAC_SAB2_ADDR_Msk ( 0xffffffffu << GMAC_SAB2_ADDR_Pos ) /**< \brief (GMAC_SAB2) Specific Address 2 */ 433 #define GMAC_SAB2_ADDR( value ) ( ( GMAC_SAB2_ADDR_Msk & ( ( value ) << GMAC_SAB2_ADDR_Pos ) ) ) 434 /* -------- GMAC_SAT2 : (GMAC Offset: 0x094) Specific Address 2 Top [47:32] Register -------- */ 435 #define GMAC_SAT2_ADDR_Pos 0 436 #define GMAC_SAT2_ADDR_Msk ( 0xffffu << GMAC_SAT2_ADDR_Pos ) /**< \brief (GMAC_SAT2) Specific Address 2 */ 437 #define GMAC_SAT2_ADDR( value ) ( ( GMAC_SAT2_ADDR_Msk & ( ( value ) << GMAC_SAT2_ADDR_Pos ) ) ) 438 /* -------- GMAC_SAB3 : (GMAC Offset: 0x098) Specific Address 3 Bottom [31:0] Register -------- */ 439 #define GMAC_SAB3_ADDR_Pos 0 440 #define GMAC_SAB3_ADDR_Msk ( 0xffffffffu << GMAC_SAB3_ADDR_Pos ) /**< \brief (GMAC_SAB3) Specific Address 3 */ 441 #define GMAC_SAB3_ADDR( value ) ( ( GMAC_SAB3_ADDR_Msk & ( ( value ) << GMAC_SAB3_ADDR_Pos ) ) ) 442 /* -------- GMAC_SAT3 : (GMAC Offset: 0x09C) Specific Address 3 Top [47:32] Register -------- */ 443 #define GMAC_SAT3_ADDR_Pos 0 444 #define GMAC_SAT3_ADDR_Msk ( 0xffffu << GMAC_SAT3_ADDR_Pos ) /**< \brief (GMAC_SAT3) Specific Address 3 */ 445 #define GMAC_SAT3_ADDR( value ) ( ( GMAC_SAT3_ADDR_Msk & ( ( value ) << GMAC_SAT3_ADDR_Pos ) ) ) 446 /* -------- GMAC_SAB4 : (GMAC Offset: 0x0A0) Specific Address 4 Bottom [31:0] Register -------- */ 447 #define GMAC_SAB4_ADDR_Pos 0 448 #define GMAC_SAB4_ADDR_Msk ( 0xffffffffu << GMAC_SAB4_ADDR_Pos ) /**< \brief (GMAC_SAB4) Specific Address 4 */ 449 #define GMAC_SAB4_ADDR( value ) ( ( GMAC_SAB4_ADDR_Msk & ( ( value ) << GMAC_SAB4_ADDR_Pos ) ) ) 450 /* -------- GMAC_SAT4 : (GMAC Offset: 0x0A4) Specific Address 4 Top [47:32] Register -------- */ 451 #define GMAC_SAT4_ADDR_Pos 0 452 #define GMAC_SAT4_ADDR_Msk ( 0xffffu << GMAC_SAT4_ADDR_Pos ) /**< \brief (GMAC_SAT4) Specific Address 4 */ 453 #define GMAC_SAT4_ADDR( value ) ( ( GMAC_SAT4_ADDR_Msk & ( ( value ) << GMAC_SAT4_ADDR_Pos ) ) ) 454 /* -------- GMAC_TIDM[4] : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ 455 #define GMAC_TIDM_TID_Pos 0 456 #define GMAC_TIDM_TID_Msk ( 0xffffu << GMAC_TIDM_TID_Pos ) /**< \brief (GMAC_TIDM[4]) Type ID Match 1 */ 457 #define GMAC_TIDM_TID( value ) ( ( GMAC_TIDM_TID_Msk & ( ( value ) << GMAC_TIDM_TID_Pos ) ) ) 458 /* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ 459 #define GMAC_WOL_IP_Pos 0 460 #define GMAC_WOL_IP_Msk ( 0xffffu << GMAC_WOL_IP_Pos ) /**< \brief (GMAC_WOL) ARP Request IP Address */ 461 #define GMAC_WOL_IP( value ) ( ( GMAC_WOL_IP_Msk & ( ( value ) << GMAC_WOL_IP_Pos ) ) ) 462 #define GMAC_WOL_MAG ( 0x1u << 16 ) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ 463 #define GMAC_WOL_ARP ( 0x1u << 17 ) /**< \brief (GMAC_WOL) ARP Request IP Address */ 464 #define GMAC_WOL_SA1 ( 0x1u << 18 ) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ 465 #define GMAC_WOL_MTI ( 0x1u << 19 ) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ 466 /* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ 467 #define GMAC_IPGS_FL_Pos 0 468 #define GMAC_IPGS_FL_Msk ( 0xffffu << GMAC_IPGS_FL_Pos ) /**< \brief (GMAC_IPGS) Frame Length */ 469 #define GMAC_IPGS_FL( value ) ( ( GMAC_IPGS_FL_Msk & ( ( value ) << GMAC_IPGS_FL_Pos ) ) ) 470 /* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ 471 #define GMAC_SVLAN_VLAN_TYPE_Pos 0 472 #define GMAC_SVLAN_VLAN_TYPE_Msk ( 0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos ) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ 473 #define GMAC_SVLAN_VLAN_TYPE( value ) ( ( GMAC_SVLAN_VLAN_TYPE_Msk & ( ( value ) << GMAC_SVLAN_VLAN_TYPE_Pos ) ) ) 474 #define GMAC_SVLAN_ESVLAN ( 0x1u << 31 ) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ 475 /* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ 476 #define GMAC_TPFCP_PEV_Pos 0 477 #define GMAC_TPFCP_PEV_Msk ( 0xffu << GMAC_TPFCP_PEV_Pos ) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ 478 #define GMAC_TPFCP_PEV( value ) ( ( GMAC_TPFCP_PEV_Msk & ( ( value ) << GMAC_TPFCP_PEV_Pos ) ) ) 479 #define GMAC_TPFCP_PQ_Pos 8 480 #define GMAC_TPFCP_PQ_Msk ( 0xffu << GMAC_TPFCP_PQ_Pos ) /**< \brief (GMAC_TPFCP) Pause Quantum */ 481 #define GMAC_TPFCP_PQ( value ) ( ( GMAC_TPFCP_PQ_Msk & ( ( value ) << GMAC_TPFCP_PQ_Pos ) ) ) 482 /* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register -------- */ 483 #define GMAC_SAMB1_ADDR_Pos 0 484 #define GMAC_SAMB1_ADDR_Msk ( 0xffffffffu << GMAC_SAMB1_ADDR_Pos ) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ 485 #define GMAC_SAMB1_ADDR( value ) ( ( GMAC_SAMB1_ADDR_Msk & ( ( value ) << GMAC_SAMB1_ADDR_Pos ) ) ) 486 /* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register -------- */ 487 #define GMAC_SAMT1_ADDR_Pos 0 488 #define GMAC_SAMT1_ADDR_Msk ( 0xffffu << GMAC_SAMT1_ADDR_Pos ) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ 489 #define GMAC_SAMT1_ADDR( value ) ( ( GMAC_SAMT1_ADDR_Msk & ( ( value ) << GMAC_SAMT1_ADDR_Pos ) ) ) 490 /* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted [31:0] Register -------- */ 491 #define GMAC_OTLO_TXO_Pos 0 492 #define GMAC_OTLO_TXO_Msk ( 0xffffffffu << GMAC_OTLO_TXO_Pos ) /**< \brief (GMAC_OTLO) Transmitted Octets */ 493 /* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted [47:32] Register -------- */ 494 #define GMAC_OTHI_TXO_Pos 0 495 #define GMAC_OTHI_TXO_Msk ( 0xffffu << GMAC_OTHI_TXO_Pos ) /**< \brief (GMAC_OTHI) Transmitted Octets */ 496 /* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ 497 #define GMAC_FT_FTX_Pos 0 498 #define GMAC_FT_FTX_Msk ( 0xffffffffu << GMAC_FT_FTX_Pos ) /**< \brief (GMAC_FT) Frames Transmitted without Error */ 499 /* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ 500 #define GMAC_BCFT_BFTX_Pos 0 501 #define GMAC_BCFT_BFTX_Msk ( 0xffffffffu << GMAC_BCFT_BFTX_Pos ) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ 502 /* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ 503 #define GMAC_MFT_MFTX_Pos 0 504 #define GMAC_MFT_MFTX_Msk ( 0xffffffffu << GMAC_MFT_MFTX_Pos ) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ 505 /* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ 506 #define GMAC_PFT_PFTX_Pos 0 507 #define GMAC_PFT_PFTX_Msk ( 0xffffu << GMAC_PFT_PFTX_Pos ) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ 508 /* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ 509 #define GMAC_BFT64_NFTX_Pos 0 510 #define GMAC_BFT64_NFTX_Msk ( 0xffffffffu << GMAC_BFT64_NFTX_Pos ) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ 511 /* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ 512 #define GMAC_TBFT127_NFTX_Pos 0 513 #define GMAC_TBFT127_NFTX_Msk ( 0xffffffffu << GMAC_TBFT127_NFTX_Pos ) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ 514 /* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ 515 #define GMAC_TBFT255_NFTX_Pos 0 516 #define GMAC_TBFT255_NFTX_Msk ( 0xffffffffu << GMAC_TBFT255_NFTX_Pos ) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ 517 /* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ 518 #define GMAC_TBFT511_NFTX_Pos 0 519 #define GMAC_TBFT511_NFTX_Msk ( 0xffffffffu << GMAC_TBFT511_NFTX_Pos ) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ 520 /* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ 521 #define GMAC_TBFT1023_NFTX_Pos 0 522 #define GMAC_TBFT1023_NFTX_Msk ( 0xffffffffu << GMAC_TBFT1023_NFTX_Pos ) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ 523 /* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ 524 #define GMAC_TBFT1518_NFTX_Pos 0 525 #define GMAC_TBFT1518_NFTX_Msk ( 0xffffffffu << GMAC_TBFT1518_NFTX_Pos ) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ 526 /* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ 527 #define GMAC_GTBFT1518_NFTX_Pos 0 528 #define GMAC_GTBFT1518_NFTX_Msk ( 0xffffffffu << GMAC_GTBFT1518_NFTX_Pos ) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ 529 /* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Under Runs Register -------- */ 530 #define GMAC_TUR_TXUNR_Pos 0 531 #define GMAC_TUR_TXUNR_Msk ( 0x3ffu << GMAC_TUR_TXUNR_Pos ) /**< \brief (GMAC_TUR) Transmit Under Runs */ 532 /* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ 533 #define GMAC_SCF_SCOL_Pos 0 534 #define GMAC_SCF_SCOL_Msk ( 0x3ffffu << GMAC_SCF_SCOL_Pos ) /**< \brief (GMAC_SCF) Single Collision */ 535 /* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ 536 #define GMAC_MCF_MCOL_Pos 0 537 #define GMAC_MCF_MCOL_Msk ( 0x3ffffu << GMAC_MCF_MCOL_Pos ) /**< \brief (GMAC_MCF) Multiple Collision */ 538 /* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ 539 #define GMAC_EC_XCOL_Pos 0 540 #define GMAC_EC_XCOL_Msk ( 0x3ffu << GMAC_EC_XCOL_Pos ) /**< \brief (GMAC_EC) Excessive Collisions */ 541 /* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ 542 #define GMAC_LC_LCOL_Pos 0 543 #define GMAC_LC_LCOL_Msk ( 0x3ffu << GMAC_LC_LCOL_Pos ) /**< \brief (GMAC_LC) Late Collisions */ 544 /* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ 545 #define GMAC_DTF_DEFT_Pos 0 546 #define GMAC_DTF_DEFT_Msk ( 0x3ffffu << GMAC_DTF_DEFT_Pos ) /**< \brief (GMAC_DTF) Deferred Transmission */ 547 /* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ 548 #define GMAC_CSE_CSR_Pos 0 549 #define GMAC_CSE_CSR_Msk ( 0x3ffu << GMAC_CSE_CSR_Pos ) /**< \brief (GMAC_CSE) Carrier Sense Error */ 550 /* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received [31:0] Received -------- */ 551 #define GMAC_ORLO_RXO_Pos 0 552 #define GMAC_ORLO_RXO_Msk ( 0xffffffffu << GMAC_ORLO_RXO_Pos ) /**< \brief (GMAC_ORLO) Received Octets */ 553 /* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received [47:32] Received -------- */ 554 #define GMAC_ORHI_RXO_Pos 0 555 #define GMAC_ORHI_RXO_Msk ( 0xffffu << GMAC_ORHI_RXO_Pos ) /**< \brief (GMAC_ORHI) Received Octets */ 556 /* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ 557 #define GMAC_FR_FRX_Pos 0 558 #define GMAC_FR_FRX_Msk ( 0xffffffffu << GMAC_FR_FRX_Pos ) /**< \brief (GMAC_FR) Frames Received without Error */ 559 /* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ 560 #define GMAC_BCFR_BFRX_Pos 0 561 #define GMAC_BCFR_BFRX_Msk ( 0xffffffffu << GMAC_BCFR_BFRX_Pos ) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ 562 /* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ 563 #define GMAC_MFR_MFRX_Pos 0 564 #define GMAC_MFR_MFRX_Msk ( 0xffffffffu << GMAC_MFR_MFRX_Pos ) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ 565 /* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ 566 #define GMAC_PFR_PFRX_Pos 0 567 #define GMAC_PFR_PFRX_Msk ( 0xffffu << GMAC_PFR_PFRX_Pos ) /**< \brief (GMAC_PFR) Pause Frames Received Register */ 568 /* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ 569 #define GMAC_BFR64_NFRX_Pos 0 570 #define GMAC_BFR64_NFRX_Msk ( 0xffffffffu << GMAC_BFR64_NFRX_Pos ) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ 571 /* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ 572 #define GMAC_TBFR127_NFRX_Pos 0 573 #define GMAC_TBFR127_NFRX_Msk ( 0xffffffffu << GMAC_TBFR127_NFRX_Pos ) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ 574 /* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ 575 #define GMAC_TBFR255_NFRX_Pos 0 576 #define GMAC_TBFR255_NFRX_Msk ( 0xffffffffu << GMAC_TBFR255_NFRX_Pos ) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ 577 /* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511Byte Frames Received Register -------- */ 578 #define GMAC_TBFR511_NFRX_Pos 0 579 #define GMAC_TBFR511_NFRX_Msk ( 0xffffffffu << GMAC_TBFR511_NFRX_Pos ) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ 580 /* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ 581 #define GMAC_TBFR1023_NFRX_Pos 0 582 #define GMAC_TBFR1023_NFRX_Msk ( 0xffffffffu << GMAC_TBFR1023_NFRX_Pos ) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ 583 /* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ 584 #define GMAC_TBFR1518_NFRX_Pos 0 585 #define GMAC_TBFR1518_NFRX_Msk ( 0xffffffffu << GMAC_TBFR1518_NFRX_Pos ) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ 586 /* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ 587 #define GMAC_TMXBFR_NFRX_Pos 0 588 #define GMAC_TMXBFR_NFRX_Msk ( 0xffffffffu << GMAC_TMXBFR_NFRX_Pos ) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ 589 /* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ 590 #define GMAC_UFR_UFRX_Pos 0 591 #define GMAC_UFR_UFRX_Msk ( 0x3ffu << GMAC_UFR_UFRX_Pos ) /**< \brief (GMAC_UFR) Undersize Frames Received */ 592 /* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ 593 #define GMAC_OFR_OFRX_Pos 0 594 #define GMAC_OFR_OFRX_Msk ( 0x3ffu << GMAC_OFR_OFRX_Pos ) /**< \brief (GMAC_OFR) Oversized Frames Received */ 595 /* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ 596 #define GMAC_JR_JRX_Pos 0 597 #define GMAC_JR_JRX_Msk ( 0x3ffu << GMAC_JR_JRX_Pos ) /**< \brief (GMAC_JR) Jabbers Received */ 598 /* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ 599 #define GMAC_FCSE_FCKR_Pos 0 600 #define GMAC_FCSE_FCKR_Msk ( 0x3ffu << GMAC_FCSE_FCKR_Pos ) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ 601 /* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ 602 #define GMAC_LFFE_LFER_Pos 0 603 #define GMAC_LFFE_LFER_Msk ( 0x3ffu << GMAC_LFFE_LFER_Pos ) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ 604 /* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ 605 #define GMAC_RSE_RXSE_Pos 0 606 #define GMAC_RSE_RXSE_Msk ( 0x3ffu << GMAC_RSE_RXSE_Pos ) /**< \brief (GMAC_RSE) Receive Symbol Errors */ 607 /* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ 608 #define GMAC_AE_AER_Pos 0 609 #define GMAC_AE_AER_Msk ( 0x3ffu << GMAC_AE_AER_Pos ) /**< \brief (GMAC_AE) Alignment Errors */ 610 /* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ 611 #define GMAC_RRE_RXRER_Pos 0 612 #define GMAC_RRE_RXRER_Msk ( 0x3ffffu << GMAC_RRE_RXRER_Pos ) /**< \brief (GMAC_RRE) Receive Resource Errors */ 613 /* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ 614 #define GMAC_ROE_RXOVR_Pos 0 615 #define GMAC_ROE_RXOVR_Msk ( 0x3ffu << GMAC_ROE_RXOVR_Pos ) /**< \brief (GMAC_ROE) Receive Overruns */ 616 /* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ 617 #define GMAC_IHCE_HCKER_Pos 0 618 #define GMAC_IHCE_HCKER_Msk ( 0xffu << GMAC_IHCE_HCKER_Pos ) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ 619 /* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ 620 #define GMAC_TCE_TCKER_Pos 0 621 #define GMAC_TCE_TCKER_Msk ( 0xffu << GMAC_TCE_TCKER_Pos ) /**< \brief (GMAC_TCE) TCP Checksum Errors */ 622 /* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ 623 #define GMAC_UCE_UCKER_Pos 0 624 #define GMAC_UCE_UCKER_Msk ( 0xffu << GMAC_UCE_UCKER_Pos ) /**< \brief (GMAC_UCE) UDP Checksum Errors */ 625 /* -------- GMAC_TSSS : (GMAC Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register -------- */ 626 #define GMAC_TSSS_VTS_Pos 0 627 #define GMAC_TSSS_VTS_Msk ( 0xffffffffu << GMAC_TSSS_VTS_Pos ) /**< \brief (GMAC_TSSS) Value of Timer Seconds Register Capture */ 628 #define GMAC_TSSS_VTS( value ) ( ( GMAC_TSSS_VTS_Msk & ( ( value ) << GMAC_TSSS_VTS_Pos ) ) ) 629 /* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register -------- */ 630 #define GMAC_TSSN_VTN_Pos 0 631 #define GMAC_TSSN_VTN_Msk ( 0x3fffffffu << GMAC_TSSN_VTN_Pos ) /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */ 632 #define GMAC_TSSN_VTN( value ) ( ( GMAC_TSSN_VTN_Msk & ( ( value ) << GMAC_TSSN_VTN_Pos ) ) ) 633 /* -------- GMAC_TS : (GMAC Offset: 0x1D0) 1588 Timer Seconds Register -------- */ 634 #define GMAC_TS_TCS_Pos 0 635 #define GMAC_TS_TCS_Msk ( 0xffffffffu << GMAC_TS_TCS_Pos ) /**< \brief (GMAC_TS) Timer Count in Seconds */ 636 #define GMAC_TS_TCS( value ) ( ( GMAC_TS_TCS_Msk & ( ( value ) << GMAC_TS_TCS_Pos ) ) ) 637 /* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ 638 #define GMAC_TN_TNS_Pos 0 639 #define GMAC_TN_TNS_Msk ( 0x3fffffffu << GMAC_TN_TNS_Pos ) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ 640 #define GMAC_TN_TNS( value ) ( ( GMAC_TN_TNS_Msk & ( ( value ) << GMAC_TN_TNS_Pos ) ) ) 641 /* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ 642 #define GMAC_TA_ITDT_Pos 0 643 #define GMAC_TA_ITDT_Msk ( 0x3fffffffu << GMAC_TA_ITDT_Pos ) /**< \brief (GMAC_TA) Increment/Decrement */ 644 #define GMAC_TA_ITDT( value ) ( ( GMAC_TA_ITDT_Msk & ( ( value ) << GMAC_TA_ITDT_Pos ) ) ) 645 #define GMAC_TA_ADJ ( 0x1u << 31 ) /**< \brief (GMAC_TA) Adjust 1588 Timer */ 646 /* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ 647 #define GMAC_TI_CNS_Pos 0 648 #define GMAC_TI_CNS_Msk ( 0xffu << GMAC_TI_CNS_Pos ) /**< \brief (GMAC_TI) Count Nanoseconds */ 649 #define GMAC_TI_CNS( value ) ( ( GMAC_TI_CNS_Msk & ( ( value ) << GMAC_TI_CNS_Pos ) ) ) 650 #define GMAC_TI_ACNS_Pos 8 651 #define GMAC_TI_ACNS_Msk ( 0xffu << GMAC_TI_ACNS_Pos ) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ 652 #define GMAC_TI_ACNS( value ) ( ( GMAC_TI_ACNS_Msk & ( ( value ) << GMAC_TI_ACNS_Pos ) ) ) 653 #define GMAC_TI_NIT_Pos 16 654 #define GMAC_TI_NIT_Msk ( 0xffu << GMAC_TI_NIT_Pos ) /**< \brief (GMAC_TI) Number of Increments */ 655 #define GMAC_TI_NIT( value ) ( ( GMAC_TI_NIT_Msk & ( ( value ) << GMAC_TI_NIT_Pos ) ) ) 656 /* -------- GMAC_EFTS : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds -------- */ 657 #define GMAC_EFTS_RUD_Pos 0 658 #define GMAC_EFTS_RUD_Msk ( 0xffffffffu << GMAC_EFTS_RUD_Pos ) /**< \brief (GMAC_EFTS) Register Update */ 659 /* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds -------- */ 660 #define GMAC_EFTN_RUD_Pos 0 661 #define GMAC_EFTN_RUD_Msk ( 0x3fffffffu << GMAC_EFTN_RUD_Pos ) /**< \brief (GMAC_EFTN) Register Update */ 662 /* -------- GMAC_EFRS : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds -------- */ 663 #define GMAC_EFRS_RUD_Pos 0 664 #define GMAC_EFRS_RUD_Msk ( 0xffffffffu << GMAC_EFRS_RUD_Pos ) /**< \brief (GMAC_EFRS) Register Update */ 665 /* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds -------- */ 666 #define GMAC_EFRN_RUD_Pos 0 667 #define GMAC_EFRN_RUD_Msk ( 0x3fffffffu << GMAC_EFRN_RUD_Pos ) /**< \brief (GMAC_EFRN) Register Update */ 668 /* -------- GMAC_PEFTS : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds -------- */ 669 #define GMAC_PEFTS_RUD_Pos 0 670 #define GMAC_PEFTS_RUD_Msk ( 0xffffffffu << GMAC_PEFTS_RUD_Pos ) /**< \brief (GMAC_PEFTS) Register Update */ 671 /* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds -------- */ 672 #define GMAC_PEFTN_RUD_Pos 0 673 #define GMAC_PEFTN_RUD_Msk ( 0x3fffffffu << GMAC_PEFTN_RUD_Pos ) /**< \brief (GMAC_PEFTN) Register Update */ 674 /* -------- GMAC_PEFRS : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds -------- */ 675 #define GMAC_PEFRS_RUD_Pos 0 676 #define GMAC_PEFRS_RUD_Msk ( 0xffffffffu << GMAC_PEFRS_RUD_Pos ) /**< \brief (GMAC_PEFRS) Register Update */ 677 /* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds -------- */ 678 #define GMAC_PEFRN_RUD_Pos 0 679 #define GMAC_PEFRN_RUD_Msk ( 0x3fffffffu << GMAC_PEFRN_RUD_Pos ) /**< \brief (GMAC_PEFRN) Register Update */ 680 /* -------- GMAC_ISRPQ[7] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue -------- */ 681 #define GMAC_ISRPQ_RCOMP ( 0x1u << 1 ) /**< \brief (GMAC_ISRPQ[7]) Receive Complete */ 682 #define GMAC_ISRPQ_RXUBR ( 0x1u << 2 ) /**< \brief (GMAC_ISRPQ[7]) RX Used Bit Read */ 683 #define GMAC_ISRPQ_RLEX ( 0x1u << 5 ) /**< \brief (GMAC_ISRPQ[7]) Retry Limit Exceeded or Late Collision */ 684 #define GMAC_ISRPQ_TFC ( 0x1u << 6 ) /**< \brief (GMAC_ISRPQ[7]) Transmit Frame Corruption due to AHB error */ 685 #define GMAC_ISRPQ_TCOMP ( 0x1u << 7 ) /**< \brief (GMAC_ISRPQ[7]) Transmit Complete */ 686 #define GMAC_ISRPQ_ROVR ( 0x1u << 10 ) /**< \brief (GMAC_ISRPQ[7]) Receive Overrun */ 687 #define GMAC_ISRPQ_HRESP ( 0x1u << 11 ) /**< \brief (GMAC_ISRPQ[7]) HRESP Not OK */ 688 /* -------- GMAC_TBQBAPQ[7] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue -------- */ 689 #define GMAC_TBQBAPQ_TXBQBA_Pos 2 690 #define GMAC_TBQBAPQ_TXBQBA_Msk ( 0x3fu << GMAC_TBQBAPQ_TXBQBA_Pos ) /**< \brief (GMAC_TBQBAPQ[7]) Transmit Buffer Queue Base Address */ 691 #define GMAC_TBQBAPQ_TXBQBA( value ) ( ( GMAC_TBQBAPQ_TXBQBA_Msk & ( ( value ) << GMAC_TBQBAPQ_TXBQBA_Pos ) ) ) 692 /* -------- GMAC_RBQBAPQ[7] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Priority Queue -------- */ 693 #define GMAC_RBQBAPQ_RXBQBA_Pos 2 694 #define GMAC_RBQBAPQ_RXBQBA_Msk ( 0x3fu << GMAC_RBQBAPQ_RXBQBA_Pos ) /**< \brief (GMAC_RBQBAPQ[7]) Receive Buffer Queue Base Address */ 695 #define GMAC_RBQBAPQ_RXBQBA( value ) ( ( GMAC_RBQBAPQ_RXBQBA_Msk & ( ( value ) << GMAC_RBQBAPQ_RXBQBA_Pos ) ) ) 696 /* -------- GMAC_RBSRPQ[7] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue -------- */ 697 #define GMAC_RBSRPQ_RBS_Pos 0 698 #define GMAC_RBSRPQ_RBS_Msk ( 0xffffu << GMAC_RBSRPQ_RBS_Pos ) /**< \brief (GMAC_RBSRPQ[7]) Receive Buffer Size */ 699 #define GMAC_RBSRPQ_RBS( value ) ( ( GMAC_RBSRPQ_RBS_Msk & ( ( value ) << GMAC_RBSRPQ_RBS_Pos ) ) ) 700 /* -------- GMAC_ST1RPQ[16] : (GMAC Offset: 0x500) Screening Type1 Register Priority Queue -------- */ 701 #define GMAC_ST1RPQ_QNB_Pos 0 702 #define GMAC_ST1RPQ_QNB_Msk ( 0xfu << GMAC_ST1RPQ_QNB_Pos ) /**< \brief (GMAC_ST1RPQ[16]) Que Number (0->7) */ 703 #define GMAC_ST1RPQ_QNB( value ) ( ( GMAC_ST1RPQ_QNB_Msk & ( ( value ) << GMAC_ST1RPQ_QNB_Pos ) ) ) 704 #define GMAC_ST1RPQ_DSTCM_Pos 4 705 #define GMAC_ST1RPQ_DSTCM_Msk ( 0xffu << GMAC_ST1RPQ_DSTCM_Pos ) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match */ 706 #define GMAC_ST1RPQ_DSTCM( value ) ( ( GMAC_ST1RPQ_DSTCM_Msk & ( ( value ) << GMAC_ST1RPQ_DSTCM_Pos ) ) ) 707 #define GMAC_ST1RPQ_UDPM_Pos 12 708 #define GMAC_ST1RPQ_UDPM_Msk ( 0xffffu << GMAC_ST1RPQ_UDPM_Pos ) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match */ 709 #define GMAC_ST1RPQ_UDPM( value ) ( ( GMAC_ST1RPQ_UDPM_Msk & ( ( value ) << GMAC_ST1RPQ_UDPM_Pos ) ) ) 710 #define GMAC_ST1RPQ_DSTCE ( 0x1u << 28 ) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match Enable */ 711 #define GMAC_ST1RPQ_UDPE ( 0x1u << 29 ) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match Enable */ 712 /* -------- GMAC_ST2RPQ[16] : (GMAC Offset: 0x540) Screening Type2 Register Priority Queue -------- */ 713 #define GMAC_ST2RPQ_QNB_Pos 0 714 #define GMAC_ST2RPQ_QNB_Msk ( 0xfu << GMAC_ST2RPQ_QNB_Pos ) /**< \brief (GMAC_ST2RPQ[16]) Que Number (0->7) */ 715 #define GMAC_ST2RPQ_QNB( value ) ( ( GMAC_ST2RPQ_QNB_Msk & ( ( value ) << GMAC_ST2RPQ_QNB_Pos ) ) ) 716 #define GMAC_ST2RPQ_VLANP_Pos 4 717 #define GMAC_ST2RPQ_VLANP_Msk ( 0xfu << GMAC_ST2RPQ_VLANP_Pos ) /**< \brief (GMAC_ST2RPQ[16]) VLAN Priority */ 718 #define GMAC_ST2RPQ_VLANP( value ) ( ( GMAC_ST2RPQ_VLANP_Msk & ( ( value ) << GMAC_ST2RPQ_VLANP_Pos ) ) ) 719 #define GMAC_ST2RPQ_VLANE ( 0x1u << 8 ) /**< \brief (GMAC_ST2RPQ[16]) VLAN Enable */ 720 /* -------- GMAC_IERPQ[7] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue -------- */ 721 #define GMAC_IERPQ_RCOMP ( 0x1u << 1 ) /**< \brief (GMAC_IERPQ[7]) Receive Complete */ 722 #define GMAC_IERPQ_RXUBR ( 0x1u << 2 ) /**< \brief (GMAC_IERPQ[7]) RX Used Bit Read */ 723 #define GMAC_IERPQ_RLEX ( 0x1u << 5 ) /**< \brief (GMAC_IERPQ[7]) Retry Limit Exceeded or Late Collision */ 724 #define GMAC_IERPQ_TFC ( 0x1u << 6 ) /**< \brief (GMAC_IERPQ[7]) Transmit Frame Corruption due to AHB error */ 725 #define GMAC_IERPQ_TCOMP ( 0x1u << 7 ) /**< \brief (GMAC_IERPQ[7]) Transmit Complete */ 726 #define GMAC_IERPQ_ROVR ( 0x1u << 10 ) /**< \brief (GMAC_IERPQ[7]) Receive Overrun */ 727 #define GMAC_IERPQ_HRESP ( 0x1u << 11 ) /**< \brief (GMAC_IERPQ[7]) HRESP Not OK */ 728 /* -------- GMAC_IDRPQ[7] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue -------- */ 729 #define GMAC_IDRPQ_RCOMP ( 0x1u << 1 ) /**< \brief (GMAC_IDRPQ[7]) Receive Complete */ 730 #define GMAC_IDRPQ_RXUBR ( 0x1u << 2 ) /**< \brief (GMAC_IDRPQ[7]) RX Used Bit Read */ 731 #define GMAC_IDRPQ_RLEX ( 0x1u << 5 ) /**< \brief (GMAC_IDRPQ[7]) Retry Limit Exceeded or Late Collision */ 732 #define GMAC_IDRPQ_TFC ( 0x1u << 6 ) /**< \brief (GMAC_IDRPQ[7]) Transmit Frame Corruption due to AHB error */ 733 #define GMAC_IDRPQ_TCOMP ( 0x1u << 7 ) /**< \brief (GMAC_IDRPQ[7]) Transmit Complete */ 734 #define GMAC_IDRPQ_ROVR ( 0x1u << 10 ) /**< \brief (GMAC_IDRPQ[7]) Receive Overrun */ 735 #define GMAC_IDRPQ_HRESP ( 0x1u << 11 ) /**< \brief (GMAC_IDRPQ[7]) HRESP Not OK */ 736 /* -------- GMAC_IMRPQ[7] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue -------- */ 737 #define GMAC_IMRPQ_RCOMP ( 0x1u << 1 ) /**< \brief (GMAC_IMRPQ[7]) Receive Complete */ 738 #define GMAC_IMRPQ_RXUBR ( 0x1u << 2 ) /**< \brief (GMAC_IMRPQ[7]) RX Used Bit Read */ 739 #define GMAC_IMRPQ_RLEX ( 0x1u << 5 ) /**< \brief (GMAC_IMRPQ[7]) Retry Limit Exceeded or Late Collision */ 740 #define GMAC_IMRPQ_AHB ( 0x1u << 6 ) /**< \brief (GMAC_IMRPQ[7]) AHB Error */ 741 #define GMAC_IMRPQ_TCOMP ( 0x1u << 7 ) /**< \brief (GMAC_IMRPQ[7]) Transmit Complete */ 742 #define GMAC_IMRPQ_ROVR ( 0x1u << 10 ) /**< \brief (GMAC_IMRPQ[7]) Receive Overrun */ 743 #define GMAC_IMRPQ_HRESP ( 0x1u << 11 ) /**< \brief (GMAC_IMRPQ[7]) HRESP Not OK */ 744 745 /*@}*/ 746 747 748 #endif /* _SAM4E_GMAC_COMPONENT_ */ 749
xref:
/FreeRTOS-Plus-TCP-v3.1.0/source/portable/NetworkInterface/ATSAM4E/component/gmac.h
(revision a4124602cc584fa0658448c229f48a459a84fbb1)