1 /** 2 * \file 3 * 4 * \brief GMAC (Ethernet MAC) driver for SAM. 5 * 6 * Copyright (c) 2013 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 44 #ifndef GMAC_H_INCLUDED 45 #define GMAC_H_INCLUDED 46 47 #include "compiler.h" 48 #include "component/gmac.h" 49 50 /*/ @cond 0 */ 51 /**INDENT-OFF**/ 52 #ifdef __cplusplus 53 extern "C" { 54 #endif 55 /**INDENT-ON**/ 56 /*/ @endcond */ 57 58 /** The buffer addresses written into the descriptors must be aligned, so the 59 * last few bits are zero. These bits have special meaning for the GMAC 60 * peripheral and cannot be used as part of the address. */ 61 #define GMAC_RXD_ADDR_MASK 0xFFFFFFFC 62 #define GMAC_RXD_WRAP ( 1ul << 1 ) /**< Wrap bit */ 63 #define GMAC_RXD_OWNERSHIP ( 1ul << 0 ) /**< Ownership bit */ 64 65 #define GMAC_RXD_BROADCAST ( 1ul << 31 ) /**< Broadcast detected */ 66 #define GMAC_RXD_MULTIHASH ( 1ul << 30 ) /**< Multicast hash match */ 67 #define GMAC_RXD_UNIHASH ( 1ul << 29 ) /**< Unicast hash match */ 68 #define GMAC_RXD_ADDR_FOUND ( 1ul << 27 ) /**< Specific address match found */ 69 #define GMAC_RXD_ADDR ( 3ul << 25 ) /**< Address match */ 70 #define GMAC_RXD_RXCOEN ( 1ul << 24 ) /**< RXCOEN related function */ 71 #define GMAC_RXD_TYPE ( 3ul << 22 ) /**< Type ID match */ 72 #define GMAC_RXD_VLAN ( 1ul << 21 ) /**< VLAN tag detected */ 73 #define GMAC_RXD_PRIORITY ( 1ul << 20 ) /**< Priority tag detected */ 74 #define GMAC_RXD_PRIORITY_MASK ( 3ul << 17 ) /**< VLAN priority */ 75 #define GMAC_RXD_CFI ( 1ul << 16 ) /**< Concatenation Format Indicator only if bit 21 is set */ 76 #define GMAC_RXD_EOF ( 1ul << 15 ) /**< End of frame */ 77 #define GMAC_RXD_SOF ( 1ul << 14 ) /**< Start of frame */ 78 #define GMAC_RXD_FCS ( 1ul << 13 ) /**< Frame check sequence */ 79 #define GMAC_RXD_OFFSET_MASK /**< Receive buffer offset */ 80 #define GMAC_RXD_LEN_MASK ( 0xFFF ) /**< Length of frame including FCS (if selected) */ 81 #define GMAC_RXD_LENJUMBO_MASK ( 0x3FFF ) /**< Jumbo frame length */ 82 83 #define GMAC_TXD_USED ( 1ul << 31 ) /**< Frame is transmitted */ 84 #define GMAC_TXD_WRAP ( 1ul << 30 ) /**< Last descriptor */ 85 #define GMAC_TXD_ERROR ( 1ul << 29 ) /**< Retry limit exceeded, error */ 86 #define GMAC_TXD_UNDERRUN ( 1ul << 28 ) /**< Transmit underrun */ 87 #define GMAC_TXD_EXHAUSTED ( 1ul << 27 ) /**< Buffer exhausted */ 88 #define GMAC_TXD_LATE ( 1ul << 26 ) /**< Late collision,transmit error */ 89 #define GMAC_TXD_CHECKSUM_ERROR ( 7ul << 20 ) /**< Checksum error */ 90 #define GMAC_TXD_NOCRC ( 1ul << 16 ) /**< No CRC */ 91 #define GMAC_TXD_LAST ( 1ul << 15 ) /**< Last buffer in frame */ 92 #define GMAC_TXD_LEN_MASK ( 0x1FFF ) /**< Length of buffer */ 93 94 /** The MAC can support frame lengths up to 1536 bytes */ 95 #define GMAC_FRAME_LENTGH_MAX 1536 96 97 #define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */ 98 #define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */ 99 100 /** GMAC clock speed */ 101 #define GMAC_MCK_SPEED_240MHZ ( 240 * 1000 * 1000 ) 102 #define GMAC_MCK_SPEED_160MHZ ( 160 * 1000 * 1000 ) 103 #define GMAC_MCK_SPEED_120MHZ ( 120 * 1000 * 1000 ) 104 #define GMAC_MCK_SPEED_80MHZ ( 80 * 1000 * 1000 ) 105 #define GMAC_MCK_SPEED_40MHZ ( 40 * 1000 * 1000 ) 106 #define GMAC_MCK_SPEED_20MHZ ( 20 * 1000 * 1000 ) 107 108 /** GMAC maintain code default value*/ 109 #define GMAC_MAN_CODE_VALUE ( 10 ) 110 111 /** GMAC maintain start of frame default value*/ 112 #define GMAC_MAN_SOF_VALUE ( 1 ) 113 114 /** GMAC maintain read/write*/ 115 #define GMAC_MAN_RW_TYPE ( 2 ) 116 117 /** GMAC maintain read only*/ 118 #define GMAC_MAN_READ_ONLY ( 1 ) 119 120 /** GMAC address length */ 121 #define GMAC_ADDR_LENGTH ( 6 ) 122 123 124 #define GMAC_DUPLEX_HALF 0 125 #define GMAC_DUPLEX_FULL 1 126 127 #define GMAC_SPEED_10M 0 128 #define GMAC_SPEED_100M 1 129 130 /** 131 * \brief Return codes for GMAC APIs. 132 */ 133 typedef enum 134 { 135 GMAC_OK = 0, /** 0 Operation OK */ 136 GMAC_TIMEOUT = 1, /** 1 GMAC operation timeout */ 137 GMAC_TX_BUSY, /** 2 TX in progress */ 138 GMAC_RX_NULL, /** 3 No data received */ 139 GMAC_SIZE_TOO_SMALL, /** 4 Buffer size not enough */ 140 GMAC_PARAM, /** 5 Parameter error, TX packet invalid or RX size too small */ 141 GMAC_INVALID = 0xFF, /* Invalid */ 142 } gmac_status_t; 143 144 /** 145 * \brief Media Independent Interface (MII) type. 146 */ 147 typedef enum 148 { 149 GMAC_PHY_MII = 0, /** MII mode */ 150 GMAC_PHY_RMII = 1, /** Reduced MII mode */ 151 GMAC_PHY_INVALID = 0xFF, /* Invalid mode*/ 152 } gmac_mii_mode_t; 153 154 /** Receive buffer descriptor struct */ 155 COMPILER_PACK_SET( 8 ) 156 typedef struct gmac_rx_descriptor 157 { 158 union gmac_rx_addr 159 { 160 uint32_t val; 161 struct gmac_rx_addr_bm 162 { 163 uint32_t b_ownership : 1, /**< User clear, GMAC sets this to 1 once it has successfully written a frame to memory */ 164 b_wrap : 1, /**< Marks last descriptor in receive buffer */ 165 addr_dw : 30; /**< Address in number of DW */ 166 } bm; 167 } addr; /**< Address, Wrap & Ownership */ 168 union gmac_rx_status 169 { 170 uint32_t val; 171 struct gmac_rx_status_bm 172 { 173 uint32_t len : 13, /** 0..12 Length of frame including FCS */ 174 b_fcs : 1, /** 13 Receive buffer offset, bits 13:12 of frame length for jumbo frame */ 175 b_sof : 1, /** 14 Start of frame */ 176 b_eof : 1, /** 15 End of frame */ 177 b_cfi : 1, /** 16 Concatenation Format Indicator */ 178 vlan_priority : 3, /** 17..19 VLAN priority (if VLAN detected) */ 179 b_priority_detected : 1, /** 20 Priority tag detected */ 180 b_vlan_detected : 1, /** 21 VLAN tag detected */ 181 b_type_id_match : 2, /** 22..23 Type ID match */ 182 b_checksumoffload : 1, /** 24 Checksum offload specific function */ 183 b_addrmatch : 2, /** 25..26 Address register match */ 184 b_ext_addr_match : 1, /** 27 External address match found */ 185 reserved : 1, /** 28 */ 186 b_uni_hash_match : 1, /** 29 Unicast hash match */ 187 b_multi_hash_match : 1, /** 30 Multicast hash match */ 188 b_boardcast_detect : 1; /** 31 Global broadcast address detected */ 189 } bm; 190 } status; 191 } gmac_rx_descriptor_t; 192 193 /** Transmit buffer descriptor struct */ 194 COMPILER_PACK_SET( 8 ) 195 typedef struct gmac_tx_descriptor 196 { 197 uint32_t addr; 198 union gmac_tx_status 199 { 200 uint32_t val; 201 struct gmac_tx_status_bm 202 { 203 uint32_t len : 14, /** 0..13 Length of buffer */ 204 reserved : 1, /** 14 */ 205 b_last_buffer : 1, /** 15 Last buffer (in the current frame) */ 206 b_no_crc : 1, /** 16 No CRC */ 207 reserved1 : 3, /** 17..19 */ 208 b_checksumoffload : 3, /** 20..22 Transmit checksum generation offload errors */ 209 reserved2 : 3, /** 23..25 */ 210 b_lco : 1, /** 26 Late collision, transmit error detected */ 211 b_exhausted : 1, /** 27 Buffer exhausted in mid frame */ 212 b_underrun : 1, /** 28 Transmit underrun */ 213 b_error : 1, /** 29 Retry limit exceeded, error detected */ 214 b_wrap : 1, /** 30 Marks last descriptor in TD list */ 215 b_used : 1; /** 31 User clear, GMAC sets this to 1 once a frame has been successfully transmitted */ 216 } bm; 217 } status; 218 } gmac_tx_descriptor_t; 219 220 COMPILER_PACK_RESET() 221 222 /** 223 * \brief Input parameters when initializing the gmac module mode. 224 */ 225 typedef struct gmac_options 226 { 227 /* Enable/Disable CopyAllFrame */ 228 uint8_t uc_copy_all_frame; 229 /* Enable/Disable NoBroadCast */ 230 uint8_t uc_no_boardcast; 231 /* MAC address */ 232 uint8_t uc_mac_addr[ GMAC_ADDR_LENGTH ]; 233 } gmac_options_t; 234 235 /** TX callback */ 236 typedef void (* gmac_dev_tx_cb_t) ( uint32_t ul_status, 237 uint8_t * puc_buffer ); 238 /** RX callback */ 239 typedef void (* gmac_dev_rx_cb_t) ( uint32_t ul_status ); 240 /** Wakeup callback */ 241 typedef void (* gmac_dev_wakeup_cb_t) ( void ); 242 243 /** 244 * GMAC driver structure. 245 */ 246 typedef struct gmac_device 247 { 248 /** Pointer to HW register base */ 249 Gmac * p_hw; 250 251 /** 252 * Pointer to allocated TX buffer. 253 * Section 3.6 of AMBA 2.0 spec states that burst should not cross 254 * 1K Boundaries. 255 * Receive buffer manager writes are burst of 2 words => 3 lsb bits 256 * of the address shall be set to 0. 257 */ 258 uint8_t * p_tx_buffer; 259 /** Pointer to allocated RX buffer */ 260 uint8_t * p_rx_buffer; 261 /** Pointer to Rx TDs (must be 8-byte aligned) */ 262 gmac_rx_descriptor_t * p_rx_dscr; 263 /** Pointer to Tx TDs (must be 8-byte aligned) */ 264 gmac_tx_descriptor_t * p_tx_dscr; 265 /** Optional callback to be invoked once a frame has been received */ 266 gmac_dev_rx_cb_t func_rx_cb; 267 #if ( GMAC_USES_WAKEUP_CALLBACK ) 268 /** Optional callback to be invoked once several TDs have been released */ 269 gmac_dev_wakeup_cb_t func_wakeup_cb; 270 #endif 271 #if ( GMAC_USES_TX_CALLBACK != 0 ) 272 /** Optional callback list to be invoked once TD has been processed */ 273 gmac_dev_tx_cb_t * func_tx_cb_list; 274 #endif 275 /** RX TD list size */ 276 uint32_t ul_rx_list_size; 277 /** RX index for current processing TD */ 278 uint32_t ul_rx_idx; 279 /** TX TD list size */ 280 uint32_t ul_tx_list_size; 281 /** Circular buffer head pointer by upper layer (buffer to be sent) */ 282 int32_t l_tx_head; 283 /** Circular buffer tail pointer incremented by handlers (buffer sent) */ 284 int32_t l_tx_tail; 285 286 /** Number of free TD before wakeup callback is invoked */ 287 uint32_t uc_wakeup_threshold; 288 } gmac_device_t; 289 290 /** 291 * \brief Write network control value. 292 * 293 * \param p_gmac Pointer to the GMAC instance. 294 * \param ul_ncr Network control value. 295 */ gmac_network_control(Gmac * p_gmac,uint32_t ul_ncr)296 static inline void gmac_network_control( Gmac * p_gmac, 297 uint32_t ul_ncr ) 298 { 299 p_gmac->GMAC_NCR = ul_ncr; 300 } 301 302 /** 303 * \brief Get network control value. 304 * 305 * \param p_gmac Pointer to the GMAC instance. 306 */ 307 gmac_get_network_control(Gmac * p_gmac)308 static inline uint32_t gmac_get_network_control( Gmac * p_gmac ) 309 { 310 return p_gmac->GMAC_NCR; 311 } 312 313 /** 314 * \brief Enable/Disable GMAC receive. 315 * 316 * \param p_gmac Pointer to the GMAC instance. 317 * \param uc_enable 0 to disable GMAC receiver, else to enable it. 318 */ gmac_enable_receive(Gmac * p_gmac,uint8_t uc_enable)319 static inline void gmac_enable_receive( Gmac * p_gmac, 320 uint8_t uc_enable ) 321 { 322 if( uc_enable ) 323 { 324 p_gmac->GMAC_NCR |= GMAC_NCR_RXEN; 325 } 326 else 327 { 328 p_gmac->GMAC_NCR &= ~GMAC_NCR_RXEN; 329 } 330 } 331 332 /** 333 * \brief Enable/Disable GMAC transmit. 334 * 335 * \param p_gmac Pointer to the GMAC instance. 336 * \param uc_enable 0 to disable GMAC transmit, else to enable it. 337 */ gmac_enable_transmit(Gmac * p_gmac,uint8_t uc_enable)338 static inline void gmac_enable_transmit( Gmac * p_gmac, 339 uint8_t uc_enable ) 340 { 341 if( uc_enable ) 342 { 343 p_gmac->GMAC_NCR |= GMAC_NCR_TXEN; 344 } 345 else 346 { 347 p_gmac->GMAC_NCR &= ~GMAC_NCR_TXEN; 348 } 349 } 350 351 /** 352 * \brief Enable/Disable GMAC management. 353 * 354 * \param p_gmac Pointer to the GMAC instance. 355 * \param uc_enable 0 to disable GMAC management, else to enable it. 356 */ gmac_enable_management(Gmac * p_gmac,uint8_t uc_enable)357 static inline void gmac_enable_management( Gmac * p_gmac, 358 uint8_t uc_enable ) 359 { 360 if( uc_enable ) 361 { 362 p_gmac->GMAC_NCR |= GMAC_NCR_MPE; 363 } 364 else 365 { 366 p_gmac->GMAC_NCR &= ~GMAC_NCR_MPE; 367 } 368 } 369 370 /** 371 * \brief Clear all statistics registers. 372 * 373 * \param p_gmac Pointer to the GMAC instance. 374 */ gmac_clear_statistics(Gmac * p_gmac)375 static inline void gmac_clear_statistics( Gmac * p_gmac ) 376 { 377 p_gmac->GMAC_NCR |= GMAC_NCR_CLRSTAT; 378 } 379 380 /** 381 * \brief Increase all statistics registers. 382 * 383 * \param p_gmac Pointer to the GMAC instance. 384 */ gmac_increase_statistics(Gmac * p_gmac)385 static inline void gmac_increase_statistics( Gmac * p_gmac ) 386 { 387 p_gmac->GMAC_NCR |= GMAC_NCR_INCSTAT; 388 } 389 390 /** 391 * \brief Enable/Disable statistics registers writing. 392 * 393 * \param p_gmac Pointer to the GMAC instance. 394 * \param uc_enable 0 to disable the statistics registers writing, else to enable it. 395 */ gmac_enable_statistics_write(Gmac * p_gmac,uint8_t uc_enable)396 static inline void gmac_enable_statistics_write( Gmac * p_gmac, 397 uint8_t uc_enable ) 398 { 399 if( uc_enable ) 400 { 401 p_gmac->GMAC_NCR |= GMAC_NCR_WESTAT; 402 } 403 else 404 { 405 p_gmac->GMAC_NCR &= ~GMAC_NCR_WESTAT; 406 } 407 } 408 409 /** 410 * \brief In half-duplex mode, forces collisions on all received frames. 411 * 412 * \param p_gmac Pointer to the GMAC instance. 413 * \param uc_enable 0 to disable the back pressure, else to enable it. 414 */ gmac_enable_back_pressure(Gmac * p_gmac,uint8_t uc_enable)415 static inline void gmac_enable_back_pressure( Gmac * p_gmac, 416 uint8_t uc_enable ) 417 { 418 if( uc_enable ) 419 { 420 p_gmac->GMAC_NCR |= GMAC_NCR_BP; 421 } 422 else 423 { 424 p_gmac->GMAC_NCR &= ~GMAC_NCR_BP; 425 } 426 } 427 428 /** 429 * \brief Start transmission. 430 * 431 * \param p_gmac Pointer to the GMAC instance. 432 */ gmac_start_transmission(Gmac * p_gmac)433 static inline void gmac_start_transmission( Gmac * p_gmac ) 434 { 435 p_gmac->GMAC_NCR |= GMAC_NCR_TSTART; 436 } 437 438 /** 439 * \brief Halt transmission. 440 * 441 * \param p_gmac Pointer to the GMAC instance. 442 */ gmac_halt_transmission(Gmac * p_gmac)443 static inline void gmac_halt_transmission( Gmac * p_gmac ) 444 { 445 p_gmac->GMAC_NCR |= GMAC_NCR_THALT; 446 } 447 448 /** 449 * \brief Transmit pause frame. 450 * 451 * \param p_gmac Pointer to the GMAC instance. 452 */ gmac_tx_pause_frame(Gmac * p_gmac)453 static inline void gmac_tx_pause_frame( Gmac * p_gmac ) 454 { 455 p_gmac->GMAC_NCR |= GMAC_NCR_TXPF; 456 } 457 458 /** 459 * \brief Transmit zero quantum pause frame. 460 * 461 * \param p_gmac Pointer to the GMAC instance. 462 */ gmac_tx_pause_zero_quantum_frame(Gmac * p_gmac)463 static inline void gmac_tx_pause_zero_quantum_frame( Gmac * p_gmac ) 464 { 465 p_gmac->GMAC_NCR |= GMAC_NCR_TXZQPF; 466 } 467 468 /** 469 * \brief Read snapshot. 470 * 471 * \param p_gmac Pointer to the GMAC instance. 472 */ gmac_read_snapshot(Gmac * p_gmac)473 static inline void gmac_read_snapshot( Gmac * p_gmac ) 474 { 475 p_gmac->GMAC_NCR |= GMAC_NCR_RDS; 476 } 477 478 /** 479 * \brief Store receivetime stamp to memory. 480 * 481 * \param p_gmac Pointer to the GMAC instance. 482 * \param uc_enable 0 to normal operation, else to enable the store. 483 */ gmac_store_rx_time_stamp(Gmac * p_gmac,uint8_t uc_enable)484 static inline void gmac_store_rx_time_stamp( Gmac * p_gmac, 485 uint8_t uc_enable ) 486 { 487 if( uc_enable ) 488 { 489 p_gmac->GMAC_NCR |= GMAC_NCR_SRTSM; 490 } 491 else 492 { 493 p_gmac->GMAC_NCR &= ~GMAC_NCR_SRTSM; 494 } 495 } 496 497 /** 498 * \brief Enable PFC priority-based pause reception. 499 * 500 * \param p_gmac Pointer to the GMAC instance. 501 * \param uc_enable 1 to set the reception, 0 to disable. 502 */ gmac_enable_pfc_pause_frame(Gmac * p_gmac,uint8_t uc_enable)503 static inline void gmac_enable_pfc_pause_frame( Gmac * p_gmac, 504 uint8_t uc_enable ) 505 { 506 if( uc_enable ) 507 { 508 p_gmac->GMAC_NCR |= GMAC_NCR_ENPBPR; 509 } 510 else 511 { 512 p_gmac->GMAC_NCR &= ~GMAC_NCR_ENPBPR; 513 } 514 } 515 516 /** 517 * \brief Transmit PFC priority-based pause reception. 518 * 519 * \param p_gmac Pointer to the GMAC instance. 520 */ gmac_transmit_pfc_pause_frame(Gmac * p_gmac)521 static inline void gmac_transmit_pfc_pause_frame( Gmac * p_gmac ) 522 { 523 p_gmac->GMAC_NCR |= GMAC_NCR_TXPBPF; 524 } 525 526 /** 527 * \brief Flush next packet. 528 * 529 * \param p_gmac Pointer to the GMAC instance. 530 */ gmac_flush_next_packet(Gmac * p_gmac)531 static inline void gmac_flush_next_packet( Gmac * p_gmac ) 532 { 533 p_gmac->GMAC_NCR |= GMAC_NCR_FNP; 534 } 535 536 /** 537 * \brief Set up network configuration register. 538 * 539 * \param p_gmac Pointer to the GMAC instance. 540 * \param ul_cfg Network configuration value. 541 */ gmac_set_configure(Gmac * p_gmac,uint32_t ul_cfg)542 static inline void gmac_set_configure( Gmac * p_gmac, 543 uint32_t ul_cfg ) 544 { 545 p_gmac->GMAC_NCFGR = ul_cfg; 546 } 547 548 /** 549 * \brief Get network configuration. 550 * 551 * \param p_gmac Pointer to the GMAC instance. 552 * 553 * \return Network configuration. 554 */ gmac_get_configure(Gmac * p_gmac)555 static inline uint32_t gmac_get_configure( Gmac * p_gmac ) 556 { 557 return p_gmac->GMAC_NCFGR; 558 } 559 560 561 /* Get and set DMA Configuration Register */ gmac_set_dma(Gmac * p_gmac,uint32_t ul_cfg)562 static inline void gmac_set_dma( Gmac * p_gmac, 563 uint32_t ul_cfg ) 564 { 565 p_gmac->GMAC_DCFGR = ul_cfg; 566 } 567 gmac_get_dma(Gmac * p_gmac)568 static inline uint32_t gmac_get_dma( Gmac * p_gmac ) 569 { 570 return p_gmac->GMAC_DCFGR; 571 } 572 573 /** 574 * \brief Set speed. 575 * 576 * \param p_gmac Pointer to the GMAC instance. 577 * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps. 578 */ gmac_set_speed(Gmac * p_gmac,uint8_t uc_speed)579 static inline void gmac_set_speed( Gmac * p_gmac, 580 uint8_t uc_speed ) 581 { 582 if( uc_speed ) 583 { 584 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_SPD; 585 } 586 else 587 { 588 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD; 589 } 590 } 591 592 /** 593 * \brief Enable/Disable Full-Duplex mode. 594 * 595 * \param p_gmac Pointer to the GMAC instance. 596 * \param uc_enable 0 to disable the Full-Duplex mode, else to enable it. 597 */ gmac_enable_full_duplex(Gmac * p_gmac,uint8_t uc_enable)598 static inline void gmac_enable_full_duplex( Gmac * p_gmac, 599 uint8_t uc_enable ) 600 { 601 if( uc_enable ) 602 { 603 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_FD; 604 } 605 else 606 { 607 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD; 608 } 609 } 610 611 /** 612 * \brief Enable/Disable Copy(Receive) All Valid Frames. 613 * 614 * \param p_gmac Pointer to the GMAC instance. 615 * \param uc_enable 0 to disable copying all valid frames, else to enable it. 616 */ gmac_enable_copy_all(Gmac * p_gmac,uint8_t uc_enable)617 static inline void gmac_enable_copy_all( Gmac * p_gmac, 618 uint8_t uc_enable ) 619 { 620 if( uc_enable ) 621 { 622 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_CAF; 623 } 624 else 625 { 626 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_CAF; 627 } 628 } 629 630 /** 631 * \brief Enable/Disable jumbo frames (up to 10240 bytes). 632 * 633 * \param p_gmac Pointer to the GMAC instance. 634 * \param uc_enable 0 to disable the jumbo frames, else to enable it. 635 */ gmac_enable_jumbo_frames(Gmac * p_gmac,uint8_t uc_enable)636 static inline void gmac_enable_jumbo_frames( Gmac * p_gmac, 637 uint8_t uc_enable ) 638 { 639 if( uc_enable ) 640 { 641 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_JFRAME; 642 } 643 else 644 { 645 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_JFRAME; 646 } 647 } 648 649 /** 650 * \brief Disable/Enable broadcast receiving. 651 * 652 * \param p_gmac Pointer to the GMAC instance. 653 * \param uc_enable 1 to disable the broadcast, else to enable it. 654 */ gmac_disable_broadcast(Gmac * p_gmac,uint8_t uc_enable)655 static inline void gmac_disable_broadcast( Gmac * p_gmac, 656 uint8_t uc_enable ) 657 { 658 if( uc_enable ) 659 { 660 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_NBC; 661 } 662 else 663 { 664 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_NBC; 665 } 666 } 667 668 /** 669 * \brief Enable/Disable multicast hash. 670 * 671 * \param p_gmac Pointer to the GMAC instance. 672 * \param uc_enable 0 to disable the multicast hash, else to enable it. 673 */ gmac_enable_multicast_hash(Gmac * p_gmac,uint8_t uc_enable)674 static inline void gmac_enable_multicast_hash( Gmac * p_gmac, 675 uint8_t uc_enable ) 676 { 677 if( uc_enable ) 678 { 679 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN; 680 } 681 else 682 { 683 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_UNIHEN; 684 } 685 } 686 687 /** 688 * \brief Enable/Disable big frames (over 1518, up to 1536). 689 * 690 * \param p_gmac Pointer to the GMAC instance. 691 * \param uc_enable 0 to disable big frames else to enable it. 692 */ gmac_enable_big_frame(Gmac * p_gmac,uint8_t uc_enable)693 static inline void gmac_enable_big_frame( Gmac * p_gmac, 694 uint8_t uc_enable ) 695 { 696 if( uc_enable ) 697 { 698 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_MAXFS; 699 } 700 else 701 { 702 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_MAXFS; 703 } 704 } 705 706 /** 707 * \brief Set MDC clock divider. 708 * 709 * \param p_gmac Pointer to the GMAC instance. 710 * \param ul_mck GMAC MCK. 711 * 712 * \return GMAC_OK if successfully. 713 */ gmac_set_mdc_clock(Gmac * p_gmac,uint32_t ul_mck)714 static inline uint8_t gmac_set_mdc_clock( Gmac * p_gmac, 715 uint32_t ul_mck ) 716 { 717 uint32_t ul_clk; 718 719 if( ul_mck > GMAC_MCK_SPEED_240MHZ ) 720 { 721 return GMAC_INVALID; 722 } 723 else if( ul_mck > GMAC_MCK_SPEED_160MHZ ) 724 { 725 ul_clk = GMAC_NCFGR_CLK_MCK_96; 726 } 727 else if( ul_mck > GMAC_MCK_SPEED_120MHZ ) 728 { 729 ul_clk = GMAC_NCFGR_CLK_MCK_64; 730 } 731 else if( ul_mck > GMAC_MCK_SPEED_80MHZ ) 732 { 733 ul_clk = GMAC_NCFGR_CLK_MCK_48; 734 } 735 else if( ul_mck > GMAC_MCK_SPEED_40MHZ ) 736 { 737 ul_clk = GMAC_NCFGR_CLK_MCK_32; 738 } 739 else if( ul_mck > GMAC_MCK_SPEED_20MHZ ) 740 { 741 ul_clk = GMAC_NCFGR_CLK_MCK_16; 742 } 743 else 744 { 745 ul_clk = GMAC_NCFGR_CLK_MCK_8; 746 } 747 748 p_gmac->GMAC_NCFGR = ( p_gmac->GMAC_NCFGR & ~GMAC_NCFGR_CLK_Msk ) | ul_clk; 749 return GMAC_OK; 750 } 751 752 /** 753 * \brief Enable/Disable retry test. 754 * 755 * \param p_gmac Pointer to the GMAC instance. 756 * \param uc_enable 0 to disable the GMAC receiver, else to enable it. 757 */ gmac_enable_retry_test(Gmac * p_gmac,uint8_t uc_enable)758 static inline void gmac_enable_retry_test( Gmac * p_gmac, 759 uint8_t uc_enable ) 760 { 761 if( uc_enable ) 762 { 763 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RTY; 764 } 765 else 766 { 767 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RTY; 768 } 769 } 770 771 /** 772 * \brief Enable/Disable pause (when a valid pause frame is received). 773 * 774 * \param p_gmac Pointer to the GMAC instance. 775 * \param uc_enable 0 to disable pause frame, else to enable it. 776 */ gmac_enable_pause_frame(Gmac * p_gmac,uint8_t uc_enable)777 static inline void gmac_enable_pause_frame( Gmac * p_gmac, 778 uint8_t uc_enable ) 779 { 780 if( uc_enable ) 781 { 782 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_PEN; 783 } 784 else 785 { 786 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_PEN; 787 } 788 } 789 790 /** 791 * \brief Set receive buffer offset to 0 ~ 3. 792 * 793 * \param p_gmac Pointer to the GMAC instance. 794 */ gmac_set_rx_buffer_offset(Gmac * p_gmac,uint8_t uc_offset)795 static inline void gmac_set_rx_buffer_offset( Gmac * p_gmac, 796 uint8_t uc_offset ) 797 { 798 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RXBUFO_Msk; 799 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RXBUFO( uc_offset ); 800 } 801 802 /** 803 * \brief Enable/Disable receive length field checking. 804 * 805 * \param p_gmac Pointer to the GMAC instance. 806 * \param uc_enable 0 to disable receive length field checking, else to enable it. 807 */ gmac_enable_rx_length_check(Gmac * p_gmac,uint8_t uc_enable)808 static inline void gmac_enable_rx_length_check( Gmac * p_gmac, 809 uint8_t uc_enable ) 810 { 811 if( uc_enable ) 812 { 813 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_LFERD; 814 } 815 else 816 { 817 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_LFERD; 818 } 819 } 820 821 /** 822 * \brief Enable/Disable discarding FCS field of received frames. 823 * 824 * \param p_gmac Pointer to the GMAC instance. 825 * \param uc_enable 0 to disable discarding FCS field of received frames, else to enable it. 826 */ gmac_enable_discard_fcs(Gmac * p_gmac,uint8_t uc_enable)827 static inline void gmac_enable_discard_fcs( Gmac * p_gmac, 828 uint8_t uc_enable ) 829 { 830 if( uc_enable ) 831 { 832 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_RFCS; 833 } 834 else 835 { 836 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_RFCS; 837 } 838 } 839 840 841 /** 842 * \brief Enable/Disable frames to be received in half-duplex mode 843 * while transmitting. 844 * 845 * \param p_gmac Pointer to the GMAC instance. 846 * \param uc_enable 0 to disable the received in half-duplex mode, else to enable it. 847 */ gmac_enable_efrhd(Gmac * p_gmac,uint8_t uc_enable)848 static inline void gmac_enable_efrhd( Gmac * p_gmac, 849 uint8_t uc_enable ) 850 { 851 if( uc_enable ) 852 { 853 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_EFRHD; 854 } 855 else 856 { 857 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_EFRHD; 858 } 859 } 860 861 /** 862 * \brief Enable/Disable ignore RX FCS. 863 * 864 * \param p_gmac Pointer to the GMAC instance. 865 * \param uc_enable 0 to disable ignore RX FCS, else to enable it. 866 */ gmac_enable_ignore_rx_fcs(Gmac * p_gmac,uint8_t uc_enable)867 static inline void gmac_enable_ignore_rx_fcs( Gmac * p_gmac, 868 uint8_t uc_enable ) 869 { 870 if( uc_enable ) 871 { 872 p_gmac->GMAC_NCFGR |= GMAC_NCFGR_IRXFCS; 873 } 874 else 875 { 876 p_gmac->GMAC_NCFGR &= ~GMAC_NCFGR_IRXFCS; 877 } 878 } 879 880 /** 881 * \brief Get Network Status. 882 * 883 * \param p_gmac Pointer to the GMAC instance. 884 * 885 * \return Network status. 886 */ gmac_get_status(Gmac * p_gmac)887 static inline uint32_t gmac_get_status( Gmac * p_gmac ) 888 { 889 return p_gmac->GMAC_NSR; 890 } 891 892 /** 893 * \brief Get MDIO IN pin status. 894 * 895 * \param p_gmac Pointer to the GMAC instance. 896 * 897 * \return MDIO IN pin status. 898 */ gmac_get_MDIO(Gmac * p_gmac)899 static inline uint8_t gmac_get_MDIO( Gmac * p_gmac ) 900 { 901 return( ( p_gmac->GMAC_NSR & GMAC_NSR_MDIO ) > 0 ); 902 } 903 904 /** 905 * \brief Check if PHY is idle. 906 * 907 * \param p_gmac Pointer to the GMAC instance. 908 * 909 * \return 1 if PHY is idle. 910 */ gmac_is_phy_idle(Gmac * p_gmac)911 static inline uint8_t gmac_is_phy_idle( Gmac * p_gmac ) 912 { 913 return( ( p_gmac->GMAC_NSR & GMAC_NSR_IDLE ) > 0 ); 914 } 915 916 /** 917 * \brief Return transmit status. 918 * 919 * \param p_gmac Pointer to the GMAC instance. 920 * 921 * \return Transmit status. 922 */ gmac_get_tx_status(Gmac * p_gmac)923 static inline uint32_t gmac_get_tx_status( Gmac * p_gmac ) 924 { 925 return p_gmac->GMAC_TSR; 926 } 927 928 /** 929 * \brief Clear transmit status. 930 * 931 * \param p_gmac Pointer to the GMAC instance. 932 * \param ul_status Transmit status. 933 */ gmac_clear_tx_status(Gmac * p_gmac,uint32_t ul_status)934 static inline void gmac_clear_tx_status( Gmac * p_gmac, 935 uint32_t ul_status ) 936 { 937 p_gmac->GMAC_TSR = ul_status; 938 } 939 940 /** 941 * \brief Return receive status. 942 * 943 * \param p_gmac Pointer to the GMAC instance. 944 */ gmac_get_rx_status(Gmac * p_gmac)945 static inline uint32_t gmac_get_rx_status( Gmac * p_gmac ) 946 { 947 return p_gmac->GMAC_RSR; 948 } 949 950 /** 951 * \brief Clear receive status. 952 * 953 * \param p_gmac Pointer to the GMAC instance. 954 * \param ul_status Receive status. 955 */ gmac_clear_rx_status(Gmac * p_gmac,uint32_t ul_status)956 static inline void gmac_clear_rx_status( Gmac * p_gmac, 957 uint32_t ul_status ) 958 { 959 p_gmac->GMAC_RSR = ul_status; 960 } 961 962 /** 963 * \brief Set Rx Queue. 964 * 965 * \param p_gmac Pointer to the GMAC instance. 966 * \param ul_addr Rx queue address. 967 */ gmac_set_rx_queue(Gmac * p_gmac,uint32_t ul_addr)968 static inline void gmac_set_rx_queue( Gmac * p_gmac, 969 uint32_t ul_addr ) 970 { 971 p_gmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & ul_addr; 972 } 973 974 /** 975 * \brief Get Rx Queue Address. 976 * 977 * \param p_gmac Pointer to the GMAC instance. 978 * 979 * \return Rx queue address. 980 */ gmac_get_rx_queue(Gmac * p_gmac)981 static inline uint32_t gmac_get_rx_queue( Gmac * p_gmac ) 982 { 983 return p_gmac->GMAC_RBQB; 984 } 985 986 /** 987 * \brief Set Tx Queue. 988 * 989 * \param p_gmac Pointer to the GMAC instance. 990 * \param ul_addr Tx queue address. 991 */ gmac_set_tx_queue(Gmac * p_gmac,uint32_t ul_addr)992 static inline void gmac_set_tx_queue( Gmac * p_gmac, 993 uint32_t ul_addr ) 994 { 995 p_gmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & ul_addr; 996 } 997 998 /** 999 * \brief Get Tx Queue. 1000 * 1001 * \param p_gmac Pointer to the GMAC instance. 1002 * 1003 * \return Rx queue address. 1004 */ gmac_get_tx_queue(Gmac * p_gmac)1005 static inline uint32_t gmac_get_tx_queue( Gmac * p_gmac ) 1006 { 1007 return p_gmac->GMAC_TBQB; 1008 } 1009 1010 /** 1011 * \brief Enable interrupt(s). 1012 * 1013 * \param p_gmac Pointer to the GMAC instance. 1014 * \param ul_source Interrupt source(s) to be enabled. 1015 */ gmac_enable_interrupt(Gmac * p_gmac,uint32_t ul_source)1016 static inline void gmac_enable_interrupt( Gmac * p_gmac, 1017 uint32_t ul_source ) 1018 { 1019 p_gmac->GMAC_IER = ul_source; 1020 } 1021 1022 /** 1023 * \brief Disable interrupt(s). 1024 * 1025 * \param p_gmac Pointer to the GMAC instance. 1026 * \param ul_source Interrupt source(s) to be disabled. 1027 */ gmac_disable_interrupt(Gmac * p_gmac,uint32_t ul_source)1028 static inline void gmac_disable_interrupt( Gmac * p_gmac, 1029 uint32_t ul_source ) 1030 { 1031 p_gmac->GMAC_IDR = ul_source; 1032 } 1033 1034 /** 1035 * \brief Return interrupt status. 1036 * 1037 * \param p_gmac Pointer to the GMAC instance. 1038 * 1039 * \return Interrupt status. 1040 */ gmac_get_interrupt_status(Gmac * p_gmac)1041 static inline uint32_t gmac_get_interrupt_status( Gmac * p_gmac ) 1042 { 1043 return p_gmac->GMAC_ISR; 1044 } 1045 1046 /** 1047 * \brief Return interrupt mask. 1048 * 1049 * \param p_gmac Pointer to the GMAC instance. 1050 * 1051 * \return Interrupt mask. 1052 */ gmac_get_interrupt_mask(Gmac * p_gmac)1053 static inline uint32_t gmac_get_interrupt_mask( Gmac * p_gmac ) 1054 { 1055 return p_gmac->GMAC_IMR; 1056 } 1057 1058 /** 1059 * \brief Execute PHY maintenance command. 1060 * 1061 * \param p_gmac Pointer to the GMAC instance. 1062 * \param uc_phy_addr PHY address. 1063 * \param uc_reg_addr Register address. 1064 * \param uc_rw 1 to Read, 0 to write. 1065 * \param us_data Data to be performed, write only. 1066 */ gmac_maintain_phy(Gmac * p_gmac,uint8_t uc_phy_addr,uint8_t uc_reg_addr,uint8_t uc_rw,uint16_t us_data)1067 static inline void gmac_maintain_phy( Gmac * p_gmac, 1068 uint8_t uc_phy_addr, 1069 uint8_t uc_reg_addr, 1070 uint8_t uc_rw, 1071 uint16_t us_data ) 1072 { 1073 /* Wait until bus idle */ 1074 while( ( p_gmac->GMAC_NSR & GMAC_NSR_IDLE ) == 0 ) 1075 { 1076 } 1077 1078 /* Write maintain register */ 1079 p_gmac->GMAC_MAN = GMAC_MAN_WTN( GMAC_MAN_CODE_VALUE ) 1080 | GMAC_MAN_CLTTO 1081 | GMAC_MAN_PHYA( uc_phy_addr ) 1082 | GMAC_MAN_REGA( uc_reg_addr ) 1083 | GMAC_MAN_OP( ( uc_rw ? GMAC_MAN_RW_TYPE : GMAC_MAN_READ_ONLY ) ) 1084 | GMAC_MAN_DATA( us_data ); 1085 } 1086 1087 /** 1088 * \brief Get PHY maintenance data returned. 1089 * 1090 * \param p_gmac Pointer to the GMAC instance. 1091 * 1092 * \return Get PHY data. 1093 */ gmac_get_phy_data(Gmac * p_gmac)1094 static inline uint16_t gmac_get_phy_data( Gmac * p_gmac ) 1095 { 1096 /* Wait until bus idle */ 1097 while( ( p_gmac->GMAC_NSR & GMAC_NSR_IDLE ) == 0 ) 1098 { 1099 } 1100 1101 /* Return data */ 1102 return ( uint16_t ) ( p_gmac->GMAC_MAN & GMAC_MAN_DATA_Msk ); 1103 } 1104 1105 /** 1106 * \brief Set Hash. 1107 * 1108 * \param p_gmac Pointer to the GMAC instance. 1109 * \param ul_hash_top Hash top. 1110 * \param ul_hash_bottom Hash bottom. 1111 */ gmac_set_hash(Gmac * p_gmac,uint32_t ul_hash_top,uint32_t ul_hash_bottom)1112 static inline void gmac_set_hash( Gmac * p_gmac, 1113 uint32_t ul_hash_top, 1114 uint32_t ul_hash_bottom ) 1115 { 1116 p_gmac->GMAC_HRB = ul_hash_bottom; 1117 p_gmac->GMAC_HRT = ul_hash_top; 1118 } 1119 1120 /** 1121 * \brief Set 64 bits Hash. 1122 * 1123 * \param p_gmac Pointer to the GMAC instance. 1124 * \param ull_hash 64 bits hash value. 1125 */ gmac_set_hash64(Gmac * p_gmac,uint64_t ull_hash)1126 static inline void gmac_set_hash64( Gmac * p_gmac, 1127 uint64_t ull_hash ) 1128 { 1129 p_gmac->GMAC_HRB = ( uint32_t ) ull_hash; 1130 p_gmac->GMAC_HRT = ( uint32_t ) ( ull_hash >> 32 ); 1131 } 1132 1133 /** 1134 * \brief Set MAC Address. 1135 * 1136 * \param p_gmac Pointer to the GMAC instance. 1137 * \param uc_index GMAC specific address register index. 1138 * \param p_mac_addr GMAC address. 1139 */ gmac_set_address(Gmac * p_gmac,uint8_t uc_index,uint8_t * p_mac_addr)1140 static inline void gmac_set_address( Gmac * p_gmac, 1141 uint8_t uc_index, 1142 uint8_t * p_mac_addr ) 1143 { 1144 p_gmac->GMAC_SA[ uc_index ].GMAC_SAB = ( p_mac_addr[ 3 ] << 24 ) 1145 | ( p_mac_addr[ 2 ] << 16 ) 1146 | ( p_mac_addr[ 1 ] << 8 ) 1147 | ( p_mac_addr[ 0 ] ); 1148 p_gmac->GMAC_SA[ uc_index ].GMAC_SAT = ( p_mac_addr[ 5 ] << 8 ) 1149 | ( p_mac_addr[ 4 ] ); 1150 } 1151 1152 /** 1153 * \brief Set MAC Address via 2 dword. 1154 * 1155 * \param p_gmac Pointer to the GMAC instance. 1156 * \param uc_index GMAC specific address register index. 1157 * \param ul_mac_top GMAC top address. 1158 * \param ul_mac_bottom GMAC bottom address. 1159 */ gmac_set_address32(Gmac * p_gmac,uint8_t uc_index,uint32_t ul_mac_top,uint32_t ul_mac_bottom)1160 static inline void gmac_set_address32( Gmac * p_gmac, 1161 uint8_t uc_index, 1162 uint32_t ul_mac_top, 1163 uint32_t ul_mac_bottom ) 1164 { 1165 p_gmac->GMAC_SA[ uc_index ].GMAC_SAB = ul_mac_bottom; 1166 p_gmac->GMAC_SA[ uc_index ].GMAC_SAT = ul_mac_top; 1167 } 1168 1169 /** 1170 * \brief Set MAC Address via int64. 1171 * 1172 * \param p_gmac Pointer to the GMAC instance. 1173 * \param uc_index GMAC specific address register index. 1174 * \param ull_mac 64-bit GMAC address. 1175 */ gmac_set_address64(Gmac * p_gmac,uint8_t uc_index,uint64_t ull_mac)1176 static inline void gmac_set_address64( Gmac * p_gmac, 1177 uint8_t uc_index, 1178 uint64_t ull_mac ) 1179 { 1180 p_gmac->GMAC_SA[ uc_index ].GMAC_SAB = ( uint32_t ) ull_mac; 1181 p_gmac->GMAC_SA[ uc_index ].GMAC_SAT = ( uint32_t ) ( ull_mac >> 32 ); 1182 } 1183 1184 /** 1185 * \brief Select media independent interface mode. 1186 * 1187 * \param p_gmac Pointer to the GMAC instance. 1188 * \param mode Media independent interface mode. 1189 */ gmac_select_mii_mode(Gmac * p_gmac,gmac_mii_mode_t mode)1190 static inline void gmac_select_mii_mode( Gmac * p_gmac, 1191 gmac_mii_mode_t mode ) 1192 { 1193 switch( mode ) 1194 { 1195 case GMAC_PHY_MII: 1196 case GMAC_PHY_RMII: 1197 p_gmac->GMAC_UR |= GMAC_UR_RMIIMII; 1198 break; 1199 1200 default: 1201 p_gmac->GMAC_UR &= ~GMAC_UR_RMIIMII; 1202 break; 1203 } 1204 } 1205 1206 uint8_t gmac_phy_read( Gmac * p_gmac, 1207 uint8_t uc_phy_address, 1208 uint8_t uc_address, 1209 uint32_t * p_value ); 1210 uint8_t gmac_phy_write( Gmac * p_gmac, 1211 uint8_t uc_phy_address, 1212 uint8_t uc_address, 1213 uint32_t ul_value ); 1214 void gmac_dev_init( Gmac * p_gmac, 1215 gmac_device_t * p_gmac_dev, 1216 gmac_options_t * p_opt ); 1217 uint32_t gmac_dev_read( gmac_device_t * p_gmac_dev, 1218 uint8_t * p_frame, 1219 uint32_t ul_frame_size, 1220 uint32_t * p_rcv_size ); 1221 uint32_t gmac_dev_write( gmac_device_t * p_gmac_dev, 1222 void * p_buffer, 1223 uint32_t ul_size, 1224 gmac_dev_tx_cb_t func_tx_cb ); 1225 uint32_t gmac_dev_get_tx_load( gmac_device_t * p_gmac_dev ); 1226 void gmac_dev_set_rx_callback( gmac_device_t * p_gmac_dev, 1227 gmac_dev_rx_cb_t func_rx_cb ); 1228 uint8_t gmac_dev_set_tx_wakeup_callback( gmac_device_t * p_gmac_dev, 1229 gmac_dev_wakeup_cb_t func_wakeup, 1230 uint8_t uc_threshold ); 1231 void gmac_dev_reset( gmac_device_t * p_gmac_dev ); 1232 void gmac_handler( gmac_device_t * p_gmac_dev ); 1233 1234 /*/ @cond 0 */ 1235 /**INDENT-OFF**/ 1236 #ifdef __cplusplus 1237 } 1238 #endif 1239 /**INDENT-ON**/ 1240 /*/ @endcond */ 1241 1242 /** 1243 * \page gmac_quickstart Quickstart guide for GMAC driver. 1244 * 1245 * This is the quickstart guide for the \ref gmac_group "Ethernet MAC", 1246 * with step-by-step instructions on how to configure and use the driver in a 1247 * selection of use cases. 1248 * 1249 * The use cases contain several code fragments. The code fragments in the 1250 * steps for setup can be copied into a custom initialization function, while 1251 * the steps for usage can be copied into, e.g., the main application function. 1252 * 1253 * \section gmac_basic_use_case Basic use case 1254 * In the basic use case, the GMAC driver are configured for: 1255 * - PHY component KSZ8051MNL is used 1256 * - GMAC uses MII mode 1257 * - The number of receive buffer is 16 1258 * - The number of transfer buffer is 8 1259 * - MAC address is set to 00-04-25-1c-a0-02 1260 * - IP address is set to 192.168.0.2 1261 * - IP address is set to 192.168.0.2 1262 * - Gateway is set to 192.168.0.1 1263 * - Network mask is 255.255.255.0 1264 * - PHY operation max retry count is 1000000 1265 * - GMAC is configured to not support copy all frame and support broadcast 1266 * - The data will be read from the ethernet 1267 * 1268 * \section gmac_basic_use_case_setup Setup steps 1269 * 1270 * \subsection gmac_basic_use_case_setup_prereq Prerequisites 1271 * -# \ref sysclk_group "System Clock Management (sysclock)" 1272 * -# \ref pmc_group "Power Management Controller (pmc)" 1273 * -# \ref ksz8051mnl_ethernet_phy_group "PHY component (KSZ8051MNL)" 1274 * 1275 * \subsection gmac_basic_use_case_setup_code Example code 1276 * Content of conf_eth.h 1277 * \code 1278 * #define GMAC_RX_BUFFERS 16 1279 * #define GMAC_TX_BUFFERS 8 1280 * #define MAC_PHY_RETRY_MAX 1000000 1281 * #define ETHERNET_CONF_ETHADDR0 0x00 1282 * #define ETHERNET_CONF_ETHADDR0 0x00 1283 * #define ETHERNET_CONF_ETHADDR1 0x04 1284 * #define ETHERNET_CONF_ETHADDR2 0x25 1285 * #define ETHERNET_CONF_ETHADDR3 0x1C 1286 * #define ETHERNET_CONF_ETHADDR4 0xA0 1287 * #define ETHERNET_CONF_ETHADDR5 0x02 1288 * #define ETHERNET_CONF_IPADDR0 192 1289 * #define ETHERNET_CONF_IPADDR1 168 1290 * #define ETHERNET_CONF_IPADDR2 0 1291 * #define ETHERNET_CONF_IPADDR3 2 1292 * #define ETHERNET_CONF_GATEWAY_ADDR0 192 1293 * #define ETHERNET_CONF_GATEWAY_ADDR1 168 1294 * #define ETHERNET_CONF_GATEWAY_ADDR2 0 1295 * #define ETHERNET_CONF_GATEWAY_ADDR3 1 1296 * #define ETHERNET_CONF_NET_MASK0 255 1297 * #define ETHERNET_CONF_NET_MASK1 255 1298 * #define ETHERNET_CONF_NET_MASK2 255 1299 * #define ETHERNET_CONF_NET_MASK3 0 1300 * #define ETH_PHY_MODE ETH_PHY_MODE 1301 * \endcode 1302 * 1303 * A specific gmac device and the receive data buffer must be defined; another ul_frm_size should be defined 1304 * to trace the actual size of the data received. 1305 * \code 1306 * static gmac_device_t gs_gmac_dev; 1307 * static volatile uint8_t gs_uc_eth_buffer[GMAC_FRAME_LENTGH_MAX]; 1308 * 1309 * uint32_t ul_frm_size; 1310 * \endcode 1311 * 1312 * Add to application C-file: 1313 * \code 1314 * void gmac_init(void) 1315 * { 1316 * sysclk_init(); 1317 * 1318 * board_init(); 1319 * 1320 * pmc_enable_periph_clk(ID_GMAC); 1321 * 1322 * gmac_option.uc_copy_all_frame = 0; 1323 * gmac_option.uc_no_boardcast = 0; 1324 * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); 1325 * gs_gmac_dev.p_hw = GMAC; 1326 * 1327 * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option); 1328 * 1329 * NVIC_EnableIRQ(GMAC_IRQn); 1330 * 1331 * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz()); 1332 * 1333 * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR); 1334 * 1335 * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1); 1336 * \endcode 1337 * 1338 * \subsection gmac_basic_use_case_setup_flow Workflow 1339 * - Ensure that conf_eth.h is present and contains the 1340 * following configuration symbol. This configuration file is used 1341 * by the driver and should not be included by the application. 1342 * -# Define the receiving buffer size used in the internal GMAC driver. 1343 * The buffer size used for RX is GMAC_RX_BUFFERS * 128. 1344 * If it was supposed receiving a large number of frame, the 1345 * GMAC_RX_BUFFERS should be set higher. E.g., the application wants to accept 1346 * a ping echo test of 2048, the GMAC_RX_BUFFERS should be set at least 1347 * (2048/128)=16, and as there are additional frames coming, a preferred 1348 * number is 24 depending on a normal Ethernet throughput. 1349 * - \code 1350 * #define GMAC_RX_BUFFERS 16 1351 * \endcode 1352 * -# Define the transmitting buffer size used in the internal GMAC driver. 1353 * The buffer size used for TX is GMAC_TX_BUFFERS * 1518. 1354 * - \code 1355 * #define GMAC_TX_BUFFERS 8 1356 * \endcode 1357 * -# Define maximum retry time for a PHY read/write operation. 1358 * - \code 1359 * #define MAC_PHY_RETRY_MAX 1000000 1360 * \endcode 1361 * -# Define the MAC address. 00:04:25:1C:A0:02 is the address reserved 1362 * for ATMEL, application should always change this address to its' own. 1363 * - \code 1364 * #define ETHERNET_CONF_ETHADDR0 0x00 1365 * #define ETHERNET_CONF_ETHADDR1 0x04 1366 * #define ETHERNET_CONF_ETHADDR2 0x25 1367 * #define ETHERNET_CONF_ETHADDR3 0x1C 1368 * #define ETHERNET_CONF_ETHADDR4 0xA0 1369 * #define ETHERNET_CONF_ETHADDR5 0x02 1370 * \endcode 1371 * -# Define the IP address configration used in the application. When DHCP 1372 * is enabled, this configuration is not effected. 1373 * - \code 1374 * #define ETHERNET_CONF_IPADDR0 192 1375 * #define ETHERNET_CONF_IPADDR1 168 1376 * #define ETHERNET_CONF_IPADDR2 0 1377 * #define ETHERNET_CONF_IPADDR3 2 1378 * #define ETHERNET_CONF_GATEWAY_ADDR0 192 1379 * #define ETHERNET_CONF_GATEWAY_ADDR1 168 1380 * #define ETHERNET_CONF_GATEWAY_ADDR2 0 1381 * #define ETHERNET_CONF_GATEWAY_ADDR3 1 1382 * #define ETHERNET_CONF_NET_MASK0 255 1383 * #define ETHERNET_CONF_NET_MASK1 255 1384 * #define ETHERNET_CONF_NET_MASK2 255 1385 * #define ETHERNET_CONF_NET_MASK3 0 1386 * \endcode 1387 * -# Configure the PHY maintenance interface. 1388 * - \code 1389 * #define ETH_PHY_MODE GMAC_PHY_MII 1390 * \endcode 1391 * -# Enable the system clock: 1392 * - \code sysclk_init(); \endcode 1393 * -# Enable PIO configurations for GMAC: 1394 * - \code board_init(); \endcode 1395 * -# Enable PMC clock for GMAC: 1396 * - \code pmc_enable_periph_clk(ID_GMAC); \endcode 1397 * -# Set the GMAC options; it's set to copy all frame and support broadcast: 1398 * - \code 1399 * gmac_option.uc_copy_all_frame = 0; 1400 * gmac_option.uc_no_boardcast = 0; 1401 * memcpy(gmac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); 1402 * gs_gmac_dev.p_hw = GMAC; 1403 * \endcode 1404 * -# Initialize GMAC device with the filled option: 1405 * - \code 1406 * gmac_dev_init(GMAC, &gs_gmac_dev, &gmac_option); 1407 * \endcode 1408 * -# Enable the interrupt service for GMAC: 1409 * - \code 1410 * NVIC_EnableIRQ(GMAC_IRQn); 1411 * \endcode 1412 * -# Initialize the PHY component: 1413 * - \code 1414 * ethernet_phy_init(GMAC, BOARD_GMAC_PHY_ADDR, sysclk_get_cpu_hz()); 1415 * \endcode 1416 * -# The link will be established based on auto negotiation. 1417 * - \code 1418 * ethernet_phy_auto_negotiate(GMAC, BOARD_GMAC_PHY_ADDR); 1419 * \endcode 1420 * -# Establish the ethernet link; the network can be worked from now on: 1421 * - \code 1422 * ethernet_phy_set_link(GMAC, BOARD_GMAC_PHY_ADDR, 1); 1423 * \endcode 1424 * 1425 * \section gmac_basic_use_case_usage Usage steps 1426 * \subsection gmac_basic_use_case_usage_code Example code 1427 * Add to, e.g., main loop in application C-file: 1428 * \code 1429 * gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); 1430 * \endcode 1431 * 1432 * \subsection gmac_basic_use_case_usage_flow Workflow 1433 * -# Start reading the data from the ethernet: 1434 * - \code gmac_dev_read(&gs_gmac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); \endcode 1435 */ 1436 1437 #define GMAC_STATS 0 1438 1439 #if ( GMAC_STATS != 0 ) 1440 1441 /* Here below some code to study the types and 1442 * frequencies of GMAC interrupts. */ 1443 #define GMAC_IDX_RXUBR 0 1444 #define GMAC_IDX_TUR 1 1445 #define GMAC_IDX_RLEX 2 1446 #define GMAC_IDX_TFC 3 1447 #define GMAC_IDX_RCOMP 4 1448 #define GMAC_IDX_TCOMP 5 1449 #define GMAC_IDX_ROVR 6 1450 #define GMAC_IDX_HRESP 7 1451 #define GMAC_IDX_PFNZ 8 1452 #define GMAC_IDX_PTZ 9 1453 1454 struct SGmacStats 1455 { 1456 unsigned recvCount; 1457 unsigned rovrCount; 1458 unsigned bnaCount; 1459 unsigned sendCount; 1460 unsigned sovrCount; 1461 unsigned incompCount; 1462 unsigned truncCount; 1463 1464 unsigned intStatus[ 10 ]; 1465 }; 1466 extern struct SGmacStats gmacStats; 1467 1468 struct SIntPair 1469 { 1470 const char * name; 1471 unsigned mask; 1472 int index; 1473 }; 1474 1475 #define MK_PAIR( NAME ) # NAME, GMAC_IER_ ## NAME, GMAC_IDX_ ## NAME 1476 static const struct SIntPair intPairs[] = 1477 { 1478 { MK_PAIR( RXUBR ) }, /* Enable receive used bit read interrupt. */ 1479 { MK_PAIR( TUR ) }, /* Enable transmit underrun interrupt. */ 1480 { MK_PAIR( RLEX ) }, /* Enable retry limit exceeded interrupt. */ 1481 { MK_PAIR( TFC ) }, /* Enable transmit buffers exhausted in mid-frame interrupt. */ 1482 { MK_PAIR( RCOMP ) }, /* Receive complete */ 1483 { MK_PAIR( TCOMP ) }, /* Enable transmit complete interrupt. */ 1484 { MK_PAIR( ROVR ) }, /* Enable receive overrun interrupt. */ 1485 { MK_PAIR( HRESP ) }, /* Enable Hresp not OK interrupt. */ 1486 { MK_PAIR( PFNZ ) }, /* Enable pause frame received interrupt. */ 1487 { MK_PAIR( PTZ ) } /* Enable pause time zero interrupt. */ 1488 }; 1489 1490 void gmac_show_irq_counts(); 1491 1492 #endif /* if ( GMAC_STATS != 0 ) */ 1493 1494 #endif /* GMAC_H_INCLUDED */ 1495
