xref: /Kernel-v10.6.2/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S (revision ef7b253b56c9788077f5ecd6c9deb4021923d646) 
1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
4 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
5 *
6 * SPDX-License-Identifier: MIT
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy of
9 * this software and associated documentation files (the "Software"), to deal in
10 * the Software without restriction, including without limitation the rights to
11 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
12 * the Software, and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in all
16 * copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
20 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
21 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
22 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * https://www.FreeRTOS.org
26 * https://github.com/FreeRTOS
27 *
28 */
29
30/*
31 * Xtensa interrupt handling data and assembly routines.
32 * Also see xtensa_intr.c and xtensa_vectors.S.
33 */
34
35#include <xtensa/hal.h>
36#include <xtensa/config/core.h>
37
38#include "xtensa_context.h"
39
40#if XCHAL_HAVE_INTERRUPTS
41
42/*
43-------------------------------------------------------------------------------
44  INTENABLE virtualization information.
45-------------------------------------------------------------------------------
46*/
47
48    .data
49    .global _xt_intdata
50    .align  8
51_xt_intdata:
52    .global _xt_intenable
53    .type   _xt_intenable,@object
54    .size   _xt_intenable,4
55    .global _xt_vpri_mask
56    .type   _xt_vpri_mask,@object
57    .size   _xt_vpri_mask,4
58
59_xt_intenable:     .word   0             /* Virtual INTENABLE     */
60_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
61
62
63/*
64-------------------------------------------------------------------------------
65  Table of C-callable interrupt handlers for each interrupt. Note that not all
66  slots can be filled, because interrupts at level > EXCM_LEVEL will not be
67  dispatched to a C handler by default.
68-------------------------------------------------------------------------------
69*/
70
71    .data
72    .global _xt_interrupt_table
73    .align  8
74
75_xt_interrupt_table:
76
77    .set    i, 0
78    .rept   XCHAL_NUM_INTERRUPTS
79    .word   xt_unhandled_interrupt      /* handler address               */
80    .word   i                           /* handler arg (default: intnum) */
81    .set    i, i+1
82    .endr
83
84#endif /* XCHAL_HAVE_INTERRUPTS */
85
86
87#if XCHAL_HAVE_EXCEPTIONS
88
89/*
90-------------------------------------------------------------------------------
91  Table of C-callable exception handlers for each exception. Note that not all
92  slots will be active, because some exceptions (e.g. coprocessor exceptions)
93  are always handled by the OS and cannot be hooked by user handlers.
94-------------------------------------------------------------------------------
95*/
96
97    .data
98    .global _xt_exception_table
99    .align  4
100
101_xt_exception_table:
102    .rept   XCHAL_EXCCAUSE_NUM
103    .word   xt_unhandled_exception    /* handler address */
104    .endr
105
106#endif
107
108
109/*
110-------------------------------------------------------------------------------
111  unsigned int xt_ints_on ( unsigned int mask )
112
113  Enables a set of interrupts. Does not simply set INTENABLE directly, but
114  computes it as a function of the current virtual priority.
115  Can be called from interrupt handlers.
116-------------------------------------------------------------------------------
117*/
118
119    .text
120    .align  4
121    .global xt_ints_on
122    .type   xt_ints_on,@function
123
124xt_ints_on:
125
126    ENTRY0
127#if XCHAL_HAVE_INTERRUPTS
128    movi    a3, 0
129    movi    a4, _xt_intdata
130    xsr     a3, INTENABLE        /* Disables all interrupts   */
131    rsync
132    l32i    a3, a4, 0            /* a3 = _xt_intenable        */
133    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask        */
134    or      a5, a3, a2           /* a5 = _xt_intenable | mask */
135    s32i    a5, a4, 0            /* _xt_intenable |= mask     */
136    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
137    wsr     a5, INTENABLE        /* Reenable interrupts       */
138    mov     a2, a3               /* Previous mask             */
139#else
140    movi    a2, 0                /* Return zero */
141#endif
142    RET0
143
144    .size   xt_ints_on, . - xt_ints_on
145
146
147/*
148-------------------------------------------------------------------------------
149  unsigned int xt_ints_off ( unsigned int mask )
150
151  Disables a set of interrupts. Does not simply set INTENABLE directly,
152  but computes it as a function of the current virtual priority.
153  Can be called from interrupt handlers.
154-------------------------------------------------------------------------------
155*/
156
157    .text
158    .align  4
159    .global xt_ints_off
160    .type   xt_ints_off,@function
161
162xt_ints_off:
163
164    ENTRY0
165#if XCHAL_HAVE_INTERRUPTS
166    movi    a3, 0
167    movi    a4, _xt_intdata
168    xsr     a3, INTENABLE        /* Disables all interrupts    */
169    rsync
170    l32i    a3, a4, 0            /* a3 = _xt_intenable         */
171    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask         */
172    or      a5, a3, a2           /* a5 = _xt_intenable | mask  */
173    xor     a5, a5, a2           /* a5 = _xt_intenable & ~mask */
174    s32i    a5, a4, 0            /* _xt_intenable &= ~mask     */
175    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
176    wsr     a5, INTENABLE        /* Reenable interrupts        */
177    mov     a2, a3               /* Previous mask              */
178#else
179    movi    a2, 0                /* return zero */
180#endif
181    RET0
182
183    .size   xt_ints_off, . - xt_ints_off
184