1/* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "xtensa_rtos.h" 8#include "esp_idf_version.h" 9#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) 10#include "esp_panic.h" 11#else 12#include "esp_private/panic_reason.h" 13#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ 14#include "sdkconfig.h" 15#include "soc/soc.h" 16 17/* 18This file contains the default handlers for the high interrupt levels as well as some specialized exceptions. 19The default behaviour is to just exit the interrupt or call the panic handler on the exceptions 20*/ 21 22 23#if XCHAL_HAVE_DEBUG 24 .global xt_debugexception 25 .weak xt_debugexception 26 .set xt_debugexception, _xt_debugexception 27 .section .iram1,"ax" 28 .type _xt_debugexception,@function 29 .align 4 30 31_xt_debugexception: 32#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) 33#define XT_DEBUGCAUSE_DI (5) 34 getcoreid a0 35#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM) 36 beqz a0, 1f 37#else 38 bnez a0, 1f 39#endif 40 41 rsr a0, DEBUGCAUSE 42 extui a0, a0, XT_DEBUGCAUSE_DI, 1 43 bnez a0, _xt_debug_di_exc 441: 45#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) 46 47 movi a0,PANIC_RSN_DEBUGEXCEPTION 48 wsr a0,EXCCAUSE 49 /* _xt_panic assumes a level 1 exception. As we're 50 crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL 51 to level 1. */ 52 rsr a0,(EPC + XCHAL_DEBUGLEVEL) 53 wsr a0,EPC_1 54 rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL) 55 wsr a0,EXCSAVE_1 56 call0 _xt_panic /* does not return */ 57 rfi XCHAL_DEBUGLEVEL 58 59#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) 60 .align 4 61_xt_debug_di_exc: 62 63 /* 64 The delay time can be calculated by the following formula: 65 T = ceil(0.25 + max(t1, t2)) us 66 67 t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2 68 69 f1: PSRAM access frequency, unit: MHz. 70 f2: Flash access frequency, unit: MHz. 71 72 When flash is slow/fast read, N = 1. 73 When flash is DOUT/DIO read, N = 2. 74 When flash is QOUT/QIO read, N = 4. 75 76 And after testing, when CPU frequency is 240 MHz, it will take 1us to loop 27 times. 77 */ 78#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT) 79 80# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) 81 movi a0, 54 82# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) 83 movi a0, 81 84# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) 85 movi a0, 81 86# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) 87 movi a0, 108 88# else 89 movi a0, 135 90# endif 91 92#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT) 93 94# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) 95 movi a0, 81 96# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) 97 movi a0, 81 98# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) 99 movi a0, 135 100# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) 101 movi a0, 189 102# else 103 movi a0, 243 104# endif 105 106#else 107 movi a0, 243 108#endif 109 1101: addi a0, a0, -1 /* delay_us(N) */ 111 .rept 4 112 nop 113 .endr 114 bnez a0, 1b 115 116 rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL 117 rfi XCHAL_DEBUGLEVEL 118#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) 119#endif /* Debug exception */ 120 121 122#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 123 .global xt_highint2 124 .weak xt_highint2 125 .set xt_highint2, _xt_highint2 126 .section .iram1,"ax" 127 .type _xt_highint2,@function 128 .align 4 129_xt_highint2: 130 131 /* Default handler does nothing; just returns */ 132 .align 4 133.L_xt_highint2_exit: 134 rsr a0, EXCSAVE_2 /* restore a0 */ 135 rfi 2 136 137#endif /* Level 2 */ 138 139#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 140 141 .global xt_highint3 142 .weak xt_highint3 143 .set xt_highint3, _xt_highint3 144 .section .iram1,"ax" 145 .type _xt_highint3,@function 146 .align 4 147_xt_highint3: 148 149 /* Default handler does nothing; just returns */ 150 151 .align 4 152.L_xt_highint3_exit: 153 rsr a0, EXCSAVE_3 /* restore a0 */ 154 rfi 3 155 156#endif /* Level 3 */ 157 158#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 159 160 .global xt_highint4 161 .weak xt_highint4 162 .set xt_highint4, _xt_highint4 163 .section .iram1,"ax" 164 .type _xt_highint4,@function 165 .align 4 166_xt_highint4: 167 168 /* Default handler does nothing; just returns */ 169 170 .align 4 171.L_xt_highint4_exit: 172 rsr a0, EXCSAVE_4 /* restore a0 */ 173 rfi 4 174 175#endif /* Level 4 */ 176 177#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 178 179 .global xt_highint5 180 .weak xt_highint5 181 .set xt_highint5, _xt_highint5 182 .section .iram1,"ax" 183 .type _xt_highint5,@function 184 .align 4 185_xt_highint5: 186 187 /* Default handler does nothing; just returns */ 188 189 .align 4 190.L_xt_highint5_exit: 191 rsr a0, EXCSAVE_5 /* restore a0 */ 192 rfi 5 193 194 195#endif /* Level 5 */ 196 197#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 198 199 .global _xt_highint6 200 .global xt_highint6 201 .weak xt_highint6 202 .set xt_highint6, _xt_highint6 203 .section .iram1,"ax" 204 .type _xt_highint6,@function 205 .align 4 206_xt_highint6: 207 208 /* Default handler does nothing; just returns */ 209 210 .align 4 211.L_xt_highint6_exit: 212 rsr a0, EXCSAVE_6 /* restore a0 */ 213 rfi 6 214 215#endif /* Level 6 */ 216 217#if XCHAL_HAVE_NMI 218 219 .global _xt_nmi 220 .global xt_nmi 221 .weak xt_nmi 222 .set xt_nmi, _xt_nmi 223 .section .iram1,"ax" 224 .type _xt_nmi,@function 225 .align 4 226_xt_nmi: 227 228 /* Default handler does nothing; just returns */ 229 230 .align 4 231.L_xt_nmi_exit: 232 rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ 233 rfi XCHAL_NMILEVEL 234 235#endif /* NMI */ 236