1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the Cygnal port.
31 *----------------------------------------------------------*/
32
33 /* Standard includes. */
34 #include <string.h>
35
36 /* Scheduler includes. */
37 #include "FreeRTOS.h"
38 #include "task.h"
39
40 /* Constants required to setup timer 2 to produce the RTOS tick. */
41 #define portCLOCK_DIVISOR ( ( uint32_t ) 12 )
42 #define portMAX_TIMER_VALUE ( ( uint32_t ) 0xffff )
43 #define portENABLE_TIMER ( ( uint8_t ) 0x04 )
44 #define portTIMER_2_INTERRUPT_ENABLE ( ( uint8_t ) 0x20 )
45
46 /* The value used in the IE register when a task first starts. */
47 #define portGLOBAL_INTERRUPT_BIT ( ( StackType_t ) 0x80 )
48
49 /* The value used in the PSW register when a task first starts. */
50 #define portINITIAL_PSW ( ( StackType_t ) 0x00 )
51
52 /* Macro to clear the timer 2 interrupt flag. */
53 #define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80;
54
55 /* Used during a context switch to store the size of the stack being copied
56 to or from XRAM. */
57 data static uint8_t ucStackBytes;
58
59 /* Used during a context switch to point to the next byte in XRAM from/to which
60 a RAM byte is to be copied. */
61 xdata static StackType_t * data pxXRAMStack;
62
63 /* Used during a context switch to point to the next byte in RAM from/to which
64 an XRAM byte is to be copied. */
65 data static StackType_t * data pxRAMStack;
66
67 /* We require the address of the pxCurrentTCB variable, but don't want to know
68 any details of its type. */
69 typedef void TCB_t;
70 extern volatile TCB_t * volatile pxCurrentTCB;
71
72 /*
73 * Setup the hardware to generate an interrupt off timer 2 at the required
74 * frequency.
75 */
76 static void prvSetupTimerInterrupt( void );
77
78 /*-----------------------------------------------------------*/
79 /*
80 * Macro that copies the current stack from internal RAM to XRAM. This is
81 * required as the 8051 only contains enough internal RAM for a single stack,
82 * but we have a stack for every task.
83 */
84 #define portCOPY_STACK_TO_XRAM() \
85 { \
86 /* pxCurrentTCB points to a TCB which itself points to the location into \
87 which the first stack byte should be copied. Set pxXRAMStack to point \
88 to the location into which the first stack byte is to be copied. */ \
89 pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
90 \
91 /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \
92 pxRAMStack = ( data StackType_t * data ) configSTACK_START; \
93 \
94 /* Calculate the size of the stack we are about to copy from the current \
95 stack pointer value. */ \
96 ucStackBytes = SP - ( configSTACK_START - 1 ); \
97 \
98 /* Before starting to copy the stack, store the calculated stack size so \
99 the stack can be restored when the task is resumed. */ \
100 *pxXRAMStack = ucStackBytes; \
101 \
102 /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \
103 have already stored the stack size into XRAM. */ \
104 while( ucStackBytes ) \
105 { \
106 pxXRAMStack++; \
107 *pxXRAMStack = *pxRAMStack; \
108 pxRAMStack++; \
109 ucStackBytes--; \
110 } \
111 }
112 /*-----------------------------------------------------------*/
113
114 /*
115 * Macro that copies the stack of the task being resumed from XRAM into
116 * internal RAM.
117 */
118 #define portCOPY_XRAM_TO_STACK() \
119 { \
120 /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \
121 copy the data back out of XRAM and into the stack. */ \
122 pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \
123 pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 ); \
124 \
125 /* The first value stored in XRAM was the size of the stack - i.e. the \
126 number of bytes we need to copy back. */ \
127 ucStackBytes = pxXRAMStack[ 0 ]; \
128 \
129 /* Copy the required number of bytes back into the stack. */ \
130 do \
131 { \
132 pxXRAMStack++; \
133 pxRAMStack++; \
134 *pxRAMStack = *pxXRAMStack; \
135 ucStackBytes--; \
136 } while( ucStackBytes ); \
137 \
138 /* Restore the stack pointer ready to use the restored stack. */ \
139 SP = ( uint8_t ) pxRAMStack; \
140 }
141 /*-----------------------------------------------------------*/
142
143 /*
144 * Macro to push the current execution context onto the stack, before the stack
145 * is moved to XRAM.
146 */
147 #define portSAVE_CONTEXT() \
148 { \
149 _asm \
150 /* Push ACC first, as when restoring the context it must be restored \
151 last (it is used to set the IE register). */ \
152 push ACC \
153 /* Store the IE register then disable interrupts. */ \
154 push IE \
155 clr _EA \
156 push DPL \
157 push DPH \
158 push b \
159 push ar2 \
160 push ar3 \
161 push ar4 \
162 push ar5 \
163 push ar6 \
164 push ar7 \
165 push ar0 \
166 push ar1 \
167 push PSW \
168 _endasm; \
169 PSW = 0; \
170 _asm \
171 push _bp \
172 _endasm; \
173 }
174 /*-----------------------------------------------------------*/
175
176 /*
177 * Macro that restores the execution context from the stack. The execution
178 * context was saved into the stack before the stack was copied into XRAM.
179 */
180 #define portRESTORE_CONTEXT() \
181 { \
182 _asm \
183 pop _bp \
184 pop PSW \
185 pop ar1 \
186 pop ar0 \
187 pop ar7 \
188 pop ar6 \
189 pop ar5 \
190 pop ar4 \
191 pop ar3 \
192 pop ar2 \
193 pop b \
194 pop DPH \
195 pop DPL \
196 /* The next byte of the stack is the IE register. Only the global \
197 enable bit forms part of the task context. Pop off the IE then set \
198 the global enable bit to match that of the stored IE register. */ \
199 pop ACC \
200 JB ACC.7,0098$ \
201 CLR IE.7 \
202 LJMP 0099$ \
203 0098$: \
204 SETB IE.7 \
205 0099$: \
206 /* Finally pop off the ACC, which was the first register saved. */ \
207 pop ACC \
208 reti \
209 _endasm; \
210 }
211 /*-----------------------------------------------------------*/
212
213 /*
214 * See header file for description.
215 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)216 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
217 {
218 uint32_t ulAddress;
219 StackType_t *pxStartOfStack;
220
221 /* Leave space to write the size of the stack as the first byte. */
222 pxStartOfStack = pxTopOfStack;
223 pxTopOfStack++;
224
225 /* Place a few bytes of known values on the bottom of the stack.
226 This is just useful for debugging and can be uncommented if required.
227 *pxTopOfStack = 0x11;
228 pxTopOfStack++;
229 *pxTopOfStack = 0x22;
230 pxTopOfStack++;
231 *pxTopOfStack = 0x33;
232 pxTopOfStack++;
233 */
234
235 /* Simulate how the stack would look after a call to the scheduler tick
236 ISR.
237
238 The return address that would have been pushed by the MCU. */
239 ulAddress = ( uint32_t ) pxCode;
240 *pxTopOfStack = ( StackType_t ) ulAddress;
241 ulAddress >>= 8;
242 pxTopOfStack++;
243 *pxTopOfStack = ( StackType_t ) ( ulAddress );
244 pxTopOfStack++;
245
246 /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
247 *pxTopOfStack = 0xaa; /* acc */
248 pxTopOfStack++;
249
250 /* We want tasks to start with interrupts enabled. */
251 *pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
252 pxTopOfStack++;
253
254 /* The function parameters will be passed in the DPTR and B register as
255 a three byte generic pointer is used. */
256 ulAddress = ( uint32_t ) pvParameters;
257 *pxTopOfStack = ( StackType_t ) ulAddress; /* DPL */
258 ulAddress >>= 8;
259 *pxTopOfStack++;
260 *pxTopOfStack = ( StackType_t ) ulAddress; /* DPH */
261 ulAddress >>= 8;
262 pxTopOfStack++;
263 *pxTopOfStack = ( StackType_t ) ulAddress; /* b */
264 pxTopOfStack++;
265
266 /* The remaining registers are straight forward. */
267 *pxTopOfStack = 0x02; /* R2 */
268 pxTopOfStack++;
269 *pxTopOfStack = 0x03; /* R3 */
270 pxTopOfStack++;
271 *pxTopOfStack = 0x04; /* R4 */
272 pxTopOfStack++;
273 *pxTopOfStack = 0x05; /* R5 */
274 pxTopOfStack++;
275 *pxTopOfStack = 0x06; /* R6 */
276 pxTopOfStack++;
277 *pxTopOfStack = 0x07; /* R7 */
278 pxTopOfStack++;
279 *pxTopOfStack = 0x00; /* R0 */
280 pxTopOfStack++;
281 *pxTopOfStack = 0x01; /* R1 */
282 pxTopOfStack++;
283 *pxTopOfStack = 0x00; /* PSW */
284 pxTopOfStack++;
285 *pxTopOfStack = 0xbb; /* BP */
286
287 /* Dont increment the stack size here as we don't want to include
288 the stack size byte as part of the stack size count.
289
290 Finally we place the stack size at the beginning. */
291 *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
292
293 /* Unlike most ports, we return the start of the stack as this is where the
294 size of the stack is stored. */
295 return pxStartOfStack;
296 }
297 /*-----------------------------------------------------------*/
298
299 /*
300 * See header file for description.
301 */
xPortStartScheduler(void)302 BaseType_t xPortStartScheduler( void )
303 {
304 /* Setup timer 2 to generate the RTOS tick. */
305 prvSetupTimerInterrupt();
306
307 /* Make sure we start with the expected SFR page. This line should not
308 really be required. */
309 SFRPAGE = 0;
310
311 /* Copy the stack for the first task to execute from XRAM into the stack,
312 restore the task context from the new stack, then start running the task. */
313 portCOPY_XRAM_TO_STACK();
314 portRESTORE_CONTEXT();
315
316 /* Should never get here! */
317 return pdTRUE;
318 }
319 /*-----------------------------------------------------------*/
320
vPortEndScheduler(void)321 void vPortEndScheduler( void )
322 {
323 /* Not implemented for this port. */
324 }
325 /*-----------------------------------------------------------*/
326
327 /*
328 * Manual context switch. The first thing we do is save the registers so we
329 * can use a naked attribute.
330 */
vPortYield(void)331 void vPortYield( void ) _naked
332 {
333 /* Save the execution context onto the stack, then copy the entire stack
334 to XRAM. This is necessary as the internal RAM is only large enough to
335 hold one stack, and we want one per task.
336
337 PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
338 IS REQUIRED. */
339 portSAVE_CONTEXT();
340 portCOPY_STACK_TO_XRAM();
341
342 /* Call the standard scheduler context switch function. */
343 vTaskSwitchContext();
344
345 /* Copy the stack of the task about to execute from XRAM into RAM and
346 restore it's context ready to run on exiting. */
347 portCOPY_XRAM_TO_STACK();
348 portRESTORE_CONTEXT();
349 }
350 /*-----------------------------------------------------------*/
351
352 #if configUSE_PREEMPTION == 1
vTimer2ISR(void)353 void vTimer2ISR( void ) interrupt 5 _naked
354 {
355 /* Preemptive context switch function triggered by the timer 2 ISR.
356 This does the same as vPortYield() (see above) with the addition
357 of incrementing the RTOS tick count. */
358
359 portSAVE_CONTEXT();
360 portCOPY_STACK_TO_XRAM();
361
362 if( xTaskIncrementTick() != pdFALSE )
363 {
364 vTaskSwitchContext();
365 }
366
367 portCLEAR_INTERRUPT_FLAG();
368 portCOPY_XRAM_TO_STACK();
369 portRESTORE_CONTEXT();
370 }
371 #else
vTimer2ISR(void)372 void vTimer2ISR( void ) interrupt 5
373 {
374 /* When using the cooperative scheduler the timer 2 ISR is only
375 required to increment the RTOS tick count. */
376
377 xTaskIncrementTick();
378 portCLEAR_INTERRUPT_FLAG();
379 }
380 #endif
381 /*-----------------------------------------------------------*/
382
prvSetupTimerInterrupt(void)383 static void prvSetupTimerInterrupt( void )
384 {
385 uint8_t ucOriginalSFRPage;
386
387 /* Constants calculated to give the required timer capture values. */
388 const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
389 const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
390 const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
391 const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
392 const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
393
394 /* NOTE: This uses a timer only present on 8052 architecture. */
395
396 /* Remember the current SFR page so we can restore it at the end of the
397 function. */
398 ucOriginalSFRPage = SFRPAGE;
399 SFRPAGE = 0;
400
401 /* TMR2CF can be left in its default state. */
402 TMR2CF = ( uint8_t ) 0;
403
404 /* Setup the overflow reload value. */
405 RCAP2L = ucLowCaptureByte;
406 RCAP2H = ucHighCaptureByte;
407
408 /* The initial load is performed manually. */
409 TMR2L = ucLowCaptureByte;
410 TMR2H = ucHighCaptureByte;
411
412 /* Enable the timer 2 interrupts. */
413 IE |= portTIMER_2_INTERRUPT_ENABLE;
414
415 /* Interrupts are disabled when this is called so the timer can be started
416 here. */
417 TMR2CN = portENABLE_TIMER;
418
419 /* Restore the original SFR page. */
420 SFRPAGE = ucOriginalSFRPage;
421 }
422
