1/*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29/*
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
33 *
34 * + The code that is common to all RISC-V chips is implemented in
35 *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
36 *   portASM.S file because the same file is used no matter which RISC-V chip is
37 *   in use.
38 *
39 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
40 *   chip is implemented in freertos_risc_v_chip_specific_extensions.h.  There
41 *   is one freertos_risc_v_chip_specific_extensions.h that can be used with any
42 *   RISC-V chip that both includes a standard CLINT and does not add to the
43 *   base set of RISC-V registers.  There are additional
44 *   freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
45 *   that do not include a standard CLINT or do add to the base set of RISC-V
46 *   registers.
47 *
48 * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
49 * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
50 * IN USE.  To include the correct freertos_risc_v_chip_specific_extensions.h
51 * header file ensure the path to the correct header file is in the assembler's
52 * include path.
53 *
54 * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
55 * that include a standard CLINT and do not add to the base set of RISC-V
56 * registers.
57 *
58 */
59
60#include "portContext.h"
61
62/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
63definitions. */
64#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
65    #error The portasmHAS_CLINT constant has been deprecated.  Please replace it with portasmHAS_MTIME.  portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
66#endif
67
68#ifdef portasmHAS_CLINT
69    #warning The portasmHAS_CLINT constant has been deprecated.  Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT.  For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
70    #define portasmHAS_MTIME portasmHAS_CLINT
71    #define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
72#endif
73
74#ifndef portasmHAS_MTIME
75    #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present).  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
76#endif
77
78#ifndef portasmHAS_SIFIVE_CLINT
79    #define portasmHAS_SIFIVE_CLINT 0
80#endif
81
82/* CSR definitions. */
83#define CSR_MSTATUS         0x300
84#define CSR_MTVEC           0x305
85#define CSR_MEPC            0x341
86#define CSR_MCAUSE          0x342
87
88    PUBLIC xPortStartFirstTask
89    PUBLIC pxPortInitialiseStack
90    PUBLIC freertos_risc_v_trap_handler
91    PUBLIC freertos_risc_v_exception_handler
92    PUBLIC freertos_risc_v_interrupt_handler
93    PUBLIC freertos_risc_v_mtimer_interrupt_handler
94
95    EXTERN vTaskSwitchContext
96    EXTERN xTaskIncrementTick
97    EXTERN pullMachineTimerCompareRegister
98    EXTERN pullNextTime
99    EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
100    EXTERN xTaskReturnAddress
101
102    PUBWEAK freertos_risc_v_application_exception_handler
103    PUBWEAK freertos_risc_v_application_interrupt_handler
104/*-----------------------------------------------------------*/
105
106    SECTION `.text`:CODE:NOROOT(2)
107    CODE
108
109portUPDATE_MTIMER_COMPARE_REGISTER MACRO
110    load_x a0, pullMachineTimerCompareRegister  /* Load address of compare register into a0. */
111    load_x a1, pullNextTime                     /* Load the address of ullNextTime into a1. */
112
113    #if( __riscv_xlen == 32 )
114
115        /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
116        li a4, -1
117        lw a2, 0(a1)                /* Load the low word of ullNextTime into a2. */
118        lw a3, 4(a1)                /* Load the high word of ullNextTime into a3. */
119        sw a4, 0(a0)                /* Low word no smaller than old value to start with - will be overwritten below. */
120        sw a3, 4(a0)                /* Store high word of ullNextTime into compare register.  No smaller than new value. */
121        sw a2, 0(a0)                /* Store low word of ullNextTime into compare register. */
122        lw t0, uxTimerIncrementsForOneTick  /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
123        add a4, t0, a2              /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
124        sltu t1, a4, a2             /* See if the sum of low words overflowed (what about the zero case?). */
125        add t2, a3, t1              /* Add overflow to high word of ullNextTime. */
126        sw a4, 0(a1)                /* Store new low word of ullNextTime. */
127        sw t2, 4(a1)                /* Store new high word of ullNextTime. */
128
129    #endif /* __riscv_xlen == 32 */
130
131    #if( __riscv_xlen == 64 )
132
133        /* Update the 64-bit mtimer compare match value. */
134        ld t2, 0(a1)                /* Load ullNextTime into t2. */
135        sd t2, 0(a0)                /* Store ullNextTime into compare register. */
136        ld t0, uxTimerIncrementsForOneTick  /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
137        add t4, t0, t2              /* Add ullNextTime to the timer increments for one tick. */
138        sd t4, 0(a1)                /* Store ullNextTime. */
139
140    #endif /* __riscv_xlen == 64 */
141    ENDM
142/*-----------------------------------------------------------*/
143
144/*
145 * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
146 * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant.  The prototype
147 * for the function is as per the other ports:
148 * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
149 *
150 * As per the standard RISC-V ABI pxTopOfStack is passed in in a0, pxCode in
151 * a1, and pvParameters in a2.  The new top of stack is passed out in a0.
152 *
153 * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
154 * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
155 *
156 * Register      ABI Name    Description                       Saver
157 * x0            zero        Hard-wired zero                   -
158 * x1            ra          Return address                    Caller
159 * x2            sp          Stack pointer                     Callee
160 * x3            gp          Global pointer                    -
161 * x4            tp          Thread pointer                    -
162 * x5-7          t0-2        Temporaries                       Caller
163 * x8            s0/fp       Saved register/Frame pointer      Callee
164 * x9            s1          Saved register                    Callee
165 * x10-11        a0-1        Function Arguments/return values  Caller
166 * x12-17        a2-7        Function arguments                Caller
167 * x18-27        s2-11       Saved registers                   Callee
168 * x28-31        t3-6        Temporaries                       Caller
169 *
170 * The RISC-V context is saved to FreeRTOS tasks in the following stack frame,
171 * where the global and thread pointers are currently assumed to be constant so
172 * are not saved:
173 *
174 * mstatus
175 * xCriticalNesting
176 * x31
177 * x30
178 * x29
179 * x28
180 * x27
181 * x26
182 * x25
183 * x24
184 * x23
185 * x22
186 * x21
187 * x20
188 * x19
189 * x18
190 * x17
191 * x16
192 * x15
193 * x14
194 * x13
195 * x12
196 * x11
197 * pvParameters
198 * x9
199 * x8
200 * x7
201 * x6
202 * x5
203 * portTASK_RETURN_ADDRESS
204 * [chip specific registers go here]
205 * pxCode
206 */
207pxPortInitialiseStack:
208    csrr t0, CSR_MSTATUS                /* Obtain current mstatus value. */
209    andi t0, t0, ~0x8                   /* Ensure interrupts are disabled when the stack is restored within an ISR.  Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
210    addi t1, x0, 0x188                  /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
211    slli t1, t1, 4
212    or t0, t0, t1                       /* Set MPIE and MPP bits in mstatus value. */
213
214    addi a0, a0, -portWORD_SIZE
215    store_x t0, 0(a0)                   /* mstatus onto the stack. */
216    addi a0, a0, -portWORD_SIZE         /* Space for critical nesting count. */
217    store_x x0, 0(a0)                   /* Critical nesting count starts at 0 for every task. */
218#ifdef __riscv_32e
219    addi a0, a0, -(6 * portWORD_SIZE)   /* Space for registers x10-15. */
220#else
221    addi a0, a0, -(22 * portWORD_SIZE)  /* Space for registers x10-x31. */
222#endif
223    store_x a2, 0(a0)                   /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
224    addi a0, a0, -(6 * portWORD_SIZE)   /* Space for registers x5-x9 + taskReturnAddress. */
225    load_x t0, xTaskReturnAddress
226    store_x t0, 0(a0)                   /* Return address onto the stack. */
227    addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
228chip_specific_stack_frame:              /* First add any chip specific registers to the stack frame being created. */
229    beq t0, x0, no_more_regs            /* No more chip specific registers to save. */
230    addi a0, a0, -portWORD_SIZE         /* Make space for chip specific register. */
231    store_x x0, 0(a0)                   /* Give the chip specific register an initial value of zero. */
232    addi t0, t0, -1                     /* Decrement the count of chip specific registers remaining. */
233    j chip_specific_stack_frame         /* Until no more chip specific registers. */
234no_more_regs:
235    addi a0, a0, -portWORD_SIZE
236    store_x a1, 0(a0)                   /* mret value (pxCode parameter) onto the stack. */
237    ret
238/*-----------------------------------------------------------*/
239
240xPortStartFirstTask:
241    load_x  sp, pxCurrentTCB            /* Load pxCurrentTCB. */
242    load_x  sp, 0( sp )                 /* Read sp from first TCB member. */
243
244    load_x  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
245
246    portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
247
248    load_x  x7, 4 * portWORD_SIZE( sp )     /* t2 */
249    load_x  x8, 5 * portWORD_SIZE( sp )     /* s0/fp */
250    load_x  x9, 6 * portWORD_SIZE( sp )     /* s1 */
251    load_x  x10, 7 * portWORD_SIZE( sp )    /* a0 */
252    load_x  x11, 8 * portWORD_SIZE( sp )    /* a1 */
253    load_x  x12, 9 * portWORD_SIZE( sp )    /* a2 */
254    load_x  x13, 10 * portWORD_SIZE( sp )   /* a3 */
255    load_x  x14, 11 * portWORD_SIZE( sp )   /* a4 */
256    load_x  x15, 12 * portWORD_SIZE( sp )   /* a5 */
257#ifndef __riscv_32e
258    load_x  x16, 13 * portWORD_SIZE( sp )   /* a6 */
259    load_x  x17, 14 * portWORD_SIZE( sp )   /* a7 */
260    load_x  x18, 15 * portWORD_SIZE( sp )   /* s2 */
261    load_x  x19, 16 * portWORD_SIZE( sp )   /* s3 */
262    load_x  x20, 17 * portWORD_SIZE( sp )   /* s4 */
263    load_x  x21, 18 * portWORD_SIZE( sp )   /* s5 */
264    load_x  x22, 19 * portWORD_SIZE( sp )   /* s6 */
265    load_x  x23, 20 * portWORD_SIZE( sp )   /* s7 */
266    load_x  x24, 21 * portWORD_SIZE( sp )   /* s8 */
267    load_x  x25, 22 * portWORD_SIZE( sp )   /* s9 */
268    load_x  x26, 23 * portWORD_SIZE( sp )   /* s10 */
269    load_x  x27, 24 * portWORD_SIZE( sp )   /* s11 */
270    load_x  x28, 25 * portWORD_SIZE( sp )   /* t3 */
271    load_x  x29, 26 * portWORD_SIZE( sp )   /* t4 */
272    load_x  x30, 27 * portWORD_SIZE( sp )   /* t5 */
273    load_x  x31, 28 * portWORD_SIZE( sp )   /* t6 */
274#endif
275
276    load_x  x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp )    /* Obtain xCriticalNesting value for this task from task's stack. */
277    load_x  x6, pxCriticalNesting           /* Load the address of xCriticalNesting into x6. */
278    store_x x5, 0( x6 )                     /* Restore the critical nesting value for this task. */
279
280    load_x  x5, portMSTATUS_OFFSET * portWORD_SIZE( sp )    /* Initial mstatus into x5 (t0). */
281    addi    x5, x5, 0x08                    /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
282    csrrw   x0, CSR_MSTATUS, x5             /* Interrupts enabled from here! */
283
284    load_x  x5, 2 * portWORD_SIZE( sp )     /* Initial x5 (t0) value. */
285    load_x  x6, 3 * portWORD_SIZE( sp )     /* Initial x6 (t1) value. */
286
287    addi    sp, sp, portCONTEXT_SIZE
288    ret
289/*-----------------------------------------------------------*/
290
291freertos_risc_v_application_exception_handler:
292    csrr t0, CSR_MCAUSE     /* For viewing in the debugger only. */
293    csrr t1, CSR_MEPC        /* For viewing in the debugger only */
294    csrr t2, CSR_MSTATUS     /* For viewing in the debugger only */
295    j $
296/*-----------------------------------------------------------*/
297
298freertos_risc_v_application_interrupt_handler:
299    csrr t0, CSR_MCAUSE     /* For viewing in the debugger only. */
300    csrr t1, CSR_MEPC        /* For viewing in the debugger only */
301    csrr t2, CSR_MSTATUS     /* For viewing in the debugger only */
302    j $
303/*-----------------------------------------------------------*/
304
305    SECTION `.text.freertos_risc_v_exception_handler`:CODE:NOROOT(2)
306    CODE
307
308freertos_risc_v_exception_handler:
309    portcontextSAVE_EXCEPTION_CONTEXT
310    /* a0 now contains mcause. */
311    li t0, 11                           /* 11 == environment call. */
312    bne a0, t0, other_exception         /* Not an M environment call, so some other exception. */
313    call vTaskSwitchContext
314    portcontextRESTORE_CONTEXT
315
316other_exception:
317    call freertos_risc_v_application_exception_handler
318    portcontextRESTORE_CONTEXT
319/*-----------------------------------------------------------*/
320
321    SECTION `.text.freertos_risc_v_interrupt_handler`:CODE:NOROOT(2)
322    CODE
323
324freertos_risc_v_interrupt_handler:
325    portcontextSAVE_INTERRUPT_CONTEXT
326    call freertos_risc_v_application_interrupt_handler
327    portcontextRESTORE_CONTEXT
328/*-----------------------------------------------------------*/
329
330    SECTION `.text.freertos_risc_v_mtimer_interrupt_handler`:CODE:NOROOT(2)
331    CODE
332
333freertos_risc_v_mtimer_interrupt_handler:
334    portcontextSAVE_INTERRUPT_CONTEXT
335    portUPDATE_MTIMER_COMPARE_REGISTER
336    call xTaskIncrementTick
337    beqz a0, exit_without_context_switch    /* Don't switch context if incrementing tick didn't unblock a task. */
338    call vTaskSwitchContext
339exit_without_context_switch:
340    portcontextRESTORE_CONTEXT
341/*-----------------------------------------------------------*/
342
343    SECTION `.text.freertos_risc_v_trap_handler`:CODE:NOROOT(8)
344    CODE
345
346freertos_risc_v_trap_handler:
347    portcontextSAVE_CONTEXT_INTERNAL
348
349    csrr a0, CSR_MCAUSE
350    csrr a1, CSR_MEPC
351
352    bge a0, x0, synchronous_exception
353
354asynchronous_interrupt:
355    store_x a1, 0( sp )                 /* Asynchronous interrupt so save unmodified exception return address. */
356    load_x sp, xISRStackTop             /* Switch to ISR stack. */
357    j handle_interrupt
358
359synchronous_exception:
360    addi a1, a1, 4                      /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */
361    store_x a1, 0( sp )                 /* Save updated exception return address. */
362    load_x sp, xISRStackTop             /* Switch to ISR stack. */
363    j handle_exception
364
365handle_interrupt:
366#if( portasmHAS_MTIME != 0 )
367
368    test_if_mtimer:                     /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
369        addi t0, x0, 1
370        slli t0, t0, __riscv_xlen - 1   /* LSB is already set, shift into MSB.  Shift 31 on 32-bit or 63 on 64-bit cores. */
371        addi t1, t0, 7                  /* 0x8000[]0007 == machine timer interrupt. */
372        bne a0, t1, application_interrupt_handler
373
374        portUPDATE_MTIMER_COMPARE_REGISTER
375        call xTaskIncrementTick
376        beqz a0, processed_source       /* Don't switch context if incrementing tick didn't unblock a task. */
377        call vTaskSwitchContext
378        j processed_source
379
380#endif /* portasmHAS_MTIME */
381
382application_interrupt_handler:
383    call freertos_risc_v_application_interrupt_handler
384    j processed_source
385
386handle_exception:
387    /* a0 contains mcause. */
388    li t0, 11                                   /* 11 == environment call. */
389    bne a0, t0, application_exception_handler   /* Not an M environment call, so some other exception. */
390    call vTaskSwitchContext
391    j processed_source
392
393application_exception_handler:
394    call freertos_risc_v_application_exception_handler
395    j processed_source                  /* No other exceptions handled yet. */
396
397processed_source:
398    portcontextRESTORE_CONTEXT
399/*-----------------------------------------------------------*/
400