xref: /Kernel-v10.6.2/portable/IAR/ARM_CM85/secure/secure_init.c (revision ef7b253b56c9788077f5ecd6c9deb4021923d646) 
1 /*
2  * FreeRTOS Kernel V10.6.2
3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
4  *
5  * SPDX-License-Identifier: MIT
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy of
8  * this software and associated documentation files (the "Software"), to deal in
9  * the Software without restriction, including without limitation the rights to
10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11  * the Software, and to permit persons to whom the Software is furnished to do so,
12  * subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in all
15  * copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * https://www.FreeRTOS.org
25  * https://github.com/FreeRTOS
26  *
27  */
28 
29 /* Standard includes. */
30 #include <stdint.h>
31 
32 /* Secure init includes. */
33 #include "secure_init.h"
34 
35 /* Secure port macros. */
36 #include "secure_port_macros.h"
37 
38 /**
39  * @brief Constants required to manipulate the SCB.
40  */
41 #define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
42 #define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )
43 #define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
44 #define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
45 #define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
46 
47 /**
48  * @brief Constants required to manipulate the FPU.
49  */
50 #define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
51 #define secureinitFPCCR_LSPENS_POS          ( 29UL )
52 #define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )
53 #define secureinitFPCCR_TS_POS              ( 26UL )
54 #define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )
55 
56 #define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
57 #define secureinitNSACR_CP10_POS            ( 10UL )
58 #define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )
59 #define secureinitNSACR_CP11_POS            ( 11UL )
60 #define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )
61 /*-----------------------------------------------------------*/
62 
SecureInit_DePrioritizeNSExceptions(void)63 secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
64 {
65     uint32_t ulIPSR;
66 
67     /* Read the Interrupt Program Status Register (IPSR) value. */
68     secureportREAD_IPSR( ulIPSR );
69 
70     /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
71      * when the processor is running in the Thread Mode. */
72     if( ulIPSR != 0 )
73     {
74         *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
75                                    ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
76                                    ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
77     }
78 }
79 /*-----------------------------------------------------------*/
80 
SecureInit_EnableNSFPUAccess(void)81 secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
82 {
83     uint32_t ulIPSR;
84 
85     /* Read the Interrupt Program Status Register (IPSR) value. */
86     secureportREAD_IPSR( ulIPSR );
87 
88     /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
89      * when the processor is running in the Thread Mode. */
90     if( ulIPSR != 0 )
91     {
92         /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
93          * permitted. CP11 should be programmed to the same value as CP10. */
94         *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
95 
96         /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
97          * that we can enable/disable lazy stacking in port.c file. */
98         *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
99 
100         /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
101          * registers (S16-S31) are also pushed to stack on exception entry and
102          * restored on exception return. */
103         *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
104     }
105 }
106 /*-----------------------------------------------------------*/
107