1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM7 port.
31 *----------------------------------------------------------*/
32
33 /* IAR includes. */
34 #include <intrinsics.h>
35
36 /* Scheduler includes. */
37 #include "FreeRTOS.h"
38 #include "task.h"
39
40 #ifndef __ARMVFP__
41 #error This port can only be used when the project options are configured to enable hardware floating point support.
42 #endif
43
44 #if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
45 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
46 #endif
47
48 /* Prototype of all Interrupt Service Routines (ISRs). */
49 typedef void ( * portISR_t )( void );
50
51 /* Constants required to manipulate the core. Registers first... */
52 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
53 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
54 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
55 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
56 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
57 /* ...then bits in the registers. */
58 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
59 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
60 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
61 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
62 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
63 #define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
64 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
65
66 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
67 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
68 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
69
70 /* Constants used to check the installation of the FreeRTOS interrupt handlers. */
71 #define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
72 #define portVECTOR_INDEX_SVC ( 11 )
73 #define portVECTOR_INDEX_PENDSV ( 14 )
74
75 /* Constants required to check the validity of an interrupt priority. */
76 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
77 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
78 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
79 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
80 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
81 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
82 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
83 #define portPRIGROUP_SHIFT ( 8UL )
84
85 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
86 #define portVECTACTIVE_MASK ( 0xFFUL )
87
88 /* Constants required to manipulate the VFP. */
89 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
90 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
91
92 /* Constants required to set up the initial stack. */
93 #define portINITIAL_XPSR ( 0x01000000 )
94 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
95
96 /* The systick is a 24-bit counter. */
97 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
98
99 /* A fiddle factor to estimate the number of SysTick counts that would have
100 * occurred while the SysTick counter is stopped during tickless idle
101 * calculations. */
102 #define portMISSED_COUNTS_FACTOR ( 94UL )
103
104 /* For strict compliance with the Cortex-M spec the task start address should
105 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
106 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
107
108 /* Let the user override the default SysTick clock rate. If defined by the
109 * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
110 * configuration register. */
111 #ifndef configSYSTICK_CLOCK_HZ
112 #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
113 /* Ensure the SysTick is clocked at the same frequency as the core. */
114 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
115 #else
116 /* Select the option to clock SysTick not at the same frequency as the core. */
117 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
118 #endif
119
120 /*
121 * Setup the timer to generate the tick interrupts. The implementation in this
122 * file is weak to allow application writers to change the timer used to
123 * generate the tick interrupt.
124 */
125 void vPortSetupTimerInterrupt( void );
126
127 /*
128 * Exception handlers.
129 */
130 void xPortSysTickHandler( void );
131
132 /*
133 * Start first task is a separate function so it can be tested in isolation.
134 */
135 extern void vPortStartFirstTask( void );
136
137 /*
138 * Turn the VFP on.
139 */
140 extern void vPortEnableVFP( void );
141
142 /*
143 * Used to catch tasks that attempt to return from their implementing function.
144 */
145 static void prvTaskExitError( void );
146
147 /*
148 * FreeRTOS handlers implemented in assembly.
149 */
150 extern void vPortSVCHandler( void );
151 extern void xPortPendSVHandler( void );
152 /*-----------------------------------------------------------*/
153
154 /* Each task maintains its own interrupt status in the critical nesting
155 * variable. */
156 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
157
158 /*
159 * The number of SysTick increments that make up one tick period.
160 */
161 #if ( configUSE_TICKLESS_IDLE == 1 )
162 static uint32_t ulTimerCountsForOneTick = 0;
163 #endif /* configUSE_TICKLESS_IDLE */
164
165 /*
166 * The maximum number of tick periods that can be suppressed is limited by the
167 * 24 bit resolution of the SysTick timer.
168 */
169 #if ( configUSE_TICKLESS_IDLE == 1 )
170 static uint32_t xMaximumPossibleSuppressedTicks = 0;
171 #endif /* configUSE_TICKLESS_IDLE */
172
173 /*
174 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
175 * power functionality only.
176 */
177 #if ( configUSE_TICKLESS_IDLE == 1 )
178 static uint32_t ulStoppedTimerCompensation = 0;
179 #endif /* configUSE_TICKLESS_IDLE */
180
181 /*
182 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
183 * FreeRTOS API functions are not called from interrupts that have been assigned
184 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
185 */
186 #if ( configASSERT_DEFINED == 1 )
187 static uint8_t ucMaxSysCallPriority = 0;
188 static uint32_t ulMaxPRIGROUPValue = 0;
189 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
190 #endif /* configASSERT_DEFINED */
191
192 /*-----------------------------------------------------------*/
193
194 /*
195 * See header file for description.
196 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)197 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
198 TaskFunction_t pxCode,
199 void * pvParameters )
200 {
201 /* Simulate the stack frame as it would be created by a context switch
202 * interrupt. */
203
204 /* Offset added to account for the way the MCU uses the stack on entry/exit
205 * of interrupts, and to ensure alignment. */
206 pxTopOfStack--;
207
208 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
209 pxTopOfStack--;
210 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
211 pxTopOfStack--;
212 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
213
214 /* Save code space by skipping register initialisation. */
215 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
216 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
217
218 /* A save method is being used that requires each task to maintain its
219 * own exec return value. */
220 pxTopOfStack--;
221 *pxTopOfStack = portINITIAL_EXC_RETURN;
222
223 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
224
225 return pxTopOfStack;
226 }
227 /*-----------------------------------------------------------*/
228
prvTaskExitError(void)229 static void prvTaskExitError( void )
230 {
231 /* A function that implements a task must not exit or attempt to return to
232 * its caller as there is nothing to return to. If a task wants to exit it
233 * should instead call vTaskDelete( NULL ).
234 *
235 * Artificially force an assert() to be triggered if configASSERT() is
236 * defined, then stop here so application writers can catch the error. */
237 configASSERT( uxCriticalNesting == ~0UL );
238 portDISABLE_INTERRUPTS();
239
240 for( ; ; )
241 {
242 }
243 }
244 /*-----------------------------------------------------------*/
245
246 /*
247 * See header file for description.
248 */
xPortStartScheduler(void)249 BaseType_t xPortStartScheduler( void )
250 {
251 /* An application can install FreeRTOS interrupt handlers in one of the
252 * following ways:
253 * 1. Direct Routing - Install the functions vPortSVCHandler and
254 * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
255 * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
256 * interrupts and route program control from those handlers to
257 * vPortSVCHandler and xPortPendSVHandler functions.
258 *
259 * Applications that use Indirect Routing must set
260 * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
261 * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
262 * is 1, should be preferred when possible. */
263 #if ( configCHECK_HANDLER_INSTALLATION == 1 )
264 {
265 const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
266
267 /* Validate that the application has correctly installed the FreeRTOS
268 * handlers for SVCall and PendSV interrupts. We do not check the
269 * installation of the SysTick handler because the application may
270 * choose to drive the RTOS tick using a timer other than the SysTick
271 * timer by overriding the weak function vPortSetupTimerInterrupt().
272 *
273 * Assertion failures here indicate incorrect installation of the
274 * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
275 * https://www.FreeRTOS.org/FAQHelp.html.
276 *
277 * Systems with a configurable address for the interrupt vector table
278 * can also encounter assertion failures or even system faults here if
279 * VTOR is not set correctly to point to the application's vector table. */
280 configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
281 configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
282 }
283 #endif /* configCHECK_HANDLER_INSTALLATION */
284
285 #if ( configASSERT_DEFINED == 1 )
286 {
287 volatile uint8_t ucOriginalPriority;
288 volatile uint32_t ulImplementedPrioBits = 0;
289 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
290 volatile uint8_t ucMaxPriorityValue;
291
292 /* Determine the maximum priority from which ISR safe FreeRTOS API
293 * functions can be called. ISR safe functions are those that end in
294 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
295 * ensure interrupt entry is as fast and simple as possible.
296 *
297 * Save the interrupt priority value that is about to be clobbered. */
298 ucOriginalPriority = *pucFirstUserPriorityRegister;
299
300 /* Determine the number of priority bits available. First write to all
301 * possible bits. */
302 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
303
304 /* Read the value back to see how many bits stuck. */
305 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
306
307 /* Use the same mask on the maximum system call priority. */
308 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
309
310 /* Check that the maximum system call priority is nonzero after
311 * accounting for the number of priority bits supported by the
312 * hardware. A priority of 0 is invalid because setting the BASEPRI
313 * register to 0 unmasks all interrupts, and interrupts with priority 0
314 * cannot be masked using BASEPRI.
315 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
316 configASSERT( ucMaxSysCallPriority );
317
318 /* Check that the bits not implemented in hardware are zero in
319 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
320 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
321
322 /* Calculate the maximum acceptable priority group value for the number
323 * of bits read back. */
324
325 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
326 {
327 ulImplementedPrioBits++;
328 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
329 }
330
331 if( ulImplementedPrioBits == 8 )
332 {
333 /* When the hardware implements 8 priority bits, there is no way for
334 * the software to configure PRIGROUP to not have sub-priorities. As
335 * a result, the least significant bit is always used for sub-priority
336 * and there are 128 preemption priorities and 2 sub-priorities.
337 *
338 * This may cause some confusion in some cases - for example, if
339 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
340 * priority interrupts will be masked in Critical Sections as those
341 * are at the same preemption priority. This may appear confusing as
342 * 4 is higher (numerically lower) priority than
343 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
344 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
345 * to 4, this confusion does not happen and the behaviour remains the same.
346 *
347 * The following assert ensures that the sub-priority bit in the
348 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
349 * confusion. */
350 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
351 ulMaxPRIGROUPValue = 0;
352 }
353 else
354 {
355 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
356 }
357
358 /* Shift the priority group value back to its position within the AIRCR
359 * register. */
360 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
361 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
362
363 /* Restore the clobbered interrupt priority register to its original
364 * value. */
365 *pucFirstUserPriorityRegister = ucOriginalPriority;
366 }
367 #endif /* configASSERT_DEFINED */
368
369 /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
370 * the highest priority. */
371 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
372 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
373 portNVIC_SHPR2_REG = 0;
374
375 /* Start the timer that generates the tick ISR. Interrupts are disabled
376 * here already. */
377 vPortSetupTimerInterrupt();
378
379 /* Initialise the critical nesting count ready for the first task. */
380 uxCriticalNesting = 0;
381
382 /* Ensure the VFP is enabled - it should be anyway. */
383 vPortEnableVFP();
384
385 /* Lazy save always. */
386 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
387
388 /* Start the first task. */
389 vPortStartFirstTask();
390
391 /* Should not get here! */
392 return 0;
393 }
394 /*-----------------------------------------------------------*/
395
vPortEndScheduler(void)396 void vPortEndScheduler( void )
397 {
398 /* Not implemented in ports where there is nothing to return to.
399 * Artificially force an assert. */
400 configASSERT( uxCriticalNesting == 1000UL );
401 }
402 /*-----------------------------------------------------------*/
403
vPortEnterCritical(void)404 void vPortEnterCritical( void )
405 {
406 portDISABLE_INTERRUPTS();
407 uxCriticalNesting++;
408
409 /* This is not the interrupt safe version of the enter critical function so
410 * assert() if it is being called from an interrupt context. Only API
411 * functions that end in "FromISR" can be used in an interrupt. Only assert if
412 * the critical nesting count is 1 to protect against recursive calls if the
413 * assert function also uses a critical section. */
414 if( uxCriticalNesting == 1 )
415 {
416 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
417 }
418 }
419 /*-----------------------------------------------------------*/
420
vPortExitCritical(void)421 void vPortExitCritical( void )
422 {
423 configASSERT( uxCriticalNesting );
424 uxCriticalNesting--;
425
426 if( uxCriticalNesting == 0 )
427 {
428 portENABLE_INTERRUPTS();
429 }
430 }
431 /*-----------------------------------------------------------*/
432
xPortSysTickHandler(void)433 void xPortSysTickHandler( void )
434 {
435 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
436 * executes all interrupts must be unmasked. There is therefore no need to
437 * save and then restore the interrupt mask value as its value is already
438 * known. */
439 portDISABLE_INTERRUPTS();
440 traceISR_ENTER();
441 {
442 /* Increment the RTOS tick. */
443 if( xTaskIncrementTick() != pdFALSE )
444 {
445 traceISR_EXIT_TO_SCHEDULER();
446
447 /* A context switch is required. Context switching is performed in
448 * the PendSV interrupt. Pend the PendSV interrupt. */
449 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
450 }
451 else
452 {
453 traceISR_EXIT();
454 }
455 }
456 portENABLE_INTERRUPTS();
457 }
458 /*-----------------------------------------------------------*/
459
460 #if ( configUSE_TICKLESS_IDLE == 1 )
461
vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)462 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
463 {
464 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
465 TickType_t xModifiableIdleTime;
466
467 /* Make sure the SysTick reload value does not overflow the counter. */
468 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
469 {
470 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
471 }
472
473 /* Enter a critical section but don't use the taskENTER_CRITICAL()
474 * method as that will mask interrupts that should exit sleep mode. */
475 __disable_interrupt();
476 __DSB();
477 __ISB();
478
479 /* If a context switch is pending or a task is waiting for the scheduler
480 * to be unsuspended then abandon the low power entry. */
481 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
482 {
483 /* Re-enable interrupts - see comments above the __disable_interrupt()
484 * call above. */
485 __enable_interrupt();
486 }
487 else
488 {
489 /* Stop the SysTick momentarily. The time the SysTick is stopped for
490 * is accounted for as best it can be, but using the tickless mode will
491 * inevitably result in some tiny drift of the time maintained by the
492 * kernel with respect to calendar time. */
493 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
494
495 /* Use the SysTick current-value register to determine the number of
496 * SysTick decrements remaining until the next tick interrupt. If the
497 * current-value register is zero, then there are actually
498 * ulTimerCountsForOneTick decrements remaining, not zero, because the
499 * SysTick requests the interrupt when decrementing from 1 to 0. */
500 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
501
502 if( ulSysTickDecrementsLeft == 0 )
503 {
504 ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
505 }
506
507 /* Calculate the reload value required to wait xExpectedIdleTime
508 * tick periods. -1 is used because this code normally executes part
509 * way through the first tick period. But if the SysTick IRQ is now
510 * pending, then clear the IRQ, suppressing the first tick, and correct
511 * the reload value to reflect that the second tick period is already
512 * underway. The expected idle time is always at least two ticks. */
513 ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
514
515 if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
516 {
517 portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
518 ulReloadValue -= ulTimerCountsForOneTick;
519 }
520
521 if( ulReloadValue > ulStoppedTimerCompensation )
522 {
523 ulReloadValue -= ulStoppedTimerCompensation;
524 }
525
526 /* Set the new reload value. */
527 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
528
529 /* Clear the SysTick count flag and set the count value back to
530 * zero. */
531 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
532
533 /* Restart SysTick. */
534 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
535
536 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
537 * set its parameter to 0 to indicate that its implementation contains
538 * its own wait for interrupt or wait for event instruction, and so wfi
539 * should not be executed again. However, the original expected idle
540 * time variable must remain unmodified, so a copy is taken. */
541 xModifiableIdleTime = xExpectedIdleTime;
542 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
543
544 if( xModifiableIdleTime > 0 )
545 {
546 __DSB();
547 __WFI();
548 __ISB();
549 }
550
551 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
552
553 /* Re-enable interrupts to allow the interrupt that brought the MCU
554 * out of sleep mode to execute immediately. See comments above
555 * the __disable_interrupt() call above. */
556 __enable_interrupt();
557 __DSB();
558 __ISB();
559
560 /* Disable interrupts again because the clock is about to be stopped
561 * and interrupts that execute while the clock is stopped will increase
562 * any slippage between the time maintained by the RTOS and calendar
563 * time. */
564 __disable_interrupt();
565 __DSB();
566 __ISB();
567
568 /* Disable the SysTick clock without reading the
569 * portNVIC_SYSTICK_CTRL_REG register to ensure the
570 * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
571 * the time the SysTick is stopped for is accounted for as best it can
572 * be, but using the tickless mode will inevitably result in some tiny
573 * drift of the time maintained by the kernel with respect to calendar
574 * time*/
575 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
576
577 /* Determine whether the SysTick has already counted to zero. */
578 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
579 {
580 uint32_t ulCalculatedLoadValue;
581
582 /* The tick interrupt ended the sleep (or is now pending), and
583 * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
584 * with whatever remains of the new tick period. */
585 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
586
587 /* Don't allow a tiny value, or values that have somehow
588 * underflowed because the post sleep hook did something
589 * that took too long or because the SysTick current-value register
590 * is zero. */
591 if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
592 {
593 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
594 }
595
596 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
597
598 /* As the pending tick will be processed as soon as this
599 * function exits, the tick value maintained by the tick is stepped
600 * forward by one less than the time spent waiting. */
601 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
602 }
603 else
604 {
605 /* Something other than the tick interrupt ended the sleep. */
606
607 /* Use the SysTick current-value register to determine the
608 * number of SysTick decrements remaining until the expected idle
609 * time would have ended. */
610 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
611 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
612 {
613 /* If the SysTick is not using the core clock, the current-
614 * value register might still be zero here. In that case, the
615 * SysTick didn't load from the reload register, and there are
616 * ulReloadValue decrements remaining in the expected idle
617 * time, not zero. */
618 if( ulSysTickDecrementsLeft == 0 )
619 {
620 ulSysTickDecrementsLeft = ulReloadValue;
621 }
622 }
623 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
624
625 /* Work out how long the sleep lasted rounded to complete tick
626 * periods (not the ulReload value which accounted for part
627 * ticks). */
628 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
629
630 /* How many complete tick periods passed while the processor
631 * was waiting? */
632 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
633
634 /* The reload value is set to whatever fraction of a single tick
635 * period remains. */
636 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
637 }
638
639 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
640 * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
641 * the SysTick is not using the core clock, temporarily configure it to
642 * use the core clock. This configuration forces the SysTick to load
643 * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
644 * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
645 * to receive the standard value immediately. */
646 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
647 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
648 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
649 {
650 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
651 }
652 #else
653 {
654 /* The temporary usage of the core clock has served its purpose,
655 * as described above. Resume usage of the other clock. */
656 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
657
658 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
659 {
660 /* The partial tick period already ended. Be sure the SysTick
661 * counts it only once. */
662 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
663 }
664
665 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
666 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
667 }
668 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
669
670 /* Step the tick to account for any tick periods that elapsed. */
671 vTaskStepTick( ulCompleteTickPeriods );
672
673 /* Exit with interrupts enabled. */
674 __enable_interrupt();
675 }
676 }
677
678 #endif /* configUSE_TICKLESS_IDLE */
679 /*-----------------------------------------------------------*/
680
681 /*
682 * Setup the systick timer to generate the tick interrupts at the required
683 * frequency.
684 */
vPortSetupTimerInterrupt(void)685 __weak void vPortSetupTimerInterrupt( void )
686 {
687 /* Calculate the constants required to configure the tick interrupt. */
688 #if ( configUSE_TICKLESS_IDLE == 1 )
689 {
690 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
691 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
692 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
693 }
694 #endif /* configUSE_TICKLESS_IDLE */
695
696 /* Stop and clear the SysTick. */
697 portNVIC_SYSTICK_CTRL_REG = 0UL;
698 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
699
700 /* Configure SysTick to interrupt at the requested rate. */
701 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
702 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
703 }
704 /*-----------------------------------------------------------*/
705
706 #if ( configASSERT_DEFINED == 1 )
707
vPortValidateInterruptPriority(void)708 void vPortValidateInterruptPriority( void )
709 {
710 uint32_t ulCurrentInterrupt;
711 uint8_t ucCurrentPriority;
712
713 /* Obtain the number of the currently executing interrupt. */
714 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
715
716 /* Is the interrupt number a user defined interrupt? */
717 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
718 {
719 /* Look up the interrupt's priority. */
720 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
721
722 /* The following assertion will fail if a service routine (ISR) for
723 * an interrupt that has been assigned a priority above
724 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
725 * function. ISR safe FreeRTOS API functions must *only* be called
726 * from interrupts that have been assigned a priority at or below
727 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
728 *
729 * Numerically low interrupt priority numbers represent logically high
730 * interrupt priorities, therefore the priority of the interrupt must
731 * be set to a value equal to or numerically *higher* than
732 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
733 *
734 * Interrupts that use the FreeRTOS API must not be left at their
735 * default priority of zero as that is the highest possible priority,
736 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
737 * and therefore also guaranteed to be invalid.
738 *
739 * FreeRTOS maintains separate thread and ISR API functions to ensure
740 * interrupt entry is as fast and simple as possible.
741 *
742 * The following links provide detailed information:
743 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
744 * https://www.FreeRTOS.org/FAQHelp.html */
745 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
746 }
747
748 /* Priority grouping: The interrupt controller (NVIC) allows the bits
749 * that define each interrupt's priority to be split between bits that
750 * define the interrupt's pre-emption priority bits and bits that define
751 * the interrupt's sub-priority. For simplicity all bits must be defined
752 * to be pre-emption priority bits. The following assertion will fail if
753 * this is not the case (if some bits represent a sub-priority).
754 *
755 * If the application only uses CMSIS libraries for interrupt
756 * configuration then the correct setting can be achieved on all Cortex-M
757 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
758 * scheduler. Note however that some vendor specific peripheral libraries
759 * assume a non-zero priority group setting, in which cases using a value
760 * of zero will result in unpredictable behaviour. */
761 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
762 }
763
764 #endif /* configASSERT_DEFINED */
765
