1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM4F port.
31 *----------------------------------------------------------*/
32
33 /* IAR includes. */
34 #include <intrinsics.h>
35
36 /* Scheduler includes. */
37 #include "FreeRTOS.h"
38 #include "task.h"
39
40 #ifndef __ARMVFP__
41 #error This port can only be used when the project options are configured to enable hardware floating point support.
42 #endif
43
44 #if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
45 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
46 #endif
47
48 /* Constants required to manipulate the core. Registers first... */
49 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
50 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
51 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
52 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
53 /* ...then bits in the registers. */
54 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
55 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
56 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
57 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
58 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
59 #define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
60 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
61
62 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
63 * r0p1 port. */
64 #define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
65 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
66 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
67
68 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
69 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
70 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
71
72 /* Constants required to check the validity of an interrupt priority. */
73 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
74 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
75 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
76 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
77 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
78 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
79 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
80 #define portPRIGROUP_SHIFT ( 8UL )
81
82 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
83 #define portVECTACTIVE_MASK ( 0xFFUL )
84
85 /* Constants required to manipulate the VFP. */
86 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
87 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
88
89 /* Constants required to set up the initial stack. */
90 #define portINITIAL_XPSR ( 0x01000000 )
91 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
92
93 /* The systick is a 24-bit counter. */
94 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
95
96 /* A fiddle factor to estimate the number of SysTick counts that would have
97 * occurred while the SysTick counter is stopped during tickless idle
98 * calculations. */
99 #define portMISSED_COUNTS_FACTOR ( 94UL )
100
101 /* For strict compliance with the Cortex-M spec the task start address should
102 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
103 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
104
105 /* Let the user override the default SysTick clock rate. If defined by the
106 * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
107 * configuration register. */
108 #ifndef configSYSTICK_CLOCK_HZ
109 #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
110 /* Ensure the SysTick is clocked at the same frequency as the core. */
111 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
112 #else
113 /* Select the option to clock SysTick not at the same frequency as the core. */
114 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
115 #endif
116
117 /*
118 * Setup the timer to generate the tick interrupts. The implementation in this
119 * file is weak to allow application writers to change the timer used to
120 * generate the tick interrupt.
121 */
122 void vPortSetupTimerInterrupt( void );
123
124 /*
125 * Exception handlers.
126 */
127 void xPortSysTickHandler( void );
128
129 /*
130 * Start first task is a separate function so it can be tested in isolation.
131 */
132 extern void vPortStartFirstTask( void );
133
134 /*
135 * Turn the VFP on.
136 */
137 extern void vPortEnableVFP( void );
138
139 /*
140 * Used to catch tasks that attempt to return from their implementing function.
141 */
142 static void prvTaskExitError( void );
143
144 /*-----------------------------------------------------------*/
145
146 /* Each task maintains its own interrupt status in the critical nesting
147 * variable. */
148 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
149
150 /*
151 * The number of SysTick increments that make up one tick period.
152 */
153 #if ( configUSE_TICKLESS_IDLE == 1 )
154 static uint32_t ulTimerCountsForOneTick = 0;
155 #endif /* configUSE_TICKLESS_IDLE */
156
157 /*
158 * The maximum number of tick periods that can be suppressed is limited by the
159 * 24 bit resolution of the SysTick timer.
160 */
161 #if ( configUSE_TICKLESS_IDLE == 1 )
162 static uint32_t xMaximumPossibleSuppressedTicks = 0;
163 #endif /* configUSE_TICKLESS_IDLE */
164
165 /*
166 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
167 * power functionality only.
168 */
169 #if ( configUSE_TICKLESS_IDLE == 1 )
170 static uint32_t ulStoppedTimerCompensation = 0;
171 #endif /* configUSE_TICKLESS_IDLE */
172
173 /*
174 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
175 * FreeRTOS API functions are not called from interrupts that have been assigned
176 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
177 */
178 #if ( configASSERT_DEFINED == 1 )
179 static uint8_t ucMaxSysCallPriority = 0;
180 static uint32_t ulMaxPRIGROUPValue = 0;
181 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
182 #endif /* configASSERT_DEFINED */
183
184 /*-----------------------------------------------------------*/
185
186 /*
187 * See header file for description.
188 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)189 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
190 TaskFunction_t pxCode,
191 void * pvParameters )
192 {
193 /* Simulate the stack frame as it would be created by a context switch
194 * interrupt. */
195
196 /* Offset added to account for the way the MCU uses the stack on entry/exit
197 * of interrupts, and to ensure alignment. */
198 pxTopOfStack--;
199
200 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
201 pxTopOfStack--;
202 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
203 pxTopOfStack--;
204 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
205
206 /* Save code space by skipping register initialisation. */
207 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
208 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
209
210 /* A save method is being used that requires each task to maintain its
211 * own exec return value. */
212 pxTopOfStack--;
213 *pxTopOfStack = portINITIAL_EXC_RETURN;
214
215 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
216
217 return pxTopOfStack;
218 }
219 /*-----------------------------------------------------------*/
220
prvTaskExitError(void)221 static void prvTaskExitError( void )
222 {
223 /* A function that implements a task must not exit or attempt to return to
224 * its caller as there is nothing to return to. If a task wants to exit it
225 * should instead call vTaskDelete( NULL ).
226 *
227 * Artificially force an assert() to be triggered if configASSERT() is
228 * defined, then stop here so application writers can catch the error. */
229 configASSERT( uxCriticalNesting == ~0UL );
230 portDISABLE_INTERRUPTS();
231
232 for( ; ; )
233 {
234 }
235 }
236 /*-----------------------------------------------------------*/
237
238 /*
239 * See header file for description.
240 */
xPortStartScheduler(void)241 BaseType_t xPortStartScheduler( void )
242 {
243 /* This port can be used on all revisions of the Cortex-M7 core other than
244 * the r0p1 parts. r0p1 parts should use the port from the
245 * /source/portable/GCC/ARM_CM7/r0p1 directory. */
246 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
247 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
248
249 #if ( configASSERT_DEFINED == 1 )
250 {
251 volatile uint8_t ucOriginalPriority;
252 volatile uint32_t ulImplementedPrioBits = 0;
253 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
254 volatile uint8_t ucMaxPriorityValue;
255
256 /* Determine the maximum priority from which ISR safe FreeRTOS API
257 * functions can be called. ISR safe functions are those that end in
258 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
259 * ensure interrupt entry is as fast and simple as possible.
260 *
261 * Save the interrupt priority value that is about to be clobbered. */
262 ucOriginalPriority = *pucFirstUserPriorityRegister;
263
264 /* Determine the number of priority bits available. First write to all
265 * possible bits. */
266 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
267
268 /* Read the value back to see how many bits stuck. */
269 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
270
271 /* Use the same mask on the maximum system call priority. */
272 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
273
274 /* Check that the maximum system call priority is nonzero after
275 * accounting for the number of priority bits supported by the
276 * hardware. A priority of 0 is invalid because setting the BASEPRI
277 * register to 0 unmasks all interrupts, and interrupts with priority 0
278 * cannot be masked using BASEPRI.
279 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
280 configASSERT( ucMaxSysCallPriority );
281
282 /* Check that the bits not implemented in hardware are zero in
283 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
284 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
285
286 /* Calculate the maximum acceptable priority group value for the number
287 * of bits read back. */
288
289 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
290 {
291 ulImplementedPrioBits++;
292 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
293 }
294
295 if( ulImplementedPrioBits == 8 )
296 {
297 /* When the hardware implements 8 priority bits, there is no way for
298 * the software to configure PRIGROUP to not have sub-priorities. As
299 * a result, the least significant bit is always used for sub-priority
300 * and there are 128 preemption priorities and 2 sub-priorities.
301 *
302 * This may cause some confusion in some cases - for example, if
303 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
304 * priority interrupts will be masked in Critical Sections as those
305 * are at the same preemption priority. This may appear confusing as
306 * 4 is higher (numerically lower) priority than
307 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
308 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
309 * to 4, this confusion does not happen and the behaviour remains the same.
310 *
311 * The following assert ensures that the sub-priority bit in the
312 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
313 * confusion. */
314 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
315 ulMaxPRIGROUPValue = 0;
316 }
317 else
318 {
319 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
320 }
321
322 /* Shift the priority group value back to its position within the AIRCR
323 * register. */
324 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
325 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
326
327 /* Restore the clobbered interrupt priority register to its original
328 * value. */
329 *pucFirstUserPriorityRegister = ucOriginalPriority;
330 }
331 #endif /* configASSERT_DEFINED */
332
333 /* Make PendSV and SysTick the lowest priority interrupts. */
334 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
335 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
336
337 /* Start the timer that generates the tick ISR. Interrupts are disabled
338 * here already. */
339 vPortSetupTimerInterrupt();
340
341 /* Initialise the critical nesting count ready for the first task. */
342 uxCriticalNesting = 0;
343
344 /* Ensure the VFP is enabled - it should be anyway. */
345 vPortEnableVFP();
346
347 /* Lazy save always. */
348 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
349
350 /* Start the first task. */
351 vPortStartFirstTask();
352
353 /* Should not get here! */
354 return 0;
355 }
356 /*-----------------------------------------------------------*/
357
vPortEndScheduler(void)358 void vPortEndScheduler( void )
359 {
360 /* Not implemented in ports where there is nothing to return to.
361 * Artificially force an assert. */
362 configASSERT( uxCriticalNesting == 1000UL );
363 }
364 /*-----------------------------------------------------------*/
365
vPortEnterCritical(void)366 void vPortEnterCritical( void )
367 {
368 portDISABLE_INTERRUPTS();
369 uxCriticalNesting++;
370
371 /* This is not the interrupt safe version of the enter critical function so
372 * assert() if it is being called from an interrupt context. Only API
373 * functions that end in "FromISR" can be used in an interrupt. Only assert if
374 * the critical nesting count is 1 to protect against recursive calls if the
375 * assert function also uses a critical section. */
376 if( uxCriticalNesting == 1 )
377 {
378 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
379 }
380 }
381 /*-----------------------------------------------------------*/
382
vPortExitCritical(void)383 void vPortExitCritical( void )
384 {
385 configASSERT( uxCriticalNesting );
386 uxCriticalNesting--;
387
388 if( uxCriticalNesting == 0 )
389 {
390 portENABLE_INTERRUPTS();
391 }
392 }
393 /*-----------------------------------------------------------*/
394
xPortSysTickHandler(void)395 void xPortSysTickHandler( void )
396 {
397 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
398 * executes all interrupts must be unmasked. There is therefore no need to
399 * save and then restore the interrupt mask value as its value is already
400 * known. */
401 portDISABLE_INTERRUPTS();
402 {
403 /* Increment the RTOS tick. */
404 if( xTaskIncrementTick() != pdFALSE )
405 {
406 /* A context switch is required. Context switching is performed in
407 * the PendSV interrupt. Pend the PendSV interrupt. */
408 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
409 }
410 }
411 portENABLE_INTERRUPTS();
412 }
413 /*-----------------------------------------------------------*/
414
415 #if ( configUSE_TICKLESS_IDLE == 1 )
416
vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)417 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
418 {
419 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
420 TickType_t xModifiableIdleTime;
421
422 /* Make sure the SysTick reload value does not overflow the counter. */
423 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
424 {
425 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
426 }
427
428 /* Enter a critical section but don't use the taskENTER_CRITICAL()
429 * method as that will mask interrupts that should exit sleep mode. */
430 __disable_interrupt();
431 __DSB();
432 __ISB();
433
434 /* If a context switch is pending or a task is waiting for the scheduler
435 * to be unsuspended then abandon the low power entry. */
436 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
437 {
438 /* Re-enable interrupts - see comments above the __disable_interrupt()
439 * call above. */
440 __enable_interrupt();
441 }
442 else
443 {
444 /* Stop the SysTick momentarily. The time the SysTick is stopped for
445 * is accounted for as best it can be, but using the tickless mode will
446 * inevitably result in some tiny drift of the time maintained by the
447 * kernel with respect to calendar time. */
448 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
449
450 /* Use the SysTick current-value register to determine the number of
451 * SysTick decrements remaining until the next tick interrupt. If the
452 * current-value register is zero, then there are actually
453 * ulTimerCountsForOneTick decrements remaining, not zero, because the
454 * SysTick requests the interrupt when decrementing from 1 to 0. */
455 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
456
457 if( ulSysTickDecrementsLeft == 0 )
458 {
459 ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
460 }
461
462 /* Calculate the reload value required to wait xExpectedIdleTime
463 * tick periods. -1 is used because this code normally executes part
464 * way through the first tick period. But if the SysTick IRQ is now
465 * pending, then clear the IRQ, suppressing the first tick, and correct
466 * the reload value to reflect that the second tick period is already
467 * underway. The expected idle time is always at least two ticks. */
468 ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
469
470 if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
471 {
472 portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
473 ulReloadValue -= ulTimerCountsForOneTick;
474 }
475
476 if( ulReloadValue > ulStoppedTimerCompensation )
477 {
478 ulReloadValue -= ulStoppedTimerCompensation;
479 }
480
481 /* Set the new reload value. */
482 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
483
484 /* Clear the SysTick count flag and set the count value back to
485 * zero. */
486 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
487
488 /* Restart SysTick. */
489 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
490
491 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
492 * set its parameter to 0 to indicate that its implementation contains
493 * its own wait for interrupt or wait for event instruction, and so wfi
494 * should not be executed again. However, the original expected idle
495 * time variable must remain unmodified, so a copy is taken. */
496 xModifiableIdleTime = xExpectedIdleTime;
497 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
498
499 if( xModifiableIdleTime > 0 )
500 {
501 __DSB();
502 __WFI();
503 __ISB();
504 }
505
506 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
507
508 /* Re-enable interrupts to allow the interrupt that brought the MCU
509 * out of sleep mode to execute immediately. See comments above
510 * the __disable_interrupt() call above. */
511 __enable_interrupt();
512 __DSB();
513 __ISB();
514
515 /* Disable interrupts again because the clock is about to be stopped
516 * and interrupts that execute while the clock is stopped will increase
517 * any slippage between the time maintained by the RTOS and calendar
518 * time. */
519 __disable_interrupt();
520 __DSB();
521 __ISB();
522
523 /* Disable the SysTick clock without reading the
524 * portNVIC_SYSTICK_CTRL_REG register to ensure the
525 * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
526 * the time the SysTick is stopped for is accounted for as best it can
527 * be, but using the tickless mode will inevitably result in some tiny
528 * drift of the time maintained by the kernel with respect to calendar
529 * time*/
530 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
531
532 /* Determine whether the SysTick has already counted to zero. */
533 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
534 {
535 uint32_t ulCalculatedLoadValue;
536
537 /* The tick interrupt ended the sleep (or is now pending), and
538 * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
539 * with whatever remains of the new tick period. */
540 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
541
542 /* Don't allow a tiny value, or values that have somehow
543 * underflowed because the post sleep hook did something
544 * that took too long or because the SysTick current-value register
545 * is zero. */
546 if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
547 {
548 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
549 }
550
551 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
552
553 /* As the pending tick will be processed as soon as this
554 * function exits, the tick value maintained by the tick is stepped
555 * forward by one less than the time spent waiting. */
556 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
557 }
558 else
559 {
560 /* Something other than the tick interrupt ended the sleep. */
561
562 /* Use the SysTick current-value register to determine the
563 * number of SysTick decrements remaining until the expected idle
564 * time would have ended. */
565 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
566 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
567 {
568 /* If the SysTick is not using the core clock, the current-
569 * value register might still be zero here. In that case, the
570 * SysTick didn't load from the reload register, and there are
571 * ulReloadValue decrements remaining in the expected idle
572 * time, not zero. */
573 if( ulSysTickDecrementsLeft == 0 )
574 {
575 ulSysTickDecrementsLeft = ulReloadValue;
576 }
577 }
578 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
579
580 /* Work out how long the sleep lasted rounded to complete tick
581 * periods (not the ulReload value which accounted for part
582 * ticks). */
583 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
584
585 /* How many complete tick periods passed while the processor
586 * was waiting? */
587 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
588
589 /* The reload value is set to whatever fraction of a single tick
590 * period remains. */
591 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
592 }
593
594 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
595 * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
596 * the SysTick is not using the core clock, temporarily configure it to
597 * use the core clock. This configuration forces the SysTick to load
598 * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
599 * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
600 * to receive the standard value immediately. */
601 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
602 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
603 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
604 {
605 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
606 }
607 #else
608 {
609 /* The temporary usage of the core clock has served its purpose,
610 * as described above. Resume usage of the other clock. */
611 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
612
613 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
614 {
615 /* The partial tick period already ended. Be sure the SysTick
616 * counts it only once. */
617 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
618 }
619
620 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
621 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
622 }
623 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
624
625 /* Step the tick to account for any tick periods that elapsed. */
626 vTaskStepTick( ulCompleteTickPeriods );
627
628 /* Exit with interrupts enabled. */
629 __enable_interrupt();
630 }
631 }
632
633 #endif /* configUSE_TICKLESS_IDLE */
634 /*-----------------------------------------------------------*/
635
636 /*
637 * Setup the systick timer to generate the tick interrupts at the required
638 * frequency.
639 */
vPortSetupTimerInterrupt(void)640 __weak void vPortSetupTimerInterrupt( void )
641 {
642 /* Calculate the constants required to configure the tick interrupt. */
643 #if ( configUSE_TICKLESS_IDLE == 1 )
644 {
645 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
646 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
647 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
648 }
649 #endif /* configUSE_TICKLESS_IDLE */
650
651 /* Stop and clear the SysTick. */
652 portNVIC_SYSTICK_CTRL_REG = 0UL;
653 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
654
655 /* Configure SysTick to interrupt at the requested rate. */
656 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
657 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
658 }
659 /*-----------------------------------------------------------*/
660
661 #if ( configASSERT_DEFINED == 1 )
662
vPortValidateInterruptPriority(void)663 void vPortValidateInterruptPriority( void )
664 {
665 uint32_t ulCurrentInterrupt;
666 uint8_t ucCurrentPriority;
667
668 /* Obtain the number of the currently executing interrupt. */
669 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
670
671 /* Is the interrupt number a user defined interrupt? */
672 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
673 {
674 /* Look up the interrupt's priority. */
675 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
676
677 /* The following assertion will fail if a service routine (ISR) for
678 * an interrupt that has been assigned a priority above
679 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
680 * function. ISR safe FreeRTOS API functions must *only* be called
681 * from interrupts that have been assigned a priority at or below
682 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
683 *
684 * Numerically low interrupt priority numbers represent logically high
685 * interrupt priorities, therefore the priority of the interrupt must
686 * be set to a value equal to or numerically *higher* than
687 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
688 *
689 * Interrupts that use the FreeRTOS API must not be left at their
690 * default priority of zero as that is the highest possible priority,
691 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
692 * and therefore also guaranteed to be invalid.
693 *
694 * FreeRTOS maintains separate thread and ISR API functions to ensure
695 * interrupt entry is as fast and simple as possible.
696 *
697 * The following links provide detailed information:
698 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
699 * https://www.FreeRTOS.org/FAQHelp.html */
700 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
701 }
702
703 /* Priority grouping: The interrupt controller (NVIC) allows the bits
704 * that define each interrupt's priority to be split between bits that
705 * define the interrupt's pre-emption priority bits and bits that define
706 * the interrupt's sub-priority. For simplicity all bits must be defined
707 * to be pre-emption priority bits. The following assertion will fail if
708 * this is not the case (if some bits represent a sub-priority).
709 *
710 * If the application only uses CMSIS libraries for interrupt
711 * configuration then the correct setting can be achieved on all Cortex-M
712 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
713 * scheduler. Note however that some vendor specific peripheral libraries
714 * assume a non-zero priority group setting, in which cases using a value
715 * of zero will result in unpredictable behaviour. */
716 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
717 }
718
719 #endif /* configASSERT_DEFINED */
720
