1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM3 port.
31 *----------------------------------------------------------*/
32
33 /* IAR includes. */
34 #include <intrinsics.h>
35
36 /* Scheduler includes. */
37 #include "FreeRTOS.h"
38 #include "task.h"
39
40 #if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
41 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
42 #endif
43
44 /* Prototype of all Interrupt Service Routines (ISRs). */
45 typedef void ( * portISR_t )( void );
46
47 /* Constants required to manipulate the core. Registers first... */
48 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
49 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
50 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
51 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
52 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
53 /* ...then bits in the registers. */
54 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
55 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
56 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
57 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
58 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
59 #define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
60 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
61
62 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
63 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
64 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
65
66 /* Constants used to check the installation of the FreeRTOS interrupt handlers. */
67 #define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
68 #define portVECTOR_INDEX_SVC ( 11 )
69 #define portVECTOR_INDEX_PENDSV ( 14 )
70
71 /* Constants required to check the validity of an interrupt priority. */
72 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
73 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
74 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
75 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
76 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
77 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
78 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
79 #define portPRIGROUP_SHIFT ( 8UL )
80
81 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
82 #define portVECTACTIVE_MASK ( 0xFFUL )
83
84 /* Constants required to set up the initial stack. */
85 #define portINITIAL_XPSR ( 0x01000000 )
86
87 /* The systick is a 24-bit counter. */
88 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
89
90 /* A fiddle factor to estimate the number of SysTick counts that would have
91 * occurred while the SysTick counter is stopped during tickless idle
92 * calculations. */
93 #define portMISSED_COUNTS_FACTOR ( 94UL )
94
95 /* For strict compliance with the Cortex-M spec the task start address should
96 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
97 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
98
99 /* Let the user override the default SysTick clock rate. If defined by the
100 * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
101 * configuration register. */
102 #ifndef configSYSTICK_CLOCK_HZ
103 #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
104 /* Ensure the SysTick is clocked at the same frequency as the core. */
105 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
106 #else
107 /* Select the option to clock SysTick not at the same frequency as the core. */
108 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
109 #endif
110
111 /*
112 * Setup the timer to generate the tick interrupts. The implementation in this
113 * file is weak to allow application writers to change the timer used to
114 * generate the tick interrupt.
115 */
116 void vPortSetupTimerInterrupt( void );
117
118 /*
119 * Exception handlers.
120 */
121 void xPortSysTickHandler( void );
122
123 /*
124 * Start first task is a separate function so it can be tested in isolation.
125 */
126 extern void vPortStartFirstTask( void );
127
128 /*
129 * Used to catch tasks that attempt to return from their implementing function.
130 */
131 static void prvTaskExitError( void );
132
133 /*
134 * FreeRTOS handlers implemented in assembly.
135 */
136 extern void vPortSVCHandler( void );
137 extern void xPortPendSVHandler( void );
138 /*-----------------------------------------------------------*/
139
140 /* Each task maintains its own interrupt status in the critical nesting
141 * variable. */
142 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
143
144 /*
145 * The number of SysTick increments that make up one tick period.
146 */
147 #if ( configUSE_TICKLESS_IDLE == 1 )
148 static uint32_t ulTimerCountsForOneTick = 0;
149 #endif /* configUSE_TICKLESS_IDLE */
150
151 /*
152 * The maximum number of tick periods that can be suppressed is limited by the
153 * 24 bit resolution of the SysTick timer.
154 */
155 #if ( configUSE_TICKLESS_IDLE == 1 )
156 static uint32_t xMaximumPossibleSuppressedTicks = 0;
157 #endif /* configUSE_TICKLESS_IDLE */
158
159 /*
160 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
161 * power functionality only.
162 */
163 #if ( configUSE_TICKLESS_IDLE == 1 )
164 static uint32_t ulStoppedTimerCompensation = 0;
165 #endif /* configUSE_TICKLESS_IDLE */
166
167 /*
168 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
169 * FreeRTOS API functions are not called from interrupts that have been assigned
170 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
171 */
172 #if ( configASSERT_DEFINED == 1 )
173 static uint8_t ucMaxSysCallPriority = 0;
174 static uint32_t ulMaxPRIGROUPValue = 0;
175 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
176 #endif /* configASSERT_DEFINED */
177
178 /*-----------------------------------------------------------*/
179
180 /*
181 * See header file for description.
182 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)183 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
184 TaskFunction_t pxCode,
185 void * pvParameters )
186 {
187 /* Simulate the stack frame as it would be created by a context switch
188 * interrupt. */
189 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
190 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
191 pxTopOfStack--;
192 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
193 pxTopOfStack--;
194 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
195 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
196 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
197 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
198
199 return pxTopOfStack;
200 }
201 /*-----------------------------------------------------------*/
202
prvTaskExitError(void)203 static void prvTaskExitError( void )
204 {
205 /* A function that implements a task must not exit or attempt to return to
206 * its caller as there is nothing to return to. If a task wants to exit it
207 * should instead call vTaskDelete( NULL ).
208 *
209 * Artificially force an assert() to be triggered if configASSERT() is
210 * defined, then stop here so application writers can catch the error. */
211 configASSERT( uxCriticalNesting == ~0UL );
212 portDISABLE_INTERRUPTS();
213
214 for( ; ; )
215 {
216 }
217 }
218 /*-----------------------------------------------------------*/
219
220 /*
221 * See header file for description.
222 */
xPortStartScheduler(void)223 BaseType_t xPortStartScheduler( void )
224 {
225 /* An application can install FreeRTOS interrupt handlers in one of the
226 * following ways:
227 * 1. Direct Routing - Install the functions vPortSVCHandler and
228 * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
229 * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
230 * interrupts and route program control from those handlers to
231 * vPortSVCHandler and xPortPendSVHandler functions.
232 *
233 * Applications that use Indirect Routing must set
234 * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
235 * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
236 * is 1, should be preferred when possible. */
237 #if ( configCHECK_HANDLER_INSTALLATION == 1 )
238 {
239 const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
240
241 /* Validate that the application has correctly installed the FreeRTOS
242 * handlers for SVCall and PendSV interrupts. We do not check the
243 * installation of the SysTick handler because the application may
244 * choose to drive the RTOS tick using a timer other than the SysTick
245 * timer by overriding the weak function vPortSetupTimerInterrupt().
246 *
247 * Assertion failures here indicate incorrect installation of the
248 * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
249 * https://www.FreeRTOS.org/FAQHelp.html.
250 *
251 * Systems with a configurable address for the interrupt vector table
252 * can also encounter assertion failures or even system faults here if
253 * VTOR is not set correctly to point to the application's vector table. */
254 configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
255 configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
256 }
257 #endif /* configCHECK_HANDLER_INSTALLATION */
258
259 #if ( configASSERT_DEFINED == 1 )
260 {
261 volatile uint8_t ucOriginalPriority;
262 volatile uint32_t ulImplementedPrioBits = 0;
263 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
264 volatile uint8_t ucMaxPriorityValue;
265
266 /* Determine the maximum priority from which ISR safe FreeRTOS API
267 * functions can be called. ISR safe functions are those that end in
268 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
269 * ensure interrupt entry is as fast and simple as possible.
270 *
271 * Save the interrupt priority value that is about to be clobbered. */
272 ucOriginalPriority = *pucFirstUserPriorityRegister;
273
274 /* Determine the number of priority bits available. First write to all
275 * possible bits. */
276 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
277
278 /* Read the value back to see how many bits stuck. */
279 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
280
281 /* Use the same mask on the maximum system call priority. */
282 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
283
284 /* Check that the maximum system call priority is nonzero after
285 * accounting for the number of priority bits supported by the
286 * hardware. A priority of 0 is invalid because setting the BASEPRI
287 * register to 0 unmasks all interrupts, and interrupts with priority 0
288 * cannot be masked using BASEPRI.
289 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
290 configASSERT( ucMaxSysCallPriority );
291
292 /* Check that the bits not implemented in hardware are zero in
293 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
294 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U );
295
296 /* Calculate the maximum acceptable priority group value for the number
297 * of bits read back. */
298
299 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
300 {
301 ulImplementedPrioBits++;
302 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
303 }
304
305 if( ulImplementedPrioBits == 8 )
306 {
307 /* When the hardware implements 8 priority bits, there is no way for
308 * the software to configure PRIGROUP to not have sub-priorities. As
309 * a result, the least significant bit is always used for sub-priority
310 * and there are 128 preemption priorities and 2 sub-priorities.
311 *
312 * This may cause some confusion in some cases - for example, if
313 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
314 * priority interrupts will be masked in Critical Sections as those
315 * are at the same preemption priority. This may appear confusing as
316 * 4 is higher (numerically lower) priority than
317 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
318 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
319 * to 4, this confusion does not happen and the behaviour remains the same.
320 *
321 * The following assert ensures that the sub-priority bit in the
322 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
323 * confusion. */
324 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
325 ulMaxPRIGROUPValue = 0;
326 }
327 else
328 {
329 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
330 }
331
332 /* Shift the priority group value back to its position within the AIRCR
333 * register. */
334 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
335 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
336
337 /* Restore the clobbered interrupt priority register to its original
338 * value. */
339 *pucFirstUserPriorityRegister = ucOriginalPriority;
340 }
341 #endif /* configASSERT_DEFINED */
342
343 /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
344 * the highest priority. */
345 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
346 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
347 portNVIC_SHPR2_REG = 0;
348
349 /* Start the timer that generates the tick ISR. Interrupts are disabled
350 * here already. */
351 vPortSetupTimerInterrupt();
352
353 /* Initialise the critical nesting count ready for the first task. */
354 uxCriticalNesting = 0;
355
356 /* Start the first task. */
357 vPortStartFirstTask();
358
359 /* Should not get here! */
360 return 0;
361 }
362 /*-----------------------------------------------------------*/
363
vPortEndScheduler(void)364 void vPortEndScheduler( void )
365 {
366 /* Not implemented in ports where there is nothing to return to.
367 * Artificially force an assert. */
368 configASSERT( uxCriticalNesting == 1000UL );
369 }
370 /*-----------------------------------------------------------*/
371
vPortEnterCritical(void)372 void vPortEnterCritical( void )
373 {
374 portDISABLE_INTERRUPTS();
375 uxCriticalNesting++;
376
377 /* This is not the interrupt safe version of the enter critical function so
378 * assert() if it is being called from an interrupt context. Only API
379 * functions that end in "FromISR" can be used in an interrupt. Only assert if
380 * the critical nesting count is 1 to protect against recursive calls if the
381 * assert function also uses a critical section. */
382 if( uxCriticalNesting == 1 )
383 {
384 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
385 }
386 }
387 /*-----------------------------------------------------------*/
388
vPortExitCritical(void)389 void vPortExitCritical( void )
390 {
391 configASSERT( uxCriticalNesting );
392 uxCriticalNesting--;
393
394 if( uxCriticalNesting == 0 )
395 {
396 portENABLE_INTERRUPTS();
397 }
398 }
399 /*-----------------------------------------------------------*/
400
xPortSysTickHandler(void)401 void xPortSysTickHandler( void )
402 {
403 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
404 * executes all interrupts must be unmasked. There is therefore no need to
405 * save and then restore the interrupt mask value as its value is already
406 * known. */
407 portDISABLE_INTERRUPTS();
408 traceISR_ENTER();
409 {
410 /* Increment the RTOS tick. */
411 if( xTaskIncrementTick() != pdFALSE )
412 {
413 traceISR_EXIT_TO_SCHEDULER();
414
415 /* A context switch is required. Context switching is performed in
416 * the PendSV interrupt. Pend the PendSV interrupt. */
417 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
418 }
419 else
420 {
421 traceISR_EXIT();
422 }
423 }
424 portENABLE_INTERRUPTS();
425 }
426 /*-----------------------------------------------------------*/
427
428 #if ( configUSE_TICKLESS_IDLE == 1 )
429
vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)430 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
431 {
432 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
433 TickType_t xModifiableIdleTime;
434
435 /* Make sure the SysTick reload value does not overflow the counter. */
436 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
437 {
438 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
439 }
440
441 /* Enter a critical section but don't use the taskENTER_CRITICAL()
442 * method as that will mask interrupts that should exit sleep mode. */
443 __disable_interrupt();
444 __DSB();
445 __ISB();
446
447 /* If a context switch is pending or a task is waiting for the scheduler
448 * to be unsuspended then abandon the low power entry. */
449 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
450 {
451 /* Re-enable interrupts - see comments above the __disable_interrupt()
452 * call above. */
453 __enable_interrupt();
454 }
455 else
456 {
457 /* Stop the SysTick momentarily. The time the SysTick is stopped for
458 * is accounted for as best it can be, but using the tickless mode will
459 * inevitably result in some tiny drift of the time maintained by the
460 * kernel with respect to calendar time. */
461 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
462
463 /* Use the SysTick current-value register to determine the number of
464 * SysTick decrements remaining until the next tick interrupt. If the
465 * current-value register is zero, then there are actually
466 * ulTimerCountsForOneTick decrements remaining, not zero, because the
467 * SysTick requests the interrupt when decrementing from 1 to 0. */
468 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
469
470 if( ulSysTickDecrementsLeft == 0 )
471 {
472 ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
473 }
474
475 /* Calculate the reload value required to wait xExpectedIdleTime
476 * tick periods. -1 is used because this code normally executes part
477 * way through the first tick period. But if the SysTick IRQ is now
478 * pending, then clear the IRQ, suppressing the first tick, and correct
479 * the reload value to reflect that the second tick period is already
480 * underway. The expected idle time is always at least two ticks. */
481 ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
482
483 if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
484 {
485 portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
486 ulReloadValue -= ulTimerCountsForOneTick;
487 }
488
489 if( ulReloadValue > ulStoppedTimerCompensation )
490 {
491 ulReloadValue -= ulStoppedTimerCompensation;
492 }
493
494 /* Set the new reload value. */
495 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
496
497 /* Clear the SysTick count flag and set the count value back to
498 * zero. */
499 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
500
501 /* Restart SysTick. */
502 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
503
504 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
505 * set its parameter to 0 to indicate that its implementation contains
506 * its own wait for interrupt or wait for event instruction, and so wfi
507 * should not be executed again. However, the original expected idle
508 * time variable must remain unmodified, so a copy is taken. */
509 xModifiableIdleTime = xExpectedIdleTime;
510 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
511
512 if( xModifiableIdleTime > 0 )
513 {
514 __DSB();
515 __WFI();
516 __ISB();
517 }
518
519 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
520
521 /* Re-enable interrupts to allow the interrupt that brought the MCU
522 * out of sleep mode to execute immediately. See comments above
523 * the __disable_interrupt() call above. */
524 __enable_interrupt();
525 __DSB();
526 __ISB();
527
528 /* Disable interrupts again because the clock is about to be stopped
529 * and interrupts that execute while the clock is stopped will increase
530 * any slippage between the time maintained by the RTOS and calendar
531 * time. */
532 __disable_interrupt();
533 __DSB();
534 __ISB();
535
536 /* Disable the SysTick clock without reading the
537 * portNVIC_SYSTICK_CTRL_REG register to ensure the
538 * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
539 * the time the SysTick is stopped for is accounted for as best it can
540 * be, but using the tickless mode will inevitably result in some tiny
541 * drift of the time maintained by the kernel with respect to calendar
542 * time*/
543 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
544
545 /* Determine whether the SysTick has already counted to zero. */
546 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
547 {
548 uint32_t ulCalculatedLoadValue;
549
550 /* The tick interrupt ended the sleep (or is now pending), and
551 * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
552 * with whatever remains of the new tick period. */
553 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
554
555 /* Don't allow a tiny value, or values that have somehow
556 * underflowed because the post sleep hook did something
557 * that took too long or because the SysTick current-value register
558 * is zero. */
559 if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
560 {
561 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
562 }
563
564 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
565
566 /* As the pending tick will be processed as soon as this
567 * function exits, the tick value maintained by the tick is stepped
568 * forward by one less than the time spent waiting. */
569 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
570 }
571 else
572 {
573 /* Something other than the tick interrupt ended the sleep. */
574
575 /* Use the SysTick current-value register to determine the
576 * number of SysTick decrements remaining until the expected idle
577 * time would have ended. */
578 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
579 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
580 {
581 /* If the SysTick is not using the core clock, the current-
582 * value register might still be zero here. In that case, the
583 * SysTick didn't load from the reload register, and there are
584 * ulReloadValue decrements remaining in the expected idle
585 * time, not zero. */
586 if( ulSysTickDecrementsLeft == 0 )
587 {
588 ulSysTickDecrementsLeft = ulReloadValue;
589 }
590 }
591 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
592
593 /* Work out how long the sleep lasted rounded to complete tick
594 * periods (not the ulReload value which accounted for part
595 * ticks). */
596 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
597
598 /* How many complete tick periods passed while the processor
599 * was waiting? */
600 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
601
602 /* The reload value is set to whatever fraction of a single tick
603 * period remains. */
604 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
605 }
606
607 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
608 * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
609 * the SysTick is not using the core clock, temporarily configure it to
610 * use the core clock. This configuration forces the SysTick to load
611 * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
612 * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
613 * to receive the standard value immediately. */
614 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
615 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
616 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
617 {
618 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
619 }
620 #else
621 {
622 /* The temporary usage of the core clock has served its purpose,
623 * as described above. Resume usage of the other clock. */
624 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
625
626 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
627 {
628 /* The partial tick period already ended. Be sure the SysTick
629 * counts it only once. */
630 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
631 }
632
633 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
634 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
635 }
636 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
637
638 /* Step the tick to account for any tick periods that elapsed. */
639 vTaskStepTick( ulCompleteTickPeriods );
640
641 /* Exit with interrupts enabled. */
642 __enable_interrupt();
643 }
644 }
645
646 #endif /* configUSE_TICKLESS_IDLE */
647 /*-----------------------------------------------------------*/
648
649 /*
650 * Setup the systick timer to generate the tick interrupts at the required
651 * frequency.
652 */
vPortSetupTimerInterrupt(void)653 __weak void vPortSetupTimerInterrupt( void )
654 {
655 /* Calculate the constants required to configure the tick interrupt. */
656 #if ( configUSE_TICKLESS_IDLE == 1 )
657 {
658 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
659 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
660 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
661 }
662 #endif /* configUSE_TICKLESS_IDLE */
663
664 /* Stop and clear the SysTick. */
665 portNVIC_SYSTICK_CTRL_REG = 0UL;
666 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
667
668 /* Configure SysTick to interrupt at the requested rate. */
669 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
670 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
671 }
672 /*-----------------------------------------------------------*/
673
674 #if ( configASSERT_DEFINED == 1 )
675
vPortValidateInterruptPriority(void)676 void vPortValidateInterruptPriority( void )
677 {
678 uint32_t ulCurrentInterrupt;
679 uint8_t ucCurrentPriority;
680
681 /* Obtain the number of the currently executing interrupt. */
682 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
683
684 /* Is the interrupt number a user defined interrupt? */
685 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
686 {
687 /* Look up the interrupt's priority. */
688 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
689
690 /* The following assertion will fail if a service routine (ISR) for
691 * an interrupt that has been assigned a priority above
692 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
693 * function. ISR safe FreeRTOS API functions must *only* be called
694 * from interrupts that have been assigned a priority at or below
695 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
696 *
697 * Numerically low interrupt priority numbers represent logically high
698 * interrupt priorities, therefore the priority of the interrupt must
699 * be set to a value equal to or numerically *higher* than
700 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
701 *
702 * Interrupts that use the FreeRTOS API must not be left at their
703 * default priority of zero as that is the highest possible priority,
704 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
705 * and therefore also guaranteed to be invalid.
706 *
707 * FreeRTOS maintains separate thread and ISR API functions to ensure
708 * interrupt entry is as fast and simple as possible.
709 *
710 * The following links provide detailed information:
711 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
712 * https://www.FreeRTOS.org/FAQHelp.html */
713 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
714 }
715
716 /* Priority grouping: The interrupt controller (NVIC) allows the bits
717 * that define each interrupt's priority to be split between bits that
718 * define the interrupt's pre-emption priority bits and bits that define
719 * the interrupt's sub-priority. For simplicity all bits must be defined
720 * to be pre-emption priority bits. The following assertion will fail if
721 * this is not the case (if some bits represent a sub-priority).
722 *
723 * If the application only uses CMSIS libraries for interrupt
724 * configuration then the correct setting can be achieved on all Cortex-M
725 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
726 * scheduler. Note however that some vendor specific peripheral libraries
727 * assume a non-zero priority group setting, in which cases using a value
728 * of zero will result in unpredictable behaviour. */
729 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
730 }
731
732 #endif /* configASSERT_DEFINED */
733