1/* 2 * FreeRTOS Kernel V10.6.2 3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 * this software and associated documentation files (the "Software"), to deal in 9 * the Software without restriction, including without limitation the rights to 10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 * the Software, and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in all 15 * copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * https://www.FreeRTOS.org 25 * https://github.com/FreeRTOS 26 * 27 */ 28 29#include <FreeRTOSConfig.h> 30 31 RSEG CODE:CODE(2) 32 thumb 33 34 EXTERN vPortYieldFromISR 35 EXTERN pxCurrentTCB 36 EXTERN vTaskSwitchContext 37 38 PUBLIC vSetMSP 39 PUBLIC xPortPendSVHandler 40 PUBLIC vPortSVCHandler 41 PUBLIC vPortStartFirstTask 42 PUBLIC ulSetInterruptMaskFromISR 43 PUBLIC vClearInterruptMaskFromISR 44 45/*-----------------------------------------------------------*/ 46 47vSetMSP 48 msr msp, r0 49 bx lr 50 51/*-----------------------------------------------------------*/ 52 53xPortPendSVHandler: 54 mrs r0, psp 55 56 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ 57 ldr r2, [r3] 58 59 subs r0, r0, #32 /* Make space for the remaining low registers. */ 60 str r0, [r2] /* Save the new top of stack. */ 61 stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */ 62 mov r4, r8 /* Store the high registers. */ 63 mov r5, r9 64 mov r6, r10 65 mov r7, r11 66 stmia r0!, {r4-r7} 67 68 push {r3, r14} 69 cpsid i 70 bl vTaskSwitchContext 71 cpsie i 72 pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */ 73 74 ldr r1, [r2] 75 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ 76 adds r0, r0, #16 /* Move to the high registers. */ 77 ldmia r0!, {r4-r7} /* Pop the high registers. */ 78 mov r8, r4 79 mov r9, r5 80 mov r10, r6 81 mov r11, r7 82 83 msr psp, r0 /* Remember the new top of stack for the task. */ 84 85 subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */ 86 ldmia r0!, {r4-r7} /* Pop low registers. */ 87 88 bx r3 89 90/*-----------------------------------------------------------*/ 91 92vPortSVCHandler; 93 /* This function is no longer used, but retained for backward 94 compatibility. */ 95 bx lr 96 97/*-----------------------------------------------------------*/ 98 99vPortStartFirstTask 100 /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector 101 table offset register that can be used to locate the initial stack value. 102 Not all M0 parts have the application vector table at address 0. */ 103 104 ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */ 105 ldr r1, [r3] 106 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ 107 adds r0, #32 /* Discard everything up to r0. */ 108 msr psp, r0 /* This is now the new top of stack to use in the task. */ 109 movs r0, #2 /* Switch to the psp stack. */ 110 msr CONTROL, r0 111 isb 112 pop {r0-r5} /* Pop the registers that are saved automatically. */ 113 mov lr, r5 /* lr is now in r5. */ 114 pop {r3} /* The return address is now in r3. */ 115 pop {r2} /* Pop and discard the XPSR. */ 116 cpsie i /* The first task has its context and interrupts can be enabled. */ 117 bx r3 /* Jump to the user defined task code. */ 118 119/*-----------------------------------------------------------*/ 120 121ulSetInterruptMaskFromISR 122 mrs r0, PRIMASK 123 cpsid i 124 bx lr 125 126/*-----------------------------------------------------------*/ 127 128vClearInterruptMaskFromISR 129 msr PRIMASK, r0 130 bx lr 131 132 END 133
