1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the SH2A port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 /* Library includes. */
38 #include "string.h"
39
40 /* Hardware specifics. */
41 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
42
43 #include "platform.h"
44
45 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
46
47 #include "iodefine.h"
48
49 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
50
51 /*-----------------------------------------------------------*/
52
53 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
54 PSW is set with U and I set, and PM and IPL clear. */
55 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
56 #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
57
58 /* These macros allow a critical section to be added around the call to
59 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
60 priority - ie a known priority. Therefore these local macros are a slight
61 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
62 which would require the old IPL to be read first and stored in a local variable. */
63 #define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
64 #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
65
66 /*-----------------------------------------------------------*/
67
68 /*
69 * Function to start the first task executing - written in asm code as direct
70 * access to registers is required.
71 */
72 static void prvStartFirstTask( void ) __attribute__((naked));
73
74 /*
75 * Software interrupt handler. Performs the actual context switch (saving and
76 * restoring of registers). Written in asm code as direct register access is
77 * required.
78 */
79 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
80 R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
81 R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
82 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
83 void vSoftwareInterruptISR( void ) __attribute__((naked));
84 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
85
86 /*
87 * The tick ISR handler. The peripheral used is configured by the application
88 * via a hook/callback function.
89 */
90 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
91
92 R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
93 R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
94
95 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
96
97 void vTickISR( void ) __attribute__( ( interrupt ) );
98
99 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
100 /*-----------------------------------------------------------*/
101
102 extern void *pxCurrentTCB;
103
104 /*-----------------------------------------------------------*/
105
106 /*
107 * See header file for description.
108 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)109 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
110 {
111 /* R0 is not included as it is the stack pointer. */
112
113 *pxTopOfStack = 0x00;
114 pxTopOfStack--;
115 *pxTopOfStack = portINITIAL_PSW;
116 pxTopOfStack--;
117 *pxTopOfStack = ( StackType_t ) pxCode;
118
119 /* When debugging it can be useful if every register is set to a known
120 value. Otherwise code space can be saved by just setting the registers
121 that need to be set. */
122 #ifdef USE_FULL_REGISTER_INITIALISATION
123 {
124 pxTopOfStack--;
125 *pxTopOfStack = 0xffffffff; /* r15. */
126 pxTopOfStack--;
127 *pxTopOfStack = 0xeeeeeeee;
128 pxTopOfStack--;
129 *pxTopOfStack = 0xdddddddd;
130 pxTopOfStack--;
131 *pxTopOfStack = 0xcccccccc;
132 pxTopOfStack--;
133 *pxTopOfStack = 0xbbbbbbbb;
134 pxTopOfStack--;
135 *pxTopOfStack = 0xaaaaaaaa;
136 pxTopOfStack--;
137 *pxTopOfStack = 0x99999999;
138 pxTopOfStack--;
139 *pxTopOfStack = 0x88888888;
140 pxTopOfStack--;
141 *pxTopOfStack = 0x77777777;
142 pxTopOfStack--;
143 *pxTopOfStack = 0x66666666;
144 pxTopOfStack--;
145 *pxTopOfStack = 0x55555555;
146 pxTopOfStack--;
147 *pxTopOfStack = 0x44444444;
148 pxTopOfStack--;
149 *pxTopOfStack = 0x33333333;
150 pxTopOfStack--;
151 *pxTopOfStack = 0x22222222;
152 pxTopOfStack--;
153 }
154 #else
155 {
156 pxTopOfStack -= 15;
157 }
158 #endif
159
160 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
161 pxTopOfStack--;
162 *pxTopOfStack = portINITIAL_FPSW;
163 pxTopOfStack--;
164 *pxTopOfStack = 0x11111111; /* Accumulator 0. */
165 pxTopOfStack--;
166 *pxTopOfStack = 0x22222222; /* Accumulator 0. */
167 pxTopOfStack--;
168 *pxTopOfStack = 0x33333333; /* Accumulator 0. */
169 pxTopOfStack--;
170 *pxTopOfStack = 0x44444444; /* Accumulator 1. */
171 pxTopOfStack--;
172 *pxTopOfStack = 0x55555555; /* Accumulator 1. */
173 pxTopOfStack--;
174 *pxTopOfStack = 0x66666666; /* Accumulator 1. */
175
176 return pxTopOfStack;
177 }
178 /*-----------------------------------------------------------*/
179
xPortStartScheduler(void)180 BaseType_t xPortStartScheduler( void )
181 {
182 extern void vApplicationSetupTimerInterrupt( void );
183
184 /* Use pxCurrentTCB just so it does not get optimised away. */
185 if( pxCurrentTCB != NULL )
186 {
187 /* Call an application function to set up the timer that will generate the
188 tick interrupt. This way the application can decide which peripheral to
189 use. A demo application is provided to show a suitable example. */
190 vApplicationSetupTimerInterrupt();
191
192 /* Enable the software interrupt. */
193 _IEN( _ICU_SWINT ) = 1;
194
195 /* Ensure the software interrupt is clear. */
196 _IR( _ICU_SWINT ) = 0;
197
198 /* Ensure the software interrupt is set to the kernel priority. */
199 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
200
201 /* Start the first task. */
202 prvStartFirstTask();
203 }
204
205 /* Should not get here. */
206 return pdFAIL;
207 }
208 /*-----------------------------------------------------------*/
209
vPortEndScheduler(void)210 void vPortEndScheduler( void )
211 {
212 /* Not implemented in ports where there is nothing to return to.
213 Artificially force an assert. */
214 configASSERT( pxCurrentTCB == NULL );
215 }
216 /*-----------------------------------------------------------*/
217
prvStartFirstTask(void)218 static void prvStartFirstTask( void )
219 {
220 __asm volatile
221 (
222 /* When starting the scheduler there is nothing that needs moving to the
223 interrupt stack because the function is not called from an interrupt.
224 Just ensure the current stack is the user stack. */
225 "SETPSW U \n" \
226
227 /* Obtain the location of the stack associated with which ever task
228 pxCurrentTCB is currently pointing to. */
229 "MOV.L #_pxCurrentTCB, R15 \n" \
230 "MOV.L [R15], R15 \n" \
231 "MOV.L [R15], R0 \n" \
232
233 /* Restore the registers from the stack of the task pointed to by
234 pxCurrentTCB. */
235 "POP R15 \n" \
236
237 /* Accumulator low 32 bits. */
238 "MVTACLO R15, A0 \n" \
239 "POP R15 \n" \
240
241 /* Accumulator high 32 bits. */
242 "MVTACHI R15, A0 \n" \
243 "POP R15 \n" \
244
245 /* Accumulator guard. */
246 "MVTACGU R15, A0 \n" \
247 "POP R15 \n" \
248
249 /* Accumulator low 32 bits. */
250 "MVTACLO R15, A1 \n" \
251 "POP R15 \n" \
252
253 /* Accumulator high 32 bits. */
254 "MVTACHI R15, A1 \n" \
255 "POP R15 \n" \
256
257 /* Accumulator guard. */
258 "MVTACGU R15, A1 \n" \
259 "POP R15 \n" \
260
261 /* Floating point status word. */
262 "MVTC R15, FPSW \n" \
263
264 /* R1 to R15 - R0 is not included as it is the SP. */
265 "POPM R1-R15 \n" \
266
267 /* This pops the remaining registers. */
268 "RTE \n" \
269 "NOP \n" \
270 "NOP \n"
271 );
272 }
273 /*-----------------------------------------------------------*/
274
vSoftwareInterruptISR(void)275 void vSoftwareInterruptISR( void )
276 {
277 __asm volatile
278 (
279 /* Re-enable interrupts. */
280 "SETPSW I \n" \
281
282 /* Move the data that was automatically pushed onto the interrupt stack when
283 the interrupt occurred from the interrupt stack to the user stack.
284
285 R15 is saved before it is clobbered. */
286 "PUSH.L R15 \n" \
287
288 /* Read the user stack pointer. */
289 "MVFC USP, R15 \n" \
290
291 /* Move the address down to the data being moved. */
292 "SUB #12, R15 \n" \
293 "MVTC R15, USP \n" \
294
295 /* Copy the data across, R15, then PC, then PSW. */
296 "MOV.L [ R0 ], [ R15 ] \n" \
297 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
298 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
299
300 /* Move the interrupt stack pointer to its new correct position. */
301 "ADD #12, R0 \n" \
302
303 /* All the rest of the registers are saved directly to the user stack. */
304 "SETPSW U \n" \
305
306 /* Save the rest of the general registers (R15 has been saved already). */
307 "PUSHM R1-R14 \n" \
308
309 /* Save the FPSW and accumulator. */
310 "MVFC FPSW, R15 \n" \
311 "PUSH.L R15 \n" \
312 "MVFACGU #0, A1, R15 \n" \
313 "PUSH.L R15 \n" \
314 "MVFACHI #0, A1, R15 \n" \
315 "PUSH.L R15 \n" \
316 /* Low order word. */
317 "MVFACLO #0, A1, R15 \n" \
318 "PUSH.L R15 \n" \
319 "MVFACGU #0, A0, R15 \n" \
320 "PUSH.L R15 \n" \
321 "MVFACHI #0, A0, R15 \n" \
322 "PUSH.L R15 \n" \
323 /* Low order word. */
324 "MVFACLO #0, A0, R15 \n" \
325 "PUSH.L R15 \n" \
326
327 /* Save the stack pointer to the TCB. */
328 "MOV.L #_pxCurrentTCB, R15 \n" \
329 "MOV.L [ R15 ], R15 \n" \
330 "MOV.L R0, [ R15 ] \n" \
331
332 /* Ensure the interrupt mask is set to the syscall priority while the kernel
333 structures are being accessed. */
334 "MVTIPL %0 \n" \
335
336 /* Select the next task to run. */
337 "BSR.A _vTaskSwitchContext \n" \
338
339 /* Reset the interrupt mask as no more data structure access is required. */
340 "MVTIPL %1 \n" \
341
342 /* Load the stack pointer of the task that is now selected as the Running
343 state task from its TCB. */
344 "MOV.L #_pxCurrentTCB,R15 \n" \
345 "MOV.L [ R15 ], R15 \n" \
346 "MOV.L [ R15 ], R0 \n" \
347
348 /* Restore the context of the new task. The PSW (Program Status Word) and
349 PC will be popped by the RTE instruction. */
350 "POP R15 \n" \
351
352 /* Accumulator low 32 bits. */
353 "MVTACLO R15, A0 \n" \
354 "POP R15 \n" \
355
356 /* Accumulator high 32 bits. */
357 "MVTACHI R15, A0 \n" \
358 "POP R15 \n" \
359
360 /* Accumulator guard. */
361 "MVTACGU R15, A0 \n" \
362 "POP R15 \n" \
363
364 /* Accumulator low 32 bits. */
365 "MVTACLO R15, A1 \n" \
366 "POP R15 \n" \
367
368 /* Accumulator high 32 bits. */
369 "MVTACHI R15, A1 \n" \
370 "POP R15 \n" \
371
372 /* Accumulator guard. */
373 "MVTACGU R15, A1 \n" \
374 "POP R15 \n" \
375 "MVTC R15, FPSW \n" \
376 "POPM R1-R15 \n" \
377 "RTE \n" \
378 "NOP \n" \
379 "NOP "
380 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
381 );
382 }
383 /*-----------------------------------------------------------*/
384
vTickISR(void)385 void vTickISR( void )
386 {
387 /* Re-enabled interrupts. */
388 __asm volatile( "SETPSW I" );
389
390 /* Increment the tick, and perform any processing the new tick value
391 necessitates. Ensure IPL is at the max syscall value first. */
392 portMASK_INTERRUPTS_FROM_KERNEL_ISR();
393 {
394 if( xTaskIncrementTick() != pdFALSE )
395 {
396 taskYIELD();
397 }
398 }
399 portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
400 }
401 /*-----------------------------------------------------------*/
402
ulPortGetIPL(void)403 uint32_t ulPortGetIPL( void )
404 {
405 __asm volatile
406 (
407 "MVFC PSW, R1 \n" \
408 "SHLR #24, R1 \n" \
409 "RTS "
410 );
411
412 /* This will never get executed, but keeps the compiler from complaining. */
413 return 0;
414 }
415 /*-----------------------------------------------------------*/
416
vPortSetIPL(uint32_t ulNewIPL)417 void vPortSetIPL( uint32_t ulNewIPL )
418 {
419 /* Avoid compiler warning about unreferenced parameter. */
420 ( void ) ulNewIPL;
421
422 __asm volatile
423 (
424 "PUSH R5 \n" \
425 "MVFC PSW, R5 \n" \
426 "SHLL #24, R1 \n" \
427 "AND #-0F000001H, R5 \n" \
428 "OR R1, R5 \n" \
429 "MVTC R5, PSW \n" \
430 "POP R5 \n" \
431 "RTS "
432 );
433 }
434
