1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the SH2A port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 /* Library includes. */
38 #include "string.h"
39
40 /* Hardware specifics. */
41 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
42
43 #include "platform.h"
44
45 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
46
47 #include "iodefine.h"
48
49 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
50
51
52 /*-----------------------------------------------------------*/
53
54 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
55 * PSW is set with U and I set, and PM and IPL clear. */
56 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
57 #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
58
59 /* These macros allow a critical section to be added around the call to
60 * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
61 * priority - ie a known priority. Therefore these local macros are a slight
62 * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
63 * which would require the old IPL to be read first and stored in a local variable. */
64 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
65 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
66
67 /*-----------------------------------------------------------*/
68
69 /*
70 * Function to start the first task executing - written in asm code as direct
71 * access to registers is required.
72 */
73 static void prvStartFirstTask( void ) __attribute__( ( naked ) );
74
75 /*
76 * Software interrupt handler. Performs the actual context switch (saving and
77 * restoring of registers). Written in asm code as direct register access is
78 * required.
79 */
80 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
81
82 R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
83 R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
84
85 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
86
87 void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
88
89 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
90
91 /*
92 * The tick ISR handler. The peripheral used is configured by the application
93 * via a hook/callback function.
94 */
95 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
96
97 R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
98 R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
99
100 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
101
102 void vTickISR( void ) __attribute__( ( interrupt ) );
103
104 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
105
106 /*-----------------------------------------------------------*/
107
108 extern void * pxCurrentTCB;
109
110 /*-----------------------------------------------------------*/
111
112 /*
113 * See header file for description.
114 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)115 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
116 TaskFunction_t pxCode,
117 void * pvParameters )
118 {
119 /* R0 is not included as it is the stack pointer. */
120
121 *pxTopOfStack = 0x00;
122 pxTopOfStack--;
123 *pxTopOfStack = portINITIAL_PSW;
124 pxTopOfStack--;
125 *pxTopOfStack = ( StackType_t ) pxCode;
126
127 /* When debugging it can be useful if every register is set to a known
128 * value. Otherwise code space can be saved by just setting the registers
129 * that need to be set. */
130 #ifdef USE_FULL_REGISTER_INITIALISATION
131 {
132 pxTopOfStack--;
133 *pxTopOfStack = 0xffffffff; /* r15. */
134 pxTopOfStack--;
135 *pxTopOfStack = 0xeeeeeeee;
136 pxTopOfStack--;
137 *pxTopOfStack = 0xdddddddd;
138 pxTopOfStack--;
139 *pxTopOfStack = 0xcccccccc;
140 pxTopOfStack--;
141 *pxTopOfStack = 0xbbbbbbbb;
142 pxTopOfStack--;
143 *pxTopOfStack = 0xaaaaaaaa;
144 pxTopOfStack--;
145 *pxTopOfStack = 0x99999999;
146 pxTopOfStack--;
147 *pxTopOfStack = 0x88888888;
148 pxTopOfStack--;
149 *pxTopOfStack = 0x77777777;
150 pxTopOfStack--;
151 *pxTopOfStack = 0x66666666;
152 pxTopOfStack--;
153 *pxTopOfStack = 0x55555555;
154 pxTopOfStack--;
155 *pxTopOfStack = 0x44444444;
156 pxTopOfStack--;
157 *pxTopOfStack = 0x33333333;
158 pxTopOfStack--;
159 *pxTopOfStack = 0x22222222;
160 pxTopOfStack--;
161 }
162 #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
163 {
164 pxTopOfStack -= 15;
165 }
166 #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
167
168 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
169 pxTopOfStack--;
170 *pxTopOfStack = portINITIAL_FPSW;
171 pxTopOfStack--;
172 *pxTopOfStack = 0x12345678; /* Accumulator. */
173 pxTopOfStack--;
174 *pxTopOfStack = 0x87654321; /* Accumulator. */
175
176 return pxTopOfStack;
177 }
178 /*-----------------------------------------------------------*/
179
xPortStartScheduler(void)180 BaseType_t xPortStartScheduler( void )
181 {
182 extern void vApplicationSetupTimerInterrupt( void );
183
184 /* Use pxCurrentTCB just so it does not get optimised away. */
185 if( pxCurrentTCB != NULL )
186 {
187 /* Call an application function to set up the timer that will generate the
188 * tick interrupt. This way the application can decide which peripheral to
189 * use. A demo application is provided to show a suitable example. */
190 vApplicationSetupTimerInterrupt();
191
192 /* Enable the software interrupt. */
193 _IEN( _ICU_SWINT ) = 1;
194
195 /* Ensure the software interrupt is clear. */
196 _IR( _ICU_SWINT ) = 0;
197
198 /* Ensure the software interrupt is set to the kernel priority. */
199 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
200
201 /* Start the first task. */
202 prvStartFirstTask();
203 }
204
205 /* Should not get here. */
206 return pdFAIL;
207 }
208 /*-----------------------------------------------------------*/
209
vPortEndScheduler(void)210 void vPortEndScheduler( void )
211 {
212 /* Not implemented in ports where there is nothing to return to.
213 * Artificially force an assert. */
214 configASSERT( pxCurrentTCB == NULL );
215 }
216 /*-----------------------------------------------------------*/
217
prvStartFirstTask(void)218 static void prvStartFirstTask( void )
219 {
220 __asm volatile
221 (
222
223 /* When starting the scheduler there is nothing that needs moving to the
224 * interrupt stack because the function is not called from an interrupt.
225 * Just ensure the current stack is the user stack. */
226 "SETPSW U \n" \
227
228
229 /* Obtain the location of the stack associated with which ever task
230 * pxCurrentTCB is currently pointing to. */
231 "MOV.L #_pxCurrentTCB, R15 \n" \
232 "MOV.L [R15], R15 \n" \
233 "MOV.L [R15], R0 \n" \
234
235
236 /* Restore the registers from the stack of the task pointed to by
237 * pxCurrentTCB. */
238 "POP R15 \n" \
239
240 /* Accumulator low 32 bits. */
241 "MVTACLO R15 \n" \
242 "POP R15 \n" \
243
244 /* Accumulator high 32 bits. */
245 "MVTACHI R15 \n" \
246 "POP R15 \n" \
247
248 /* Floating point status word. */
249 "MVTC R15, FPSW \n" \
250
251 /* R1 to R15 - R0 is not included as it is the SP. */
252 "POPM R1-R15 \n" \
253
254 /* This pops the remaining registers. */
255 "RTE \n" \
256 "NOP \n" \
257 "NOP \n"
258 );
259 }
260 /*-----------------------------------------------------------*/
261
vSoftwareInterruptISR(void)262 void vSoftwareInterruptISR( void )
263 {
264 __asm volatile
265 (
266 /* Re-enable interrupts. */
267 "SETPSW I \n" \
268
269
270 /* Move the data that was automatically pushed onto the interrupt stack when
271 * the interrupt occurred from the interrupt stack to the user stack.
272 *
273 * R15 is saved before it is clobbered. */
274 "PUSH.L R15 \n" \
275
276 /* Read the user stack pointer. */
277 "MVFC USP, R15 \n" \
278
279 /* Move the address down to the data being moved. */
280 "SUB #12, R15 \n" \
281 "MVTC R15, USP \n" \
282
283 /* Copy the data across, R15, then PC, then PSW. */
284 "MOV.L [ R0 ], [ R15 ] \n" \
285 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
286 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
287
288 /* Move the interrupt stack pointer to its new correct position. */
289 "ADD #12, R0 \n" \
290
291 /* All the rest of the registers are saved directly to the user stack. */
292 "SETPSW U \n" \
293
294 /* Save the rest of the general registers (R15 has been saved already). */
295 "PUSHM R1-R14 \n" \
296
297 /* Save the FPSW and accumulator. */
298 "MVFC FPSW, R15 \n" \
299 "PUSH.L R15 \n" \
300 "MVFACHI R15 \n" \
301 "PUSH.L R15 \n" \
302
303 /* Middle word. */
304 "MVFACMI R15 \n" \
305
306 /* Shifted left as it is restored to the low order word. */
307 "SHLL #16, R15 \n" \
308 "PUSH.L R15 \n" \
309
310 /* Save the stack pointer to the TCB. */
311 "MOV.L #_pxCurrentTCB, R15 \n" \
312 "MOV.L [ R15 ], R15 \n" \
313 "MOV.L R0, [ R15 ] \n" \
314
315
316 /* Ensure the interrupt mask is set to the syscall priority while the kernel
317 * structures are being accessed. */
318 "MVTIPL %0 \n" \
319
320 /* Select the next task to run. */
321 "BSR.A _vTaskSwitchContext \n" \
322
323 /* Reset the interrupt mask as no more data structure access is required. */
324 "MVTIPL %1 \n" \
325
326
327 /* Load the stack pointer of the task that is now selected as the Running
328 * state task from its TCB. */
329 "MOV.L #_pxCurrentTCB,R15 \n" \
330 "MOV.L [ R15 ], R15 \n" \
331 "MOV.L [ R15 ], R0 \n" \
332
333
334 /* Restore the context of the new task. The PSW (Program Status Word) and
335 * PC will be popped by the RTE instruction. */
336 "POP R15 \n" \
337 "MVTACLO R15 \n" \
338 "POP R15 \n" \
339 "MVTACHI R15 \n" \
340 "POP R15 \n" \
341 "MVTC R15, FPSW \n" \
342 "POPM R1-R15 \n" \
343 "RTE \n" \
344 "NOP \n" \
345 "NOP "
346 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
347 );
348 }
349 /*-----------------------------------------------------------*/
350
vTickISR(void)351 void vTickISR( void )
352 {
353 /* Re-enabled interrupts. */
354 __asm volatile ( "SETPSW I" );
355
356 /* Increment the tick, and perform any processing the new tick value
357 * necessitates. Ensure IPL is at the max syscall value first. */
358 portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
359 {
360 if( xTaskIncrementTick() != pdFALSE )
361 {
362 taskYIELD();
363 }
364 }
365 portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
366 }
367 /*-----------------------------------------------------------*/
368
ulPortGetIPL(void)369 uint32_t ulPortGetIPL( void )
370 {
371 __asm volatile
372 (
373 "MVFC PSW, R1 \n" \
374 "SHLR #24, R1 \n" \
375 "RTS "
376 );
377
378 /* This will never get executed, but keeps the compiler from complaining. */
379 return 0;
380 }
381 /*-----------------------------------------------------------*/
382
vPortSetIPL(uint32_t ulNewIPL)383 void vPortSetIPL( uint32_t ulNewIPL )
384 {
385 /* Avoid compiler warning about unreferenced parameter. */
386 ( void ) ulNewIPL;
387
388 __asm volatile
389 (
390 "PUSH R5 \n" \
391 "MVFC PSW, R5 \n" \
392 "SHLL #24, R1 \n" \
393 "AND #-0F000001H, R5 \n" \
394 "OR R1, R5 \n" \
395 "MVTC R5, PSW \n" \
396 "POP R5 \n" \
397 "RTS "
398 );
399 }
400
