1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the SH2A port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 /* Library includes. */
38 #include "string.h"
39
40 /* Hardware specifics. */
41 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
42
43 #include "platform.h"
44
45 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
46
47 #include "iodefine.h"
48
49 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
50
51
52 /*-----------------------------------------------------------*/
53
54 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
55 PSW is set with U and I set, and PM and IPL clear. */
56 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
57 #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
58
59 /* These macros allow a critical section to be added around the call to
60 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
61 priority - ie a known priority. Therefore these local macros are a slight
62 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
63 which would require the old IPL to be read first and stored in a local variable. */
64 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
65 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
66
67 /*-----------------------------------------------------------*/
68
69 /*
70 * Function to start the first task executing - written in asm code as direct
71 * access to registers is required.
72 */
73 static void prvStartFirstTask( void ) __attribute__((naked));
74 /*
75 * Software interrupt handler. Performs the actual context switch (saving and
76 * restoring of registers). Written in asm code as direct register access is
77 * required.
78 */
79 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
80
81 R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
82 R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
83
84 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
85
86 void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
87
88 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
89
90 /*
91 * The tick ISR handler. The peripheral used is configured by the application
92 * via a hook/callback function.
93 */
94 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
95
96 R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
97 R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
98
99 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
100
101 void vTickISR( void ) __attribute__( ( interrupt ) );
102
103 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
104
105 /*-----------------------------------------------------------*/
106
107 extern void *pxCurrentTCB;
108
109 /*-----------------------------------------------------------*/
110
111 /*
112 * See header file for description.
113 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)114 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
115 {
116 /* R0 is not included as it is the stack pointer. */
117
118 *pxTopOfStack = 0x00;
119 pxTopOfStack--;
120 *pxTopOfStack = portINITIAL_PSW;
121 pxTopOfStack--;
122 *pxTopOfStack = ( StackType_t ) pxCode;
123
124 /* When debugging it can be useful if every register is set to a known
125 value. Otherwise code space can be saved by just setting the registers
126 that need to be set. */
127 #ifdef USE_FULL_REGISTER_INITIALISATION
128 {
129 pxTopOfStack--;
130 *pxTopOfStack = 0xffffffff; /* r15. */
131 pxTopOfStack--;
132 *pxTopOfStack = 0xeeeeeeee;
133 pxTopOfStack--;
134 *pxTopOfStack = 0xdddddddd;
135 pxTopOfStack--;
136 *pxTopOfStack = 0xcccccccc;
137 pxTopOfStack--;
138 *pxTopOfStack = 0xbbbbbbbb;
139 pxTopOfStack--;
140 *pxTopOfStack = 0xaaaaaaaa;
141 pxTopOfStack--;
142 *pxTopOfStack = 0x99999999;
143 pxTopOfStack--;
144 *pxTopOfStack = 0x88888888;
145 pxTopOfStack--;
146 *pxTopOfStack = 0x77777777;
147 pxTopOfStack--;
148 *pxTopOfStack = 0x66666666;
149 pxTopOfStack--;
150 *pxTopOfStack = 0x55555555;
151 pxTopOfStack--;
152 *pxTopOfStack = 0x44444444;
153 pxTopOfStack--;
154 *pxTopOfStack = 0x33333333;
155 pxTopOfStack--;
156 *pxTopOfStack = 0x22222222;
157 pxTopOfStack--;
158 }
159 #else
160 {
161 pxTopOfStack -= 15;
162 }
163 #endif
164
165 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
166 pxTopOfStack--;
167 *pxTopOfStack = portINITIAL_FPSW;
168 pxTopOfStack--;
169 *pxTopOfStack = 0x12345678; /* Accumulator. */
170 pxTopOfStack--;
171 *pxTopOfStack = 0x87654321; /* Accumulator. */
172
173 return pxTopOfStack;
174 }
175 /*-----------------------------------------------------------*/
176
xPortStartScheduler(void)177 BaseType_t xPortStartScheduler( void )
178 {
179 extern void vApplicationSetupTimerInterrupt( void );
180
181 /* Use pxCurrentTCB just so it does not get optimised away. */
182 if( pxCurrentTCB != NULL )
183 {
184 /* Call an application function to set up the timer that will generate the
185 tick interrupt. This way the application can decide which peripheral to
186 use. A demo application is provided to show a suitable example. */
187 vApplicationSetupTimerInterrupt();
188
189 /* Enable the software interrupt. */
190 _IEN( _ICU_SWINT ) = 1;
191
192 /* Ensure the software interrupt is clear. */
193 _IR( _ICU_SWINT ) = 0;
194
195 /* Ensure the software interrupt is set to the kernel priority. */
196 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
197
198 /* Start the first task. */
199 prvStartFirstTask();
200 }
201
202 /* Should not get here. */
203 return pdFAIL;
204 }
205 /*-----------------------------------------------------------*/
206
vPortEndScheduler(void)207 void vPortEndScheduler( void )
208 {
209 /* Not implemented in ports where there is nothing to return to.
210 Artificially force an assert. */
211 configASSERT( pxCurrentTCB == NULL );
212 }
213 /*-----------------------------------------------------------*/
214
prvStartFirstTask(void)215 static void prvStartFirstTask( void )
216 {
217 __asm volatile
218 (
219 /* When starting the scheduler there is nothing that needs moving to the
220 interrupt stack because the function is not called from an interrupt.
221 Just ensure the current stack is the user stack. */
222 "SETPSW U \n" \
223
224 /* Obtain the location of the stack associated with which ever task
225 pxCurrentTCB is currently pointing to. */
226 "MOV.L #_pxCurrentTCB, R15 \n" \
227 "MOV.L [R15], R15 \n" \
228 "MOV.L [R15], R0 \n" \
229
230 /* Restore the registers from the stack of the task pointed to by
231 pxCurrentTCB. */
232 "POP R15 \n" \
233
234 /* Accumulator low 32 bits. */
235 "MVTACLO R15 \n" \
236 "POP R15 \n" \
237
238 /* Accumulator high 32 bits. */
239 "MVTACHI R15 \n" \
240 "POP R15 \n" \
241
242 /* Floating point status word. */
243 "MVTC R15, FPSW \n" \
244
245 /* R1 to R15 - R0 is not included as it is the SP. */
246 "POPM R1-R15 \n" \
247
248 /* This pops the remaining registers. */
249 "RTE \n" \
250 "NOP \n" \
251 "NOP \n"
252 );
253 }
254 /*-----------------------------------------------------------*/
255
vSoftwareInterruptISR(void)256 void vSoftwareInterruptISR( void )
257 {
258 __asm volatile
259 (
260 /* Re-enable interrupts. */
261 "SETPSW I \n" \
262
263 /* Move the data that was automatically pushed onto the interrupt stack when
264 the interrupt occurred from the interrupt stack to the user stack.
265
266 R15 is saved before it is clobbered. */
267 "PUSH.L R15 \n" \
268
269 /* Read the user stack pointer. */
270 "MVFC USP, R15 \n" \
271
272 /* Move the address down to the data being moved. */
273 "SUB #12, R15 \n" \
274 "MVTC R15, USP \n" \
275
276 /* Copy the data across, R15, then PC, then PSW. */
277 "MOV.L [ R0 ], [ R15 ] \n" \
278 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
279 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
280
281 /* Move the interrupt stack pointer to its new correct position. */
282 "ADD #12, R0 \n" \
283
284 /* All the rest of the registers are saved directly to the user stack. */
285 "SETPSW U \n" \
286
287 /* Save the rest of the general registers (R15 has been saved already). */
288 "PUSHM R1-R14 \n" \
289
290 /* Save the FPSW and accumulator. */
291 "MVFC FPSW, R15 \n" \
292 "PUSH.L R15 \n" \
293 "MVFACHI R15 \n" \
294 "PUSH.L R15 \n" \
295
296 /* Middle word. */
297 "MVFACMI R15 \n" \
298
299 /* Shifted left as it is restored to the low order word. */
300 "SHLL #16, R15 \n" \
301 "PUSH.L R15 \n" \
302
303 /* Save the stack pointer to the TCB. */
304 "MOV.L #_pxCurrentTCB, R15 \n" \
305 "MOV.L [ R15 ], R15 \n" \
306 "MOV.L R0, [ R15 ] \n" \
307
308 /* Ensure the interrupt mask is set to the syscall priority while the kernel
309 structures are being accessed. */
310 "MVTIPL %0 \n" \
311
312 /* Select the next task to run. */
313 "BSR.A _vTaskSwitchContext \n" \
314
315 /* Reset the interrupt mask as no more data structure access is required. */
316 "MVTIPL %1 \n" \
317
318 /* Load the stack pointer of the task that is now selected as the Running
319 state task from its TCB. */
320 "MOV.L #_pxCurrentTCB,R15 \n" \
321 "MOV.L [ R15 ], R15 \n" \
322 "MOV.L [ R15 ], R0 \n" \
323
324 /* Restore the context of the new task. The PSW (Program Status Word) and
325 PC will be popped by the RTE instruction. */
326 "POP R15 \n" \
327 "MVTACLO R15 \n" \
328 "POP R15 \n" \
329 "MVTACHI R15 \n" \
330 "POP R15 \n" \
331 "MVTC R15, FPSW \n" \
332 "POPM R1-R15 \n" \
333 "RTE \n" \
334 "NOP \n" \
335 "NOP "
336 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
337 );
338 }
339 /*-----------------------------------------------------------*/
340
vTickISR(void)341 void vTickISR( void )
342 {
343 /* Re-enabled interrupts. */
344 __asm volatile( "SETPSW I" );
345
346 /* Increment the tick, and perform any processing the new tick value
347 necessitates. Ensure IPL is at the max syscall value first. */
348 portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
349 {
350 if( xTaskIncrementTick() != pdFALSE )
351 {
352 taskYIELD();
353 }
354 }
355 portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
356 }
357 /*-----------------------------------------------------------*/
358
ulPortGetIPL(void)359 uint32_t ulPortGetIPL( void )
360 {
361 __asm volatile
362 (
363 "MVFC PSW, R1 \n" \
364 "SHLR #24, R1 \n" \
365 "RTS "
366 );
367
368 /* This will never get executed, but keeps the compiler from complaining. */
369 return 0;
370 }
371 /*-----------------------------------------------------------*/
372
vPortSetIPL(uint32_t ulNewIPL)373 void vPortSetIPL( uint32_t ulNewIPL )
374 {
375 /* Avoid compiler warning about unreferenced parameter. */
376 ( void ) ulNewIPL;
377
378 __asm volatile
379 (
380 "PUSH R5 \n" \
381 "MVFC PSW, R5 \n" \
382 "SHLL #24, R1 \n" \
383 "AND #-0F000001H, R5 \n" \
384 "OR R1, R5 \n" \
385 "MVTC R5, PSW \n" \
386 "POP R5 \n" \
387 "RTS "
388 );
389 }
390
