1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the SH2A port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 /* Library includes. */
38 #include "string.h"
39
40 /* Hardware specifics. */
41 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
42
43 #include "platform.h"
44
45 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
46
47 #include "iodefine.h"
48
49 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
50
51 /*-----------------------------------------------------------*/
52
53 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
54 * PSW is set with U and I set, and PM and IPL clear. */
55 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
56 #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
57
58 /* These macros allow a critical section to be added around the call to
59 * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
60 * priority - ie a known priority. Therefore these local macros are a slight
61 * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
62 * which would require the old IPL to be read first and stored in a local variable. */
63 #define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
64 #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
65
66 /*-----------------------------------------------------------*/
67
68 /*
69 * Function to start the first task executing - written in asm code as direct
70 * access to registers is required.
71 */
72 static void prvStartFirstTask( void ) __attribute__( ( naked ) );
73
74
75 /*
76 * Software interrupt handler. Performs the actual context switch (saving and
77 * restoring of registers). Written in asm code as direct register access is
78 * required.
79 */
80 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
81
82 R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
83 R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
84
85 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
86
87 void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
88
89 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
90
91 /*
92 * The tick ISR handler. The peripheral used is configured by the application
93 * via a hook/callback function.
94 */
95 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
96
97 R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
98 R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
99
100 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
101
102 void vTickISR( void ) __attribute__( ( interrupt ) );
103
104 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
105
106 /*-----------------------------------------------------------*/
107
108 extern void * pxCurrentTCB;
109
110 /*-----------------------------------------------------------*/
111
112 /*
113 * See header file for description.
114 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)115 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
116 TaskFunction_t pxCode,
117 void * pvParameters )
118 {
119 /* R0 is not included as it is the stack pointer. */
120
121 *pxTopOfStack = 0x00;
122 pxTopOfStack--;
123 *pxTopOfStack = portINITIAL_PSW;
124 pxTopOfStack--;
125 *pxTopOfStack = ( StackType_t ) pxCode;
126
127 /* When debugging it can be useful if every register is set to a known
128 * value. Otherwise code space can be saved by just setting the registers
129 * that need to be set. */
130 #ifdef USE_FULL_REGISTER_INITIALISATION
131 {
132 pxTopOfStack--;
133 *pxTopOfStack = 0xffffffff; /* r15. */
134 pxTopOfStack--;
135 *pxTopOfStack = 0xeeeeeeee;
136 pxTopOfStack--;
137 *pxTopOfStack = 0xdddddddd;
138 pxTopOfStack--;
139 *pxTopOfStack = 0xcccccccc;
140 pxTopOfStack--;
141 *pxTopOfStack = 0xbbbbbbbb;
142 pxTopOfStack--;
143 *pxTopOfStack = 0xaaaaaaaa;
144 pxTopOfStack--;
145 *pxTopOfStack = 0x99999999;
146 pxTopOfStack--;
147 *pxTopOfStack = 0x88888888;
148 pxTopOfStack--;
149 *pxTopOfStack = 0x77777777;
150 pxTopOfStack--;
151 *pxTopOfStack = 0x66666666;
152 pxTopOfStack--;
153 *pxTopOfStack = 0x55555555;
154 pxTopOfStack--;
155 *pxTopOfStack = 0x44444444;
156 pxTopOfStack--;
157 *pxTopOfStack = 0x33333333;
158 pxTopOfStack--;
159 *pxTopOfStack = 0x22222222;
160 pxTopOfStack--;
161 }
162 #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
163 {
164 pxTopOfStack -= 15;
165 }
166 #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
167
168 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
169 pxTopOfStack--;
170 *pxTopOfStack = portINITIAL_FPSW;
171 pxTopOfStack--;
172 *pxTopOfStack = 0x11111111; /* Accumulator 0. */
173 pxTopOfStack--;
174 *pxTopOfStack = 0x22222222; /* Accumulator 0. */
175 pxTopOfStack--;
176 *pxTopOfStack = 0x33333333; /* Accumulator 0. */
177 pxTopOfStack--;
178 *pxTopOfStack = 0x44444444; /* Accumulator 1. */
179 pxTopOfStack--;
180 *pxTopOfStack = 0x55555555; /* Accumulator 1. */
181 pxTopOfStack--;
182 *pxTopOfStack = 0x66666666; /* Accumulator 1. */
183
184 return pxTopOfStack;
185 }
186 /*-----------------------------------------------------------*/
187
xPortStartScheduler(void)188 BaseType_t xPortStartScheduler( void )
189 {
190 extern void vApplicationSetupTimerInterrupt( void );
191
192 /* Use pxCurrentTCB just so it does not get optimised away. */
193 if( pxCurrentTCB != NULL )
194 {
195 /* Call an application function to set up the timer that will generate the
196 * tick interrupt. This way the application can decide which peripheral to
197 * use. A demo application is provided to show a suitable example. */
198 vApplicationSetupTimerInterrupt();
199
200 /* Enable the software interrupt. */
201 _IEN( _ICU_SWINT ) = 1;
202
203 /* Ensure the software interrupt is clear. */
204 _IR( _ICU_SWINT ) = 0;
205
206 /* Ensure the software interrupt is set to the kernel priority. */
207 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
208
209 /* Start the first task. */
210 prvStartFirstTask();
211 }
212
213 /* Should not get here. */
214 return pdFAIL;
215 }
216 /*-----------------------------------------------------------*/
217
vPortEndScheduler(void)218 void vPortEndScheduler( void )
219 {
220 /* Not implemented in ports where there is nothing to return to.
221 * Artificially force an assert. */
222 configASSERT( pxCurrentTCB == NULL );
223 }
224 /*-----------------------------------------------------------*/
225
prvStartFirstTask(void)226 static void prvStartFirstTask( void )
227 {
228 __asm volatile
229 (
230
231 /* When starting the scheduler there is nothing that needs moving to the
232 * interrupt stack because the function is not called from an interrupt.
233 * Just ensure the current stack is the user stack. */
234 "SETPSW U \n" \
235
236
237 /* Obtain the location of the stack associated with which ever task
238 * pxCurrentTCB is currently pointing to. */
239 "MOV.L #_pxCurrentTCB, R15 \n" \
240 "MOV.L [R15], R15 \n" \
241 "MOV.L [R15], R0 \n" \
242
243
244 /* Restore the registers from the stack of the task pointed to by
245 * pxCurrentTCB. */
246 "POP R15 \n" \
247
248 /* Accumulator low 32 bits. */
249 "MVTACLO R15, A0 \n" \
250 "POP R15 \n" \
251
252 /* Accumulator high 32 bits. */
253 "MVTACHI R15, A0 \n" \
254 "POP R15 \n" \
255
256 /* Accumulator guard. */
257 "MVTACGU R15, A0 \n" \
258 "POP R15 \n" \
259
260 /* Accumulator low 32 bits. */
261 "MVTACLO R15, A1 \n" \
262 "POP R15 \n" \
263
264 /* Accumulator high 32 bits. */
265 "MVTACHI R15, A1 \n" \
266 "POP R15 \n" \
267
268 /* Accumulator guard. */
269 "MVTACGU R15, A1 \n" \
270 "POP R15 \n" \
271
272 /* Floating point status word. */
273 "MVTC R15, FPSW \n" \
274
275 /* R1 to R15 - R0 is not included as it is the SP. */
276 "POPM R1-R15 \n" \
277
278 /* This pops the remaining registers. */
279 "RTE \n" \
280 "NOP \n" \
281 "NOP \n"
282 );
283 }
284 /*-----------------------------------------------------------*/
285
vSoftwareInterruptISR(void)286 void vSoftwareInterruptISR( void )
287 {
288 __asm volatile
289 (
290 /* Re-enable interrupts. */
291 "SETPSW I \n" \
292
293
294 /* Move the data that was automatically pushed onto the interrupt stack when
295 * the interrupt occurred from the interrupt stack to the user stack.
296 *
297 * R15 is saved before it is clobbered. */
298 "PUSH.L R15 \n" \
299
300 /* Read the user stack pointer. */
301 "MVFC USP, R15 \n" \
302
303 /* Move the address down to the data being moved. */
304 "SUB #12, R15 \n" \
305 "MVTC R15, USP \n" \
306
307 /* Copy the data across, R15, then PC, then PSW. */
308 "MOV.L [ R0 ], [ R15 ] \n" \
309 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
310 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
311
312 /* Move the interrupt stack pointer to its new correct position. */
313 "ADD #12, R0 \n" \
314
315 /* All the rest of the registers are saved directly to the user stack. */
316 "SETPSW U \n" \
317
318 /* Save the rest of the general registers (R15 has been saved already). */
319 "PUSHM R1-R14 \n" \
320
321 /* Save the FPSW and accumulator. */
322 "MVFC FPSW, R15 \n" \
323 "PUSH.L R15 \n" \
324 "MVFACGU #0, A1, R15 \n" \
325 "PUSH.L R15 \n" \
326 "MVFACHI #0, A1, R15 \n" \
327 "PUSH.L R15 \n" \
328 /* Low order word. */
329 "MVFACLO #0, A1, R15 \n" \
330 "PUSH.L R15 \n" \
331 "MVFACGU #0, A0, R15 \n" \
332 "PUSH.L R15 \n" \
333 "MVFACHI #0, A0, R15 \n" \
334 "PUSH.L R15 \n" \
335 /* Low order word. */
336 "MVFACLO #0, A0, R15 \n" \
337 "PUSH.L R15 \n" \
338
339 /* Save the stack pointer to the TCB. */
340 "MOV.L #_pxCurrentTCB, R15 \n" \
341 "MOV.L [ R15 ], R15 \n" \
342 "MOV.L R0, [ R15 ] \n" \
343
344
345 /* Ensure the interrupt mask is set to the syscall priority while the kernel
346 * structures are being accessed. */
347 "MVTIPL %0 \n" \
348
349 /* Select the next task to run. */
350 "BSR.A _vTaskSwitchContext \n" \
351
352 /* Reset the interrupt mask as no more data structure access is required. */
353 "MVTIPL %1 \n" \
354
355
356 /* Load the stack pointer of the task that is now selected as the Running
357 * state task from its TCB. */
358 "MOV.L #_pxCurrentTCB,R15 \n" \
359 "MOV.L [ R15 ], R15 \n" \
360 "MOV.L [ R15 ], R0 \n" \
361
362
363 /* Restore the context of the new task. The PSW (Program Status Word) and
364 * PC will be popped by the RTE instruction. */
365 "POP R15 \n" \
366
367 /* Accumulator low 32 bits. */
368 "MVTACLO R15, A0 \n" \
369 "POP R15 \n" \
370
371 /* Accumulator high 32 bits. */
372 "MVTACHI R15, A0 \n" \
373 "POP R15 \n" \
374
375 /* Accumulator guard. */
376 "MVTACGU R15, A0 \n" \
377 "POP R15 \n" \
378
379 /* Accumulator low 32 bits. */
380 "MVTACLO R15, A1 \n" \
381 "POP R15 \n" \
382
383 /* Accumulator high 32 bits. */
384 "MVTACHI R15, A1 \n" \
385 "POP R15 \n" \
386
387 /* Accumulator guard. */
388 "MVTACGU R15, A1 \n" \
389 "POP R15 \n" \
390 "MVTC R15, FPSW \n" \
391 "POPM R1-R15 \n" \
392 "RTE \n" \
393 "NOP \n" \
394 "NOP "
395 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
396 );
397 }
398 /*-----------------------------------------------------------*/
399
vTickISR(void)400 void vTickISR( void )
401 {
402 /* Re-enabled interrupts. */
403 __asm volatile ( "SETPSW I" );
404
405 /* Increment the tick, and perform any processing the new tick value
406 * necessitates. Ensure IPL is at the max syscall value first. */
407 portMASK_INTERRUPTS_FROM_KERNEL_ISR();
408 {
409 if( xTaskIncrementTick() != pdFALSE )
410 {
411 taskYIELD();
412 }
413 }
414 portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
415 }
416 /*-----------------------------------------------------------*/
417
ulPortGetIPL(void)418 uint32_t ulPortGetIPL( void )
419 {
420 __asm volatile
421 (
422 "MVFC PSW, R1 \n" \
423 "SHLR #24, R1 \n" \
424 "RTS "
425 );
426
427 /* This will never get executed, but keeps the compiler from complaining. */
428 return 0;
429 }
430 /*-----------------------------------------------------------*/
431
vPortSetIPL(uint32_t ulNewIPL)432 void vPortSetIPL( uint32_t ulNewIPL )
433 {
434 __asm volatile
435 (
436 "PUSH R5 \n" \
437 "MVFC PSW, R5 \n" \
438 "SHLL #24, R1 \n" \
439 "AND #-0F000001H, R5 \n" \
440 "OR R1, R5 \n" \
441 "MVTC R5, PSW \n" \
442 "POP R5 \n" \
443 "RTS "
444 );
445 }
446
