1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the SH2A port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 /* Library includes. */
38 #include "string.h"
39
40 /* Hardware specifics. */
41 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
42
43 #include "platform.h"
44
45 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
46
47 #include "iodefine.h"
48
49 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
50
51 /*-----------------------------------------------------------*/
52
53 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
54 PSW is set with U and I set, and PM and IPL clear. */
55 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
56 #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
57
58 /* These macros allow a critical section to be added around the call to
59 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
60 priority - ie a known priority. Therefore these local macros are a slight
61 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
62 which would require the old IPL to be read first and stored in a local variable. */
63 #define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
64 #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
65
66 /*-----------------------------------------------------------*/
67
68 /*
69 * Function to start the first task executing - written in asm code as direct
70 * access to registers is required.
71 */
72 static void prvStartFirstTask( void ) __attribute__((naked));
73
74
75 /*
76 * Software interrupt handler. Performs the actual context switch (saving and
77 * restoring of registers). Written in asm code as direct register access is
78 * required.
79 */
80 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
81
82 R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
83 R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
84
85 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
86
87 void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
88
89 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
90
91 /*
92 * The tick ISR handler. The peripheral used is configured by the application
93 * via a hook/callback function.
94 */
95 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
96
97 R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
98 R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
99
100 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
101
102 void vTickISR( void ) __attribute__( ( interrupt ) );
103
104 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
105
106 /*-----------------------------------------------------------*/
107
108 extern void *pxCurrentTCB;
109
110 /*-----------------------------------------------------------*/
111
112 /*
113 * See header file for description.
114 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)115 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
116 {
117 /* R0 is not included as it is the stack pointer. */
118
119 *pxTopOfStack = 0x00;
120 pxTopOfStack--;
121 *pxTopOfStack = portINITIAL_PSW;
122 pxTopOfStack--;
123 *pxTopOfStack = ( StackType_t ) pxCode;
124
125 /* When debugging it can be useful if every register is set to a known
126 value. Otherwise code space can be saved by just setting the registers
127 that need to be set. */
128 #ifdef USE_FULL_REGISTER_INITIALISATION
129 {
130 pxTopOfStack--;
131 *pxTopOfStack = 0xffffffff; /* r15. */
132 pxTopOfStack--;
133 *pxTopOfStack = 0xeeeeeeee;
134 pxTopOfStack--;
135 *pxTopOfStack = 0xdddddddd;
136 pxTopOfStack--;
137 *pxTopOfStack = 0xcccccccc;
138 pxTopOfStack--;
139 *pxTopOfStack = 0xbbbbbbbb;
140 pxTopOfStack--;
141 *pxTopOfStack = 0xaaaaaaaa;
142 pxTopOfStack--;
143 *pxTopOfStack = 0x99999999;
144 pxTopOfStack--;
145 *pxTopOfStack = 0x88888888;
146 pxTopOfStack--;
147 *pxTopOfStack = 0x77777777;
148 pxTopOfStack--;
149 *pxTopOfStack = 0x66666666;
150 pxTopOfStack--;
151 *pxTopOfStack = 0x55555555;
152 pxTopOfStack--;
153 *pxTopOfStack = 0x44444444;
154 pxTopOfStack--;
155 *pxTopOfStack = 0x33333333;
156 pxTopOfStack--;
157 *pxTopOfStack = 0x22222222;
158 pxTopOfStack--;
159 }
160 #else
161 {
162 pxTopOfStack -= 15;
163 }
164 #endif
165
166 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
167 pxTopOfStack--;
168 *pxTopOfStack = portINITIAL_FPSW;
169 pxTopOfStack--;
170 *pxTopOfStack = 0x11111111; /* Accumulator 0. */
171 pxTopOfStack--;
172 *pxTopOfStack = 0x22222222; /* Accumulator 0. */
173 pxTopOfStack--;
174 *pxTopOfStack = 0x33333333; /* Accumulator 0. */
175 pxTopOfStack--;
176 *pxTopOfStack = 0x44444444; /* Accumulator 1. */
177 pxTopOfStack--;
178 *pxTopOfStack = 0x55555555; /* Accumulator 1. */
179 pxTopOfStack--;
180 *pxTopOfStack = 0x66666666; /* Accumulator 1. */
181
182 return pxTopOfStack;
183 }
184 /*-----------------------------------------------------------*/
185
xPortStartScheduler(void)186 BaseType_t xPortStartScheduler( void )
187 {
188 extern void vApplicationSetupTimerInterrupt( void );
189
190 /* Use pxCurrentTCB just so it does not get optimised away. */
191 if( pxCurrentTCB != NULL )
192 {
193 /* Call an application function to set up the timer that will generate the
194 tick interrupt. This way the application can decide which peripheral to
195 use. A demo application is provided to show a suitable example. */
196 vApplicationSetupTimerInterrupt();
197
198 /* Enable the software interrupt. */
199 _IEN( _ICU_SWINT ) = 1;
200
201 /* Ensure the software interrupt is clear. */
202 _IR( _ICU_SWINT ) = 0;
203
204 /* Ensure the software interrupt is set to the kernel priority. */
205 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
206
207 /* Start the first task. */
208 prvStartFirstTask();
209 }
210
211 /* Should not get here. */
212 return pdFAIL;
213 }
214 /*-----------------------------------------------------------*/
215
vPortEndScheduler(void)216 void vPortEndScheduler( void )
217 {
218 /* Not implemented in ports where there is nothing to return to.
219 Artificially force an assert. */
220 configASSERT( pxCurrentTCB == NULL );
221 }
222 /*-----------------------------------------------------------*/
223
prvStartFirstTask(void)224 static void prvStartFirstTask( void )
225 {
226 __asm volatile
227 (
228 /* When starting the scheduler there is nothing that needs moving to the
229 interrupt stack because the function is not called from an interrupt.
230 Just ensure the current stack is the user stack. */
231 "SETPSW U \n" \
232
233 /* Obtain the location of the stack associated with which ever task
234 pxCurrentTCB is currently pointing to. */
235 "MOV.L #_pxCurrentTCB, R15 \n" \
236 "MOV.L [R15], R15 \n" \
237 "MOV.L [R15], R0 \n" \
238
239 /* Restore the registers from the stack of the task pointed to by
240 pxCurrentTCB. */
241 "POP R15 \n" \
242
243 /* Accumulator low 32 bits. */
244 "MVTACLO R15, A0 \n" \
245 "POP R15 \n" \
246
247 /* Accumulator high 32 bits. */
248 "MVTACHI R15, A0 \n" \
249 "POP R15 \n" \
250
251 /* Accumulator guard. */
252 "MVTACGU R15, A0 \n" \
253 "POP R15 \n" \
254
255 /* Accumulator low 32 bits. */
256 "MVTACLO R15, A1 \n" \
257 "POP R15 \n" \
258
259 /* Accumulator high 32 bits. */
260 "MVTACHI R15, A1 \n" \
261 "POP R15 \n" \
262
263 /* Accumulator guard. */
264 "MVTACGU R15, A1 \n" \
265 "POP R15 \n" \
266
267 /* Floating point status word. */
268 "MVTC R15, FPSW \n" \
269
270 /* R1 to R15 - R0 is not included as it is the SP. */
271 "POPM R1-R15 \n" \
272
273 /* This pops the remaining registers. */
274 "RTE \n" \
275 "NOP \n" \
276 "NOP \n"
277 );
278 }
279 /*-----------------------------------------------------------*/
280
vSoftwareInterruptISR(void)281 void vSoftwareInterruptISR( void )
282 {
283 __asm volatile
284 (
285 /* Re-enable interrupts. */
286 "SETPSW I \n" \
287
288 /* Move the data that was automatically pushed onto the interrupt stack when
289 the interrupt occurred from the interrupt stack to the user stack.
290
291 R15 is saved before it is clobbered. */
292 "PUSH.L R15 \n" \
293
294 /* Read the user stack pointer. */
295 "MVFC USP, R15 \n" \
296
297 /* Move the address down to the data being moved. */
298 "SUB #12, R15 \n" \
299 "MVTC R15, USP \n" \
300
301 /* Copy the data across, R15, then PC, then PSW. */
302 "MOV.L [ R0 ], [ R15 ] \n" \
303 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
304 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
305
306 /* Move the interrupt stack pointer to its new correct position. */
307 "ADD #12, R0 \n" \
308
309 /* All the rest of the registers are saved directly to the user stack. */
310 "SETPSW U \n" \
311
312 /* Save the rest of the general registers (R15 has been saved already). */
313 "PUSHM R1-R14 \n" \
314
315 /* Save the FPSW and accumulator. */
316 "MVFC FPSW, R15 \n" \
317 "PUSH.L R15 \n" \
318 "MVFACGU #0, A1, R15 \n" \
319 "PUSH.L R15 \n" \
320 "MVFACHI #0, A1, R15 \n" \
321 "PUSH.L R15 \n" \
322 /* Low order word. */
323 "MVFACLO #0, A1, R15 \n" \
324 "PUSH.L R15 \n" \
325 "MVFACGU #0, A0, R15 \n" \
326 "PUSH.L R15 \n" \
327 "MVFACHI #0, A0, R15 \n" \
328 "PUSH.L R15 \n" \
329 /* Low order word. */
330 "MVFACLO #0, A0, R15 \n" \
331 "PUSH.L R15 \n" \
332
333 /* Save the stack pointer to the TCB. */
334 "MOV.L #_pxCurrentTCB, R15 \n" \
335 "MOV.L [ R15 ], R15 \n" \
336 "MOV.L R0, [ R15 ] \n" \
337
338 /* Ensure the interrupt mask is set to the syscall priority while the kernel
339 structures are being accessed. */
340 "MVTIPL %0 \n" \
341
342 /* Select the next task to run. */
343 "BSR.A _vTaskSwitchContext \n" \
344
345 /* Reset the interrupt mask as no more data structure access is required. */
346 "MVTIPL %1 \n" \
347
348 /* Load the stack pointer of the task that is now selected as the Running
349 state task from its TCB. */
350 "MOV.L #_pxCurrentTCB,R15 \n" \
351 "MOV.L [ R15 ], R15 \n" \
352 "MOV.L [ R15 ], R0 \n" \
353
354 /* Restore the context of the new task. The PSW (Program Status Word) and
355 PC will be popped by the RTE instruction. */
356 "POP R15 \n" \
357
358 /* Accumulator low 32 bits. */
359 "MVTACLO R15, A0 \n" \
360 "POP R15 \n" \
361
362 /* Accumulator high 32 bits. */
363 "MVTACHI R15, A0 \n" \
364 "POP R15 \n" \
365
366 /* Accumulator guard. */
367 "MVTACGU R15, A0 \n" \
368 "POP R15 \n" \
369
370 /* Accumulator low 32 bits. */
371 "MVTACLO R15, A1 \n" \
372 "POP R15 \n" \
373
374 /* Accumulator high 32 bits. */
375 "MVTACHI R15, A1 \n" \
376 "POP R15 \n" \
377
378 /* Accumulator guard. */
379 "MVTACGU R15, A1 \n" \
380 "POP R15 \n" \
381 "MVTC R15, FPSW \n" \
382 "POPM R1-R15 \n" \
383 "RTE \n" \
384 "NOP \n" \
385 "NOP "
386 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
387 );
388 }
389 /*-----------------------------------------------------------*/
390
vTickISR(void)391 void vTickISR( void )
392 {
393 /* Re-enabled interrupts. */
394 __asm volatile( "SETPSW I" );
395
396 /* Increment the tick, and perform any processing the new tick value
397 necessitates. Ensure IPL is at the max syscall value first. */
398 portMASK_INTERRUPTS_FROM_KERNEL_ISR();
399 {
400 if( xTaskIncrementTick() != pdFALSE )
401 {
402 taskYIELD();
403 }
404 }
405 portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
406 }
407 /*-----------------------------------------------------------*/
408
ulPortGetIPL(void)409 uint32_t ulPortGetIPL( void )
410 {
411 __asm volatile
412 (
413 "MVFC PSW, R1 \n" \
414 "SHLR #24, R1 \n" \
415 "RTS "
416 );
417
418 /* This will never get executed, but keeps the compiler from complaining. */
419 return 0;
420 }
421 /*-----------------------------------------------------------*/
422
vPortSetIPL(uint32_t ulNewIPL)423 void vPortSetIPL( uint32_t ulNewIPL )
424 {
425 __asm volatile
426 (
427 "PUSH R5 \n" \
428 "MVFC PSW, R5 \n" \
429 "SHLL #24, R1 \n" \
430 "AND #-0F000001H, R5 \n" \
431 "OR R1, R5 \n" \
432 "MVTC R5, PSW \n" \
433 "POP R5 \n" \
434 "RTS "
435 );
436 }
437
