1/*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28    .extern pxCurrentTCB
29    .extern vTaskISRHandler
30    .extern vTaskSwitchContext
31    .extern uxCriticalNesting
32    .extern pulISRStack
33
34    .global __FreeRTOS_interrupt_handler
35    .global VPortYieldASM
36    .global vStartFirstTask
37
38
39.macro portSAVE_CONTEXT
40    /* Make room for the context on the stack. */
41    addik r1, r1, -132
42    /* Save r31 so it can then be used. */
43    swi r31, r1, 4
44    /* Copy the msr into r31 - this is stacked later. */
45    mfs r31, rmsr
46    /* Stack general registers. */
47    swi r30, r1, 12
48    swi r29, r1, 16
49    swi r28, r1, 20
50    swi r27, r1, 24
51    swi r26, r1, 28
52    swi r25, r1, 32
53    swi r24, r1, 36
54    swi r23, r1, 40
55    swi r22, r1, 44
56    swi r21, r1, 48
57    swi r20, r1, 52
58    swi r19, r1, 56
59    swi r18, r1, 60
60    swi r17, r1, 64
61    swi r16, r1, 68
62    swi r15, r1, 72
63    swi r13, r1, 80
64    swi r12, r1, 84
65    swi r11, r1, 88
66    swi r10, r1, 92
67    swi r9, r1, 96
68    swi r8, r1, 100
69    swi r7, r1, 104
70    swi r6, r1, 108
71    swi r5, r1, 112
72    swi r4, r1, 116
73    swi r3, r1, 120
74    swi r2, r1, 124
75    /* Stack the critical section nesting value. */
76    lwi r3, r0, uxCriticalNesting
77    swi r3, r1, 128
78    /* Save the top of stack value to the TCB. */
79    lwi r3, r0, pxCurrentTCB
80    sw  r1, r0, r3
81
82    .endm
83
84.macro portRESTORE_CONTEXT
85    /* Load the top of stack value from the TCB. */
86    lwi r3, r0, pxCurrentTCB
87    lw  r1, r0, r3
88    /* Restore the general registers. */
89    lwi r31, r1, 4
90    lwi r30, r1, 12
91    lwi r29, r1, 16
92    lwi r28, r1, 20
93    lwi r27, r1, 24
94    lwi r26, r1, 28
95    lwi r25, r1, 32
96    lwi r24, r1, 36
97    lwi r23, r1, 40
98    lwi r22, r1, 44
99    lwi r21, r1, 48
100    lwi r20, r1, 52
101    lwi r19, r1, 56
102    lwi r18, r1, 60
103    lwi r17, r1, 64
104    lwi r16, r1, 68
105    lwi r15, r1, 72
106    lwi r14, r1, 76
107    lwi r13, r1, 80
108    lwi r12, r1, 84
109    lwi r11, r1, 88
110    lwi r10, r1, 92
111    lwi r9, r1, 96
112    lwi r8, r1, 100
113    lwi r7, r1, 104
114    lwi r6, r1, 108
115    lwi r5, r1, 112
116    lwi r4, r1, 116
117    lwi r2, r1, 124
118
119    /* Load the critical nesting value. */
120    lwi r3, r1, 128
121    swi r3, r0, uxCriticalNesting
122
123    /* Obtain the MSR value from the stack. */
124    lwi r3, r1, 8
125
126    /* Are interrupts enabled in the MSR?  If so return using an return from
127    interrupt instruction to ensure interrupts are enabled only once the task
128    is running again. */
129    andi r3, r3, 2
130    beqid r3, 36
131    or r0, r0, r0
132
133    /* Reload the rmsr from the stack, clear the enable interrupt bit in the
134    value before saving back to rmsr register, then return enabling interrupts
135    as we return. */
136    lwi r3, r1, 8
137    andi r3, r3, ~2
138    mts rmsr, r3
139    lwi r3, r1, 120
140    addik r1, r1, 132
141    rtid r14, 0
142    or r0, r0, r0
143
144    /* Reload the rmsr from the stack, place it in the rmsr register, and
145    return without enabling interrupts. */
146    lwi r3, r1, 8
147    mts rmsr, r3
148    lwi r3, r1, 120
149    addik r1, r1, 132
150    rtsd r14, 0
151    or r0, r0, r0
152
153    .endm
154
155    .text
156    .align  2
157
158
159__FreeRTOS_interrupt_handler:
160    portSAVE_CONTEXT
161    /* Entered via an interrupt so interrupts must be enabled in msr. */
162    ori r31, r31, 2
163    /* Stack msr. */
164    swi r31, r1, 8
165    /* Stack the return address.  As we entered via an interrupt we do
166    not need to modify the return address prior to stacking. */
167    swi r14, r1, 76
168    /* Now switch to use the ISR stack. */
169    lwi r3, r0, pulISRStack
170    add r1, r3, r0
171    bralid r15, vTaskISRHandler
172    or r0, r0, r0
173    portRESTORE_CONTEXT
174
175
176VPortYieldASM:
177    portSAVE_CONTEXT
178    /* Stack msr. */
179    swi r31, r1, 8
180    /* Modify the return address so we return to the instruction after the
181    exception. */
182    addi r14, r14, 8
183    swi r14, r1, 76
184    /* Now switch to use the ISR stack. */
185    lwi r3, r0, pulISRStack
186    add r1, r3, r0
187    bralid r15, vTaskSwitchContext
188    or r0, r0, r0
189    portRESTORE_CONTEXT
190
191vStartFirstTask:
192    portRESTORE_CONTEXT
193
194
195