1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdlib.h>
31 #include <string.h>
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
38 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
39 #endif
40
41 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
42 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
43 #endif
44
45 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
46 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
47 #endif
48
49 #ifndef configSETUP_TICK_INTERRUPT
50 #error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
51 #endif /* configSETUP_TICK_INTERRUPT */
52
53 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
54 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
55 #endif
56
57 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
58 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
59 #endif
60
61 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
62 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
63 #endif
64
65 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
66 /* Check the configuration. */
67 #if ( configMAX_PRIORITIES > 32 )
68 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
69 #endif
70 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
71
72 /* In case security extensions are implemented. */
73 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
74 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
75 #endif
76
77 /*
78 * __ARM_FP is defined by the c preprocessor when FPU support is enabled,
79 * usually with the -mfpu= argument and -mfloat-abi=.
80 *
81 * Note: Some implementations of the c standard library may use FPU registers
82 * for generic memory operations (memcpy, etc).
83 * When setting configUSE_TASK_FPU_SUPPORT == 1, care must be taken to
84 * ensure that the FPU registers are not used without an FPU context.
85 */
86 #if ( configUSE_TASK_FPU_SUPPORT == 0 )
87 #ifdef __ARM_FP
88 #error __ARM_FP is defined, so configUSE_TASK_FPU_SUPPORT must be set to either to 1 or 2.
89 #endif /* __ARM_FP */
90 #elif ( configUSE_TASK_FPU_SUPPORT == 1 ) || ( configUSE_TASK_FPU_SUPPORT == 2 )
91 #ifndef __ARM_FP
92 #error __ARM_FP is not defined, so configUSE_TASK_FPU_SUPPORT must be set to 0.
93 #endif /* __ARM_FP */
94 #endif /* configUSE_TASK_FPU_SUPPORT */
95
96 /*
97 * Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
98 * portmacro.h.
99 */
100 #ifndef configCLEAR_TICK_INTERRUPT
101 #define configCLEAR_TICK_INTERRUPT()
102 #endif
103
104 /*
105 * A critical section is exited when the critical section nesting count reaches
106 * this value.
107 */
108 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
109
110 /*
111 * In all GICs 255 can be written to the priority mask register to unmask all
112 * (but the lowest) interrupt priority.
113 */
114 #define portUNMASK_VALUE ( 0xFFUL )
115
116 /*
117 * Tasks are not created with a floating point context, but can be given a
118 * floating point context after they have been created. A variable is stored as
119 * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
120 * does not have an FPU context, or any other value if the task does have an FPU
121 * context.
122 */
123 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
124
125 /* Constants required to setup the initial task context. */
126 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
127 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
128 #define portINTERRUPT_ENABLE_BIT ( 0x80UL )
129 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
130
131 /*
132 * Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
133 * point is zero.
134 */
135 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
136
137 /* Masks all bits in the APSR other than the mode bits. */
138 #define portAPSR_MODE_BITS_MASK ( 0x1F )
139
140 /* The value of the mode bits in the APSR when the CPU is executing in user
141 * mode. */
142 #define portAPSR_USER_MODE ( 0x10 )
143
144 /* The critical section macros only mask interrupts up to an application
145 * determined priority level. Sometimes it is necessary to turn interrupt off in
146 * the CPU itself before modifying certain hardware registers. */
147 #define portCPU_IRQ_DISABLE() \
148 __asm volatile ( "CPSID i" ::: "memory" ); \
149 __asm volatile ( "DSB" ); \
150 __asm volatile ( "ISB" );
151
152 #define portCPU_IRQ_ENABLE() \
153 __asm volatile ( "CPSIE i" ::: "memory" ); \
154 __asm volatile ( "DSB" ); \
155 __asm volatile ( "ISB" );
156
157
158 /* Macro to unmask all interrupt priorities. */
159 #define portCLEAR_INTERRUPT_MASK() \
160 { \
161 portCPU_IRQ_DISABLE(); \
162 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
163 __asm volatile ( "DSB \n" \
164 "ISB \n"); \
165 portCPU_IRQ_ENABLE(); \
166 }
167
168 #define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
169 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
170 #define portBIT_0_SET ( ( uint8_t ) 0x01 )
171
172 /*
173 * Let the user override the pre-loading of the initial LR with the address of
174 * prvTaskExitError() in case is messes up unwinding of the stack in the
175 * debugger.
176 */
177 #ifdef configTASK_RETURN_ADDRESS
178 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
179 #else
180 #define portTASK_RETURN_ADDRESS prvTaskExitError
181 #endif
182
183 #if ( configUSE_TASK_FPU_SUPPORT != 0 )
184
185 /*
186 * The space on the stack required to hold the FPU registers.
187 *
188 * The ARM Cortex R5 processor implements the VFPv3-D16 FPU
189 * architecture. This includes only 16 double-precision registers,
190 * instead of 32 as is in VFPv3. The register bank can be viewed
191 * either as sixteen 64-bit double-word registers (D0-D15) or
192 * thirty-two 32-bit single-word registers (S0-S31), in both cases
193 * the size of the bank remains the same. The FPU has also a 32-bit
194 * status register.
195 */
196 #define portFPU_REGISTER_WORDS ( ( 16 * 2 ) + 1 )
197 #endif /* configUSE_TASK_FPU_SUPPORT != 0 */
198
199 /*-----------------------------------------------------------*/
200
201 /*
202 * Starts the first task executing. This function is necessarily written in
203 * assembly code so is implemented in portASM.s.
204 */
205 extern void vPortRestoreTaskContext( void );
206
207 /*
208 * Used to catch tasks that attempt to return from their implementing function.
209 */
210 static void prvTaskExitError( void );
211
212 #if ( configUSE_TASK_FPU_SUPPORT != 0 )
213
214 /*
215 * If the application provides an implementation of vApplicationIRQHandler(),
216 * then it will get called directly without saving the FPU registers on
217 * interrupt entry, and this weak implementation of
218 * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
219 * it should never actually get called so its implementation contains a
220 * call to configASSERT() that will always fail.
221 *
222 * If the application provides its own implementation of
223 * vApplicationFPUSafeIRQHandler() then the implementation of
224 * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
225 * before calling it.
226 *
227 * Therefore, if the application writer wants FPU registers to be saved on
228 * interrupt entry their IRQ handler must be called
229 * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
230 * FPU registers to be saved on interrupt entry their IRQ handler must be
231 * called vApplicationIRQHandler().
232 */
233 void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak ) );
234 #endif /* configUSE_TASK_FPU_SUPPORT != 0 */
235
236 /*-----------------------------------------------------------*/
237
238 /*
239 * A variable is used to keep track of the critical section nesting. This
240 * variable has to be stored as part of the task context and must be initialised to
241 * a non zero value to ensure interrupts don't inadvertently become unmasked before
242 * the scheduler starts. As it is stored as part of the task context it will
243 * automatically be set to 0 when the first task is started.
244 */
245 volatile uint32_t ulCriticalNesting = 9999UL;
246
247 #if ( configUSE_TASK_FPU_SUPPORT != 0 )
248
249 /*
250 * Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
251 * a floating point context must be saved and restored for the task.
252 */
253 uint32_t ulPortTaskHasFPUContext = pdFALSE;
254 #endif /* configUSE_TASK_FPU_SUPPORT != 0 */
255
256 /* Set to 1 to pend a context switch from an ISR. */
257 uint32_t ulPortYieldRequired = pdFALSE;
258
259 /*
260 * Counts the interrupt nesting depth. A context switch is only performed if
261 * if the nesting depth is 0.
262 */
263 uint32_t ulPortInterruptNesting = 0UL;
264
265 /* Used in asm code. */
266 __attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
267 __attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
268 __attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
269 __attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
270
271 /*-----------------------------------------------------------*/
272
273 /*
274 * See header file for description.
275 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)276 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
277 TaskFunction_t pxCode,
278 void * pvParameters )
279 {
280 /*
281 * Setup the initial stack of the task. The stack is set exactly as
282 * expected by the portRESTORE_CONTEXT() macro.
283 *
284 * The fist real value on the stack is the status register, which is set for
285 * system mode, with interrupts enabled. A few NULLs are added first to ensure
286 * GDB does not try decoding a non-existent return address.
287 */
288 *pxTopOfStack = ( StackType_t ) NULL;
289 pxTopOfStack--;
290 *pxTopOfStack = ( StackType_t ) NULL;
291 pxTopOfStack--;
292 *pxTopOfStack = ( StackType_t ) NULL;
293 pxTopOfStack--;
294 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
295
296 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
297 {
298 /* The task will start in THUMB mode. */
299 *pxTopOfStack |= portTHUMB_MODE_BIT;
300 }
301
302 pxTopOfStack--;
303
304 /* Next the return address, which in this case is the start of the task. */
305 *pxTopOfStack = ( StackType_t ) pxCode;
306 pxTopOfStack--;
307
308 /* Next all the registers other than the stack pointer. */
309 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
310 pxTopOfStack--;
311 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
312 pxTopOfStack--;
313 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
314 pxTopOfStack--;
315 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
316 pxTopOfStack--;
317 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
318 pxTopOfStack--;
319 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
320 pxTopOfStack--;
321 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
322 pxTopOfStack--;
323 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
324 pxTopOfStack--;
325 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
326 pxTopOfStack--;
327 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
328 pxTopOfStack--;
329 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
330 pxTopOfStack--;
331 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
332 pxTopOfStack--;
333 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
334 pxTopOfStack--;
335 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
336
337 /*
338 * The task will start with a critical nesting count of 0 as interrupts are
339 * enabled.
340 */
341 pxTopOfStack--;
342 *pxTopOfStack = portNO_CRITICAL_NESTING;
343
344 #if ( configUSE_TASK_FPU_SUPPORT == 1 )
345 {
346 /*
347 * The task will start without a floating point context.
348 * A task that uses the floating point hardware must call
349 * vPortTaskUsesFPU() before executing any floating point
350 * instructions.
351 */
352 pxTopOfStack--;
353 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
354 }
355 #elif ( configUSE_TASK_FPU_SUPPORT == 2 )
356 {
357 /*
358 * The task will start with a floating point context. Leave enough
359 * space for the registers and ensure they are initialized to 0.
360 */
361 pxTopOfStack -= portFPU_REGISTER_WORDS;
362 memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
363
364 pxTopOfStack--;
365 *pxTopOfStack = pdTRUE;
366 ulPortTaskHasFPUContext = pdTRUE;
367 }
368 #elif ( configUSE_TASK_FPU_SUPPORT != 0 )
369 {
370 #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 0, 1, or 2.
371 }
372 #endif /* configUSE_TASK_FPU_SUPPORT */
373
374 return pxTopOfStack;
375 }
376 /*-----------------------------------------------------------*/
377
prvTaskExitError(void)378 static void prvTaskExitError( void )
379 {
380 /*
381 * A function that implements a task must not exit or attempt to return to
382 * its caller as there is nothing to return to. If a task wants to exit it
383 * should instead call vTaskDelete( NULL ).
384 *
385 * Artificially force an assert() to be triggered if configASSERT() is
386 * defined, then stop here so application writers can catch the error.
387 */
388 configASSERT( ulPortInterruptNesting == ~0UL );
389 portDISABLE_INTERRUPTS();
390
391 for( ; ; )
392 {
393 }
394 }
395 /*-----------------------------------------------------------*/
396
397 #if ( configUSE_TASK_FPU_SUPPORT != 0 )
398
vApplicationFPUSafeIRQHandler(uint32_t ulICCIAR)399 void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) /* __attribute__( ( weak ) ) */
400 {
401 ( void ) ulICCIAR;
402 configASSERT( ( volatile void * ) NULL );
403 }
404
405 #endif /* configUSE_TASK_FPU_SUPPORT != 0 */
406 /*-----------------------------------------------------------*/
407
xPortStartScheduler(void)408 BaseType_t xPortStartScheduler( void )
409 {
410 uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
411
412 #if ( configASSERT_DEFINED == 1 )
413 {
414 volatile uint8_t ucOriginalPriority;
415 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
416 volatile uint8_t ucMaxPriorityValue;
417
418 /*
419 * Determine how many priority bits are implemented in the GIC.
420 * Save the interrupt priority value that is about to be clobbered.
421 */
422 ucOriginalPriority = *pucFirstUserPriorityRegister;
423
424 /*
425 * Determine the number of priority bits available. First write to
426 * all possible bits.
427 */
428 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
429
430 /* Read the value back to see how many bits stuck. */
431 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
432
433 /* Shift to the least significant bits. */
434 while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
435 {
436 ucMaxPriorityValue >>= ( uint8_t ) 0x01;
437
438 /*
439 * If ulCycles reaches 0 then ucMaxPriorityValue must have been
440 * read as 0, indicating a misconfiguration.
441 */
442 ulCycles--;
443
444 if( ulCycles == 0 )
445 {
446 break;
447 }
448 }
449
450 /*
451 * Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
452 * value.
453 */
454 configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
455
456 /*
457 * Restore the clobbered interrupt priority register to its original
458 * value.
459 */
460 *pucFirstUserPriorityRegister = ucOriginalPriority;
461 }
462 #endif /* configASSERT_DEFINED */
463
464 /*
465 * Only continue if the CPU is not in User mode. The CPU must be in a
466 * Privileged mode for the scheduler to start.
467 */
468 __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
469 ulAPSR &= portAPSR_MODE_BITS_MASK;
470 configASSERT( ulAPSR != portAPSR_USER_MODE );
471
472 if( ulAPSR != portAPSR_USER_MODE )
473 {
474 /*
475 * Only continue if the binary point value is set to its lowest possible
476 * setting. See the comments in vPortValidateInterruptPriority() below for
477 * more information.
478 */
479 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
480
481 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
482 {
483 /*
484 * Interrupts are turned off in the CPU itself to ensure tick does
485 * not execute while the scheduler is being started. Interrupts are
486 * automatically turned back on in the CPU when the first task starts
487 * executing.
488 */
489 portCPU_IRQ_DISABLE();
490
491 /* Start the timer that generates the tick ISR. */
492 configSETUP_TICK_INTERRUPT();
493
494 /* Start the first task executing. */
495 vPortRestoreTaskContext();
496 }
497 }
498
499 /*
500 * Will only get here if vTaskStartScheduler() was called with the CPU in
501 * a non-privileged mode or the binary point register was not set to its lowest
502 * possible value. prvTaskExitError() is referenced to prevent a compiler
503 * warning about it being defined but not referenced in the case that the user
504 * defines their own exit address.
505 */
506 ( void ) prvTaskExitError;
507
508 return 0;
509 }
510 /*-----------------------------------------------------------*/
511
vPortEndScheduler(void)512 void vPortEndScheduler( void )
513 {
514 /*
515 * Not implemented in ports where there is nothing to return to.
516 * Artificially force an assert.
517 */
518 configASSERT( ulCriticalNesting == 1000UL );
519 }
520 /*-----------------------------------------------------------*/
521
vPortEnterCritical(void)522 void vPortEnterCritical( void )
523 {
524 /* Mask interrupts up to the max syscall interrupt priority. */
525 ulPortSetInterruptMask();
526
527 /*
528 * Now interrupts are disabled ulCriticalNesting can be accessed
529 * directly. Increment ulCriticalNesting to keep a count of how many times
530 * portENTER_CRITICAL() has been called.
531 */
532 ulCriticalNesting++;
533
534 /*
535 * This is not the interrupt safe version of the enter critical function so
536 * assert() if it is being called from an interrupt context. Only API
537 * functions that end in "FromISR" can be used in an interrupt. Only assert if
538 * the critical nesting count is 1 to protect against recursive calls if the
539 * assert function also uses a critical section.
540 */
541 if( ulCriticalNesting == 1 )
542 {
543 configASSERT( ulPortInterruptNesting == 0 );
544 }
545 }
546 /*-----------------------------------------------------------*/
547
vPortExitCritical(void)548 void vPortExitCritical( void )
549 {
550 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
551 {
552 /* Decrement the nesting count as the critical section is being exited. */
553 ulCriticalNesting--;
554
555 /*
556 * If the nesting level has reached zero then all interrupt
557 * priorities must be re-enabled.
558 */
559 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
560 {
561 /*
562 * Critical nesting has reached zero so all interrupt priorities
563 * should be unmasked.
564 */
565 portCLEAR_INTERRUPT_MASK();
566 }
567 }
568 }
569 /*-----------------------------------------------------------*/
570
FreeRTOS_Tick_Handler(void)571 void FreeRTOS_Tick_Handler( void )
572 {
573 /*
574 * Set interrupt mask before altering scheduler structures. The tick
575 * handler runs at the lowest priority, so interrupts cannot already be masked,
576 * so there is no need to save and restore the current mask value. It is
577 * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
578 * updated.
579 */
580 portCPU_IRQ_DISABLE();
581 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
582 __asm volatile ( "dsb \n"
583 "isb \n"::: "memory" );
584 portCPU_IRQ_ENABLE();
585
586 /* Increment the RTOS tick. */
587 if( xTaskIncrementTick() != pdFALSE )
588 {
589 ulPortYieldRequired = pdTRUE;
590 }
591
592 /* Ensure all interrupt priorities are active again. */
593 portCLEAR_INTERRUPT_MASK();
594 configCLEAR_TICK_INTERRUPT();
595 }
596 /*-----------------------------------------------------------*/
597
598 #if ( configUSE_TASK_FPU_SUPPORT == 1 )
599
vPortTaskUsesFPU(void)600 void vPortTaskUsesFPU( void )
601 {
602 uint32_t ulInitialFPSCR = 0;
603
604 /*
605 * A task is registering the fact that it needs an FPU context. Set the
606 * FPU flag (which is saved as part of the task context).
607 */
608 ulPortTaskHasFPUContext = pdTRUE;
609
610 /* Initialise the floating point status register. */
611 __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
612 }
613
614 #endif /* configUSE_TASK_FPU_SUPPORT == 1 */
615 /*-----------------------------------------------------------*/
616
vPortClearInterruptMask(uint32_t ulNewMaskValue)617 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
618 {
619 if( ulNewMaskValue == pdFALSE )
620 {
621 portCLEAR_INTERRUPT_MASK();
622 }
623 }
624 /*-----------------------------------------------------------*/
625
ulPortSetInterruptMask(void)626 uint32_t ulPortSetInterruptMask( void )
627 {
628 uint32_t ulReturn;
629
630 /* Interrupts must be masked while ICCPMR is updated. */
631 portCPU_IRQ_DISABLE();
632
633 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
634 {
635 /* Interrupts were already masked. */
636 ulReturn = pdTRUE;
637 }
638 else
639 {
640 ulReturn = pdFALSE;
641 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
642 __asm volatile ( "dsb \n"
643 "isb \n"::: "memory" );
644 }
645
646 portCPU_IRQ_ENABLE();
647
648 return ulReturn;
649 }
650 /*-----------------------------------------------------------*/
651
652 #if ( configASSERT_DEFINED == 1 )
653
vPortValidateInterruptPriority(void)654 void vPortValidateInterruptPriority( void )
655 {
656 /*
657 * The following assertion will fail if a service routine (ISR) for
658 * an interrupt that has been assigned a priority above
659 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
660 * function. ISR safe FreeRTOS API functions must *only* be called
661 * from interrupts that have been assigned a priority at or below
662 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
663 *
664 * Numerically low interrupt priority numbers represent logically high
665 * interrupt priorities, therefore the priority of the interrupt must
666 * be set to a value equal to or numerically *higher* than
667 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
668 *
669 * FreeRTOS maintains separate thread and ISR API functions to ensure
670 * interrupt entry is as fast and simple as possible.
671 */
672
673 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
674
675 /*
676 * Priority grouping: The interrupt controller (GIC) allows the bits
677 * that define each interrupt's priority to be split between bits that
678 * define the interrupt's pre-emption priority bits and bits that define
679 * the interrupt's sub-priority. For simplicity all bits must be defined
680 * to be pre-emption priority bits. The following assertion will fail if
681 * this is not the case (if some bits represent a sub-priority).
682 *
683 * The priority grouping is configured by the GIC's binary point register
684 * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
685 * possible value (which may be above 0).
686 */
687 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
688 }
689
690 #endif /* configASSERT_DEFINED */
691 /*-----------------------------------------------------------*/
692
