1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM7 port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 #ifndef __VFP_FP__
38 #error This port can only be used when the project options are configured to enable hardware floating point support.
39 #endif
40
41 /* Prototype of all Interrupt Service Routines (ISRs). */
42 typedef void ( * portISR_t )( void );
43
44 /* Constants required to manipulate the core. Registers first... */
45 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
46 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
47 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
48 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
49 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
50 /* ...then bits in the registers. */
51 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
52 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
53 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
54 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
55 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
56 #define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
57 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
58
59 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
60 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
61 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
62
63 /* Constants used to check the installation of the FreeRTOS interrupt handlers. */
64 #define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
65 #define portVECTOR_INDEX_SVC ( 11 )
66 #define portVECTOR_INDEX_PENDSV ( 14 )
67
68 /* Constants required to check the validity of an interrupt priority. */
69 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
70 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
71 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
72 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
73 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
74 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
75 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
76 #define portPRIGROUP_SHIFT ( 8UL )
77
78 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
79 #define portVECTACTIVE_MASK ( 0xFFUL )
80
81 /* Constants required to manipulate the VFP. */
82 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
83 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
84
85 /* Constants required to set up the initial stack. */
86 #define portINITIAL_XPSR ( 0x01000000 )
87 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
88
89 /* The systick is a 24-bit counter. */
90 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
91
92 /* For strict compliance with the Cortex-M spec the task start address should
93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
94 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
95
96 /* A fiddle factor to estimate the number of SysTick counts that would have
97 * occurred while the SysTick counter is stopped during tickless idle
98 * calculations. */
99 #define portMISSED_COUNTS_FACTOR ( 94UL )
100
101 /* Let the user override the default SysTick clock rate. If defined by the
102 * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
103 * configuration register. */
104 #ifndef configSYSTICK_CLOCK_HZ
105 #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
106 /* Ensure the SysTick is clocked at the same frequency as the core. */
107 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
108 #else
109 /* Select the option to clock SysTick not at the same frequency as the core. */
110 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
111 #endif
112
113 /* Let the user override the pre-loading of the initial LR with the address of
114 * prvTaskExitError() in case it messes up unwinding of the stack in the
115 * debugger. */
116 #ifdef configTASK_RETURN_ADDRESS
117 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
118 #else
119 #define portTASK_RETURN_ADDRESS prvTaskExitError
120 #endif
121
122 /*
123 * Setup the timer to generate the tick interrupts. The implementation in this
124 * file is weak to allow application writers to change the timer used to
125 * generate the tick interrupt.
126 */
127 void vPortSetupTimerInterrupt( void );
128
129 /*
130 * Exception handlers.
131 */
132 void xPortPendSVHandler( void ) __attribute__( ( naked ) );
133 void xPortSysTickHandler( void );
134 void vPortSVCHandler( void ) __attribute__( ( naked ) );
135
136 /*
137 * Start first task is a separate function so it can be tested in isolation.
138 */
139 static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
140
141 /*
142 * Function to enable the VFP.
143 */
144 static void vPortEnableVFP( void ) __attribute__( ( naked ) );
145
146 /*
147 * Used to catch tasks that attempt to return from their implementing function.
148 */
149 static void prvTaskExitError( void );
150
151 /*-----------------------------------------------------------*/
152
153 /* Each task maintains its own interrupt status in the critical nesting
154 * variable. */
155 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
156
157 /*
158 * The number of SysTick increments that make up one tick period.
159 */
160 #if ( configUSE_TICKLESS_IDLE == 1 )
161 static uint32_t ulTimerCountsForOneTick = 0;
162 #endif /* configUSE_TICKLESS_IDLE */
163
164 /*
165 * The maximum number of tick periods that can be suppressed is limited by the
166 * 24 bit resolution of the SysTick timer.
167 */
168 #if ( configUSE_TICKLESS_IDLE == 1 )
169 static uint32_t xMaximumPossibleSuppressedTicks = 0;
170 #endif /* configUSE_TICKLESS_IDLE */
171
172 /*
173 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
174 * power functionality only.
175 */
176 #if ( configUSE_TICKLESS_IDLE == 1 )
177 static uint32_t ulStoppedTimerCompensation = 0;
178 #endif /* configUSE_TICKLESS_IDLE */
179
180 /*
181 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
182 * FreeRTOS API functions are not called from interrupts that have been assigned
183 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
184 */
185 #if ( configASSERT_DEFINED == 1 )
186 static uint8_t ucMaxSysCallPriority = 0;
187 static uint32_t ulMaxPRIGROUPValue = 0;
188 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
189 #endif /* configASSERT_DEFINED */
190
191 /*-----------------------------------------------------------*/
192
193 /*
194 * See header file for description.
195 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)196 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
197 TaskFunction_t pxCode,
198 void * pvParameters )
199 {
200 /* Simulate the stack frame as it would be created by a context switch
201 * interrupt. */
202
203 /* Offset added to account for the way the MCU uses the stack on entry/exit
204 * of interrupts, and to ensure alignment. */
205 pxTopOfStack--;
206
207 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
208 pxTopOfStack--;
209 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
210 pxTopOfStack--;
211 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
212
213 /* Save code space by skipping register initialisation. */
214 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
215 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
216
217 /* A save method is being used that requires each task to maintain its
218 * own exec return value. */
219 pxTopOfStack--;
220 *pxTopOfStack = portINITIAL_EXC_RETURN;
221
222 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
223
224 return pxTopOfStack;
225 }
226 /*-----------------------------------------------------------*/
227
prvTaskExitError(void)228 static void prvTaskExitError( void )
229 {
230 volatile uint32_t ulDummy = 0;
231
232 /* A function that implements a task must not exit or attempt to return to
233 * its caller as there is nothing to return to. If a task wants to exit it
234 * should instead call vTaskDelete( NULL ).
235 *
236 * Artificially force an assert() to be triggered if configASSERT() is
237 * defined, then stop here so application writers can catch the error. */
238 configASSERT( uxCriticalNesting == ~0UL );
239 portDISABLE_INTERRUPTS();
240
241 while( ulDummy == 0 )
242 {
243 /* This file calls prvTaskExitError() after the scheduler has been
244 * started to remove a compiler warning about the function being defined
245 * but never called. ulDummy is used purely to quieten other warnings
246 * about code appearing after this function is called - making ulDummy
247 * volatile makes the compiler think the function could return and
248 * therefore not output an 'unreachable code' warning for code that appears
249 * after it. */
250 }
251 }
252 /*-----------------------------------------------------------*/
253
vPortSVCHandler(void)254 void vPortSVCHandler( void )
255 {
256 __asm volatile (
257 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
258 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
259 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
260 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
261 " msr psp, r0 \n" /* Restore the task stack pointer. */
262 " isb \n"
263 " mov r0, #0 \n"
264 " msr basepri, r0 \n"
265 " bx r14 \n"
266 " \n"
267 " .align 4 \n"
268 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
269 );
270 }
271 /*-----------------------------------------------------------*/
272
prvPortStartFirstTask(void)273 static void prvPortStartFirstTask( void )
274 {
275 /* Start the first task. This also clears the bit that indicates the FPU is
276 * in use in case the FPU was used before the scheduler was started - which
277 * would otherwise result in the unnecessary leaving of space in the SVC stack
278 * for lazy saving of FPU registers. */
279 __asm volatile (
280 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
281 " ldr r0, [r0] \n"
282 " ldr r0, [r0] \n"
283 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
284 " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
285 " msr control, r0 \n"
286 " cpsie i \n" /* Globally enable interrupts. */
287 " cpsie f \n"
288 " dsb \n"
289 " isb \n"
290 " svc 0 \n" /* System call to start first task. */
291 " nop \n"
292 " .ltorg \n"
293 );
294 }
295 /*-----------------------------------------------------------*/
296
297 /*
298 * See header file for description.
299 */
xPortStartScheduler(void)300 BaseType_t xPortStartScheduler( void )
301 {
302 /* An application can install FreeRTOS interrupt handlers in one of the
303 * following ways:
304 * 1. Direct Routing - Install the functions vPortSVCHandler and
305 * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
306 * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
307 * interrupts and route program control from those handlers to
308 * vPortSVCHandler and xPortPendSVHandler functions.
309 *
310 * Applications that use Indirect Routing must set
311 * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
312 * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
313 * is 1, should be preferred when possible. */
314 #if ( configCHECK_HANDLER_INSTALLATION == 1 )
315 {
316 const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
317
318 /* Validate that the application has correctly installed the FreeRTOS
319 * handlers for SVCall and PendSV interrupts. We do not check the
320 * installation of the SysTick handler because the application may
321 * choose to drive the RTOS tick using a timer other than the SysTick
322 * timer by overriding the weak function vPortSetupTimerInterrupt().
323 *
324 * Assertion failures here indicate incorrect installation of the
325 * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
326 * https://www.FreeRTOS.org/FAQHelp.html.
327 *
328 * Systems with a configurable address for the interrupt vector table
329 * can also encounter assertion failures or even system faults here if
330 * VTOR is not set correctly to point to the application's vector table. */
331 configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
332 configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
333 }
334 #endif /* configCHECK_HANDLER_INSTALLATION */
335
336 #if ( configASSERT_DEFINED == 1 )
337 {
338 volatile uint8_t ucOriginalPriority;
339 volatile uint32_t ulImplementedPrioBits = 0;
340 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
341 volatile uint8_t ucMaxPriorityValue;
342
343 /* Determine the maximum priority from which ISR safe FreeRTOS API
344 * functions can be called. ISR safe functions are those that end in
345 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
346 * ensure interrupt entry is as fast and simple as possible.
347 *
348 * Save the interrupt priority value that is about to be clobbered. */
349 ucOriginalPriority = *pucFirstUserPriorityRegister;
350
351 /* Determine the number of priority bits available. First write to all
352 * possible bits. */
353 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
354
355 /* Read the value back to see how many bits stuck. */
356 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
357
358 /* Use the same mask on the maximum system call priority. */
359 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
360
361 /* Check that the maximum system call priority is nonzero after
362 * accounting for the number of priority bits supported by the
363 * hardware. A priority of 0 is invalid because setting the BASEPRI
364 * register to 0 unmasks all interrupts, and interrupts with priority 0
365 * cannot be masked using BASEPRI.
366 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
367 configASSERT( ucMaxSysCallPriority );
368
369 /* Check that the bits not implemented in hardware are zero in
370 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
371 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
372
373 /* Calculate the maximum acceptable priority group value for the number
374 * of bits read back. */
375
376 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
377 {
378 ulImplementedPrioBits++;
379 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
380 }
381
382 if( ulImplementedPrioBits == 8 )
383 {
384 /* When the hardware implements 8 priority bits, there is no way for
385 * the software to configure PRIGROUP to not have sub-priorities. As
386 * a result, the least significant bit is always used for sub-priority
387 * and there are 128 preemption priorities and 2 sub-priorities.
388 *
389 * This may cause some confusion in some cases - for example, if
390 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
391 * priority interrupts will be masked in Critical Sections as those
392 * are at the same preemption priority. This may appear confusing as
393 * 4 is higher (numerically lower) priority than
394 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
395 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
396 * to 4, this confusion does not happen and the behaviour remains the same.
397 *
398 * The following assert ensures that the sub-priority bit in the
399 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
400 * confusion. */
401 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
402 ulMaxPRIGROUPValue = 0;
403 }
404 else
405 {
406 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
407 }
408
409 /* Shift the priority group value back to its position within the AIRCR
410 * register. */
411 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
412 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
413
414 /* Restore the clobbered interrupt priority register to its original
415 * value. */
416 *pucFirstUserPriorityRegister = ucOriginalPriority;
417 }
418 #endif /* configASSERT_DEFINED */
419
420 /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
421 * the highest priority. */
422 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
423 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
424 portNVIC_SHPR2_REG = 0;
425
426 /* Start the timer that generates the tick ISR. Interrupts are disabled
427 * here already. */
428 vPortSetupTimerInterrupt();
429
430 /* Initialise the critical nesting count ready for the first task. */
431 uxCriticalNesting = 0;
432
433 /* Ensure the VFP is enabled - it should be anyway. */
434 vPortEnableVFP();
435
436 /* Lazy save always. */
437 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
438
439 /* Start the first task. */
440 prvPortStartFirstTask();
441
442 /* Should never get here as the tasks will now be executing! Call the task
443 * exit error function to prevent compiler warnings about a static function
444 * not being called in the case that the application writer overrides this
445 * functionality by defining configTASK_RETURN_ADDRESS. Call
446 * vTaskSwitchContext() so link time optimisation does not remove the
447 * symbol. */
448 vTaskSwitchContext();
449 prvTaskExitError();
450
451 /* Should not get here! */
452 return 0;
453 }
454 /*-----------------------------------------------------------*/
455
vPortEndScheduler(void)456 void vPortEndScheduler( void )
457 {
458 /* Not implemented in ports where there is nothing to return to.
459 * Artificially force an assert. */
460 configASSERT( uxCriticalNesting == 1000UL );
461 }
462 /*-----------------------------------------------------------*/
463
vPortEnterCritical(void)464 void vPortEnterCritical( void )
465 {
466 portDISABLE_INTERRUPTS();
467 uxCriticalNesting++;
468
469 /* This is not the interrupt safe version of the enter critical function so
470 * assert() if it is being called from an interrupt context. Only API
471 * functions that end in "FromISR" can be used in an interrupt. Only assert if
472 * the critical nesting count is 1 to protect against recursive calls if the
473 * assert function also uses a critical section. */
474 if( uxCriticalNesting == 1 )
475 {
476 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
477 }
478 }
479 /*-----------------------------------------------------------*/
480
vPortExitCritical(void)481 void vPortExitCritical( void )
482 {
483 configASSERT( uxCriticalNesting );
484 uxCriticalNesting--;
485
486 if( uxCriticalNesting == 0 )
487 {
488 portENABLE_INTERRUPTS();
489 }
490 }
491 /*-----------------------------------------------------------*/
492
xPortPendSVHandler(void)493 void xPortPendSVHandler( void )
494 {
495 /* This is a naked function. */
496
497 __asm volatile
498 (
499 " mrs r0, psp \n"
500 " isb \n"
501 " \n"
502 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
503 " ldr r2, [r3] \n"
504 " \n"
505 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
506 " it eq \n"
507 " vstmdbeq r0!, {s16-s31} \n"
508 " \n"
509 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
510 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
511 " \n"
512 " stmdb sp!, {r0, r3} \n"
513 " mov r0, %0 \n"
514 " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
515 " msr basepri, r0 \n"
516 " dsb \n"
517 " isb \n"
518 " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
519 " bl vTaskSwitchContext \n"
520 " mov r0, #0 \n"
521 " msr basepri, r0 \n"
522 " ldmia sp!, {r0, r3} \n"
523 " \n"
524 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
525 " ldr r0, [r1] \n"
526 " \n"
527 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
528 " \n"
529 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
530 " it eq \n"
531 " vldmiaeq r0!, {s16-s31} \n"
532 " \n"
533 " msr psp, r0 \n"
534 " isb \n"
535 " \n"
536 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
537 #if WORKAROUND_PMU_CM001 == 1
538 " push { r14 } \n"
539 " pop { pc } \n"
540 #endif
541 #endif
542 " \n"
543 " bx r14 \n"
544 " \n"
545 " .align 4 \n"
546 "pxCurrentTCBConst: .word pxCurrentTCB \n"
547 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
548 );
549 }
550 /*-----------------------------------------------------------*/
551
xPortSysTickHandler(void)552 void xPortSysTickHandler( void )
553 {
554 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
555 * executes all interrupts must be unmasked. There is therefore no need to
556 * save and then restore the interrupt mask value as its value is already
557 * known. */
558 portDISABLE_INTERRUPTS();
559 traceISR_ENTER();
560 {
561 /* Increment the RTOS tick. */
562 if( xTaskIncrementTick() != pdFALSE )
563 {
564 traceISR_EXIT_TO_SCHEDULER();
565
566 /* A context switch is required. Context switching is performed in
567 * the PendSV interrupt. Pend the PendSV interrupt. */
568 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
569 }
570 else
571 {
572 traceISR_EXIT();
573 }
574 }
575 portENABLE_INTERRUPTS();
576 }
577 /*-----------------------------------------------------------*/
578
579 #if ( configUSE_TICKLESS_IDLE == 1 )
580
vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)581 __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
582 {
583 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
584 TickType_t xModifiableIdleTime;
585
586 /* Make sure the SysTick reload value does not overflow the counter. */
587 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
588 {
589 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
590 }
591
592 /* Enter a critical section but don't use the taskENTER_CRITICAL()
593 * method as that will mask interrupts that should exit sleep mode. */
594 __asm volatile ( "cpsid i" ::: "memory" );
595 __asm volatile ( "dsb" );
596 __asm volatile ( "isb" );
597
598 /* If a context switch is pending or a task is waiting for the scheduler
599 * to be unsuspended then abandon the low power entry. */
600 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
601 {
602 /* Re-enable interrupts - see comments above the cpsid instruction
603 * above. */
604 __asm volatile ( "cpsie i" ::: "memory" );
605 }
606 else
607 {
608 /* Stop the SysTick momentarily. The time the SysTick is stopped for
609 * is accounted for as best it can be, but using the tickless mode will
610 * inevitably result in some tiny drift of the time maintained by the
611 * kernel with respect to calendar time. */
612 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
613
614 /* Use the SysTick current-value register to determine the number of
615 * SysTick decrements remaining until the next tick interrupt. If the
616 * current-value register is zero, then there are actually
617 * ulTimerCountsForOneTick decrements remaining, not zero, because the
618 * SysTick requests the interrupt when decrementing from 1 to 0. */
619 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
620
621 if( ulSysTickDecrementsLeft == 0 )
622 {
623 ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
624 }
625
626 /* Calculate the reload value required to wait xExpectedIdleTime
627 * tick periods. -1 is used because this code normally executes part
628 * way through the first tick period. But if the SysTick IRQ is now
629 * pending, then clear the IRQ, suppressing the first tick, and correct
630 * the reload value to reflect that the second tick period is already
631 * underway. The expected idle time is always at least two ticks. */
632 ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
633
634 if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
635 {
636 portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
637 ulReloadValue -= ulTimerCountsForOneTick;
638 }
639
640 if( ulReloadValue > ulStoppedTimerCompensation )
641 {
642 ulReloadValue -= ulStoppedTimerCompensation;
643 }
644
645 /* Set the new reload value. */
646 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
647
648 /* Clear the SysTick count flag and set the count value back to
649 * zero. */
650 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
651
652 /* Restart SysTick. */
653 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
654
655 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
656 * set its parameter to 0 to indicate that its implementation contains
657 * its own wait for interrupt or wait for event instruction, and so wfi
658 * should not be executed again. However, the original expected idle
659 * time variable must remain unmodified, so a copy is taken. */
660 xModifiableIdleTime = xExpectedIdleTime;
661 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
662
663 if( xModifiableIdleTime > 0 )
664 {
665 __asm volatile ( "dsb" ::: "memory" );
666 __asm volatile ( "wfi" );
667 __asm volatile ( "isb" );
668 }
669
670 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
671
672 /* Re-enable interrupts to allow the interrupt that brought the MCU
673 * out of sleep mode to execute immediately. See comments above
674 * the cpsid instruction above. */
675 __asm volatile ( "cpsie i" ::: "memory" );
676 __asm volatile ( "dsb" );
677 __asm volatile ( "isb" );
678
679 /* Disable interrupts again because the clock is about to be stopped
680 * and interrupts that execute while the clock is stopped will increase
681 * any slippage between the time maintained by the RTOS and calendar
682 * time. */
683 __asm volatile ( "cpsid i" ::: "memory" );
684 __asm volatile ( "dsb" );
685 __asm volatile ( "isb" );
686
687 /* Disable the SysTick clock without reading the
688 * portNVIC_SYSTICK_CTRL_REG register to ensure the
689 * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
690 * the time the SysTick is stopped for is accounted for as best it can
691 * be, but using the tickless mode will inevitably result in some tiny
692 * drift of the time maintained by the kernel with respect to calendar
693 * time*/
694 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
695
696 /* Determine whether the SysTick has already counted to zero. */
697 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
698 {
699 uint32_t ulCalculatedLoadValue;
700
701 /* The tick interrupt ended the sleep (or is now pending), and
702 * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
703 * with whatever remains of the new tick period. */
704 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
705
706 /* Don't allow a tiny value, or values that have somehow
707 * underflowed because the post sleep hook did something
708 * that took too long or because the SysTick current-value register
709 * is zero. */
710 if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
711 {
712 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
713 }
714
715 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
716
717 /* As the pending tick will be processed as soon as this
718 * function exits, the tick value maintained by the tick is stepped
719 * forward by one less than the time spent waiting. */
720 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
721 }
722 else
723 {
724 /* Something other than the tick interrupt ended the sleep. */
725
726 /* Use the SysTick current-value register to determine the
727 * number of SysTick decrements remaining until the expected idle
728 * time would have ended. */
729 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
730 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
731 {
732 /* If the SysTick is not using the core clock, the current-
733 * value register might still be zero here. In that case, the
734 * SysTick didn't load from the reload register, and there are
735 * ulReloadValue decrements remaining in the expected idle
736 * time, not zero. */
737 if( ulSysTickDecrementsLeft == 0 )
738 {
739 ulSysTickDecrementsLeft = ulReloadValue;
740 }
741 }
742 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
743
744 /* Work out how long the sleep lasted rounded to complete tick
745 * periods (not the ulReload value which accounted for part
746 * ticks). */
747 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
748
749 /* How many complete tick periods passed while the processor
750 * was waiting? */
751 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
752
753 /* The reload value is set to whatever fraction of a single tick
754 * period remains. */
755 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
756 }
757
758 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
759 * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
760 * the SysTick is not using the core clock, temporarily configure it to
761 * use the core clock. This configuration forces the SysTick to load
762 * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
763 * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
764 * to receive the standard value immediately. */
765 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
766 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
767 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
768 {
769 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
770 }
771 #else
772 {
773 /* The temporary usage of the core clock has served its purpose,
774 * as described above. Resume usage of the other clock. */
775 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
776
777 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
778 {
779 /* The partial tick period already ended. Be sure the SysTick
780 * counts it only once. */
781 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
782 }
783
784 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
785 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
786 }
787 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
788
789 /* Step the tick to account for any tick periods that elapsed. */
790 vTaskStepTick( ulCompleteTickPeriods );
791
792 /* Exit with interrupts enabled. */
793 __asm volatile ( "cpsie i" ::: "memory" );
794 }
795 }
796
797 #endif /* #if configUSE_TICKLESS_IDLE */
798 /*-----------------------------------------------------------*/
799
800 /*
801 * Setup the systick timer to generate the tick interrupts at the required
802 * frequency.
803 */
vPortSetupTimerInterrupt(void)804 __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
805 {
806 /* Calculate the constants required to configure the tick interrupt. */
807 #if ( configUSE_TICKLESS_IDLE == 1 )
808 {
809 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
810 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
811 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
812 }
813 #endif /* configUSE_TICKLESS_IDLE */
814
815 /* Stop and clear the SysTick. */
816 portNVIC_SYSTICK_CTRL_REG = 0UL;
817 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
818
819 /* Configure SysTick to interrupt at the requested rate. */
820 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
821 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
822 }
823 /*-----------------------------------------------------------*/
824
825 /* This is a naked function. */
vPortEnableVFP(void)826 static void vPortEnableVFP( void )
827 {
828 __asm volatile
829 (
830 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
831 " ldr r1, [r0] \n"
832 " \n"
833 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
834 " str r1, [r0] \n"
835 " bx r14 \n"
836 " .ltorg \n"
837 );
838 }
839 /*-----------------------------------------------------------*/
840
841 #if ( configASSERT_DEFINED == 1 )
842
vPortValidateInterruptPriority(void)843 void vPortValidateInterruptPriority( void )
844 {
845 uint32_t ulCurrentInterrupt;
846 uint8_t ucCurrentPriority;
847
848 /* Obtain the number of the currently executing interrupt. */
849 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
850
851 /* Is the interrupt number a user defined interrupt? */
852 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
853 {
854 /* Look up the interrupt's priority. */
855 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
856
857 /* The following assertion will fail if a service routine (ISR) for
858 * an interrupt that has been assigned a priority above
859 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
860 * function. ISR safe FreeRTOS API functions must *only* be called
861 * from interrupts that have been assigned a priority at or below
862 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
863 *
864 * Numerically low interrupt priority numbers represent logically high
865 * interrupt priorities, therefore the priority of the interrupt must
866 * be set to a value equal to or numerically *higher* than
867 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
868 *
869 * Interrupts that use the FreeRTOS API must not be left at their
870 * default priority of zero as that is the highest possible priority,
871 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
872 * and therefore also guaranteed to be invalid.
873 *
874 * FreeRTOS maintains separate thread and ISR API functions to ensure
875 * interrupt entry is as fast and simple as possible.
876 *
877 * The following links provide detailed information:
878 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
879 * https://www.FreeRTOS.org/FAQHelp.html */
880 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
881 }
882
883 /* Priority grouping: The interrupt controller (NVIC) allows the bits
884 * that define each interrupt's priority to be split between bits that
885 * define the interrupt's pre-emption priority bits and bits that define
886 * the interrupt's sub-priority. For simplicity all bits must be defined
887 * to be pre-emption priority bits. The following assertion will fail if
888 * this is not the case (if some bits represent a sub-priority).
889 *
890 * If the application only uses CMSIS libraries for interrupt
891 * configuration then the correct setting can be achieved on all Cortex-M
892 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
893 * scheduler. Note however that some vendor specific peripheral libraries
894 * assume a non-zero priority group setting, in which cases using a value
895 * of zero will result in unpredictable behaviour. */
896 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
897 }
898
899 #endif /* configASSERT_DEFINED */
900
