1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM4 MPU port.
31 *----------------------------------------------------------*/
32
33 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
34 * all the API functions to use the MPU wrappers. That should only be done when
35 * task.h is included from an application file. */
36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
37
38 /* Scheduler includes. */
39 #include "FreeRTOS.h"
40 #include "task.h"
41 #include "mpu_syscall_numbers.h"
42
43 #ifndef __VFP_FP__
44 #error This port can only be used when the project options are configured to enable hardware floating point support.
45 #endif
46
47 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
48
49 #ifndef configSYSTICK_CLOCK_HZ
50 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
51 /* Ensure the SysTick is clocked at the same frequency as the core. */
52 #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
53 #else
54
55 /* The way the SysTick is clocked is not modified in case it is not the same
56 * as the core. */
57 #define portNVIC_SYSTICK_CLK ( 0 )
58 #endif
59
60 #ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
61 #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
62 #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
63 #endif
64
65 /* Prototype of all Interrupt Service Routines (ISRs). */
66 typedef void ( * portISR_t )( void );
67
68 /* Constants required to access and manipulate the NVIC. */
69 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
70 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
71 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
72 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
73 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
74 #define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
75 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
76
77 /* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
78 * that a work around is active for errata 837070. */
79 #define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
80 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
81 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
82
83 /* Constants required to access and manipulate the MPU. */
84 #define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
85 #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
86 #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
87 #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
88 #define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
89 #define portMPU_ENABLE ( 0x01UL )
90 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
91 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
92 #define portMPU_REGION_VALID ( 0x10UL )
93 #define portMPU_REGION_ENABLE ( 0x01UL )
94 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
95 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
96
97 /* Constants required to access and manipulate the SysTick. */
98 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
99 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
100 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
101 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
102 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
103
104 /* Constants required to manipulate the VFP. */
105 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
106 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
107
108 /* Constants required to set up the initial stack. */
109 #define portINITIAL_XPSR ( 0x01000000UL )
110 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
111 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
112 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
113
114 /* Constants used to check the installation of the FreeRTOS interrupt handlers. */
115 #define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
116 #define portVECTOR_INDEX_SVC ( 11 )
117 #define portVECTOR_INDEX_PENDSV ( 14 )
118
119 /* Constants required to check the validity of an interrupt priority. */
120 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
121 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
122 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
123 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
124 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
125 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
126 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
127 #define portPRIGROUP_SHIFT ( 8UL )
128
129 /* Constants used during system call enter and exit. */
130 #define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
131 #define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
132
133 /* Offsets in the stack to the parameters when inside the SVC handler. */
134 #define portOFFSET_TO_LR ( 5 )
135 #define portOFFSET_TO_PC ( 6 )
136 #define portOFFSET_TO_PSR ( 7 )
137
138
139 /* For strict compliance with the Cortex-M spec the task start address should
140 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
141 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
142
143 /* Does addr lie within [start, end] address range? */
144 #define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
145 ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
146
147 /* Is the access request satisfied by the available permissions? */
148 #define portIS_AUTHORIZED( accessRequest, permissions ) \
149 ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
150
151 /* Max value that fits in a uint32_t type. */
152 #define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
153
154 /* Check if adding a and b will result in overflow. */
155 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
156 /*-----------------------------------------------------------*/
157
158 /*
159 * Configure a number of standard MPU regions that are used by all tasks.
160 */
161 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
162
163 /*
164 * Return the smallest MPU region size that a given number of bytes will fit
165 * into. The region size is returned as the value that should be programmed
166 * into the region attribute register for that region.
167 */
168 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
169
170 /*
171 * Setup the timer to generate the tick interrupts. The implementation in this
172 * file is weak to allow application writers to change the timer used to
173 * generate the tick interrupt.
174 */
175 void vPortSetupTimerInterrupt( void );
176
177 /*
178 * Standard FreeRTOS exception handlers.
179 */
180 void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
181 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
182 void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
183
184 /*
185 * Starts the scheduler by restoring the context of the first task to run.
186 */
187 static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
188
189 /*
190 * C portion of the SVC handler. The SVC handler is split between an asm entry
191 * and a C wrapper for simplicity of coding and maintenance.
192 */
193 void vSVCHandler_C( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
194
195 /*
196 * Function to enable the VFP.
197 */
198 static void vPortEnableVFP( void ) __attribute__( ( naked ) );
199
200 /**
201 * @brief Checks whether or not the processor is privileged.
202 *
203 * @return 1 if the processor is already privileged, 0 otherwise.
204 */
205 BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
206
207 /**
208 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
209 * register.
210 *
211 * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
212 * Bit[0] = 0 --> The processor is running privileged
213 * Bit[0] = 1 --> The processor is running unprivileged.
214 */
215 void vResetPrivilege( void ) __attribute__( ( naked ) );
216
217 /**
218 * @brief Make a task unprivileged.
219 */
220 void vPortSwitchToUserMode( void );
221
222 /**
223 * @brief Enter critical section.
224 */
225 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
226 void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
227 #else
228 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
229 #endif
230
231 /**
232 * @brief Exit from critical section.
233 */
234 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
235 void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
236 #else
237 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
238 #endif
239
240 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
241
242 /**
243 * @brief Sets up the system call stack so that upon returning from
244 * SVC, the system call stack is used.
245 *
246 * @param pulTaskStack The current SP when the SVC was raised.
247 * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
248 * @param ucSystemCallNumber The system call number of the system call.
249 */
250 void vSystemCallEnter( uint32_t * pulTaskStack,
251 uint32_t ulLR,
252 uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
253
254 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
255
256 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
257
258 /**
259 * @brief Raise SVC for exiting from a system call.
260 */
261 void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
262
263 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
264
265 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
266
267 /**
268 * @brief Sets up the task stack so that upon returning from
269 * SVC, the task stack is used again.
270 *
271 * @param pulSystemCallStack The current SP when the SVC was raised.
272 * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
273 */
274 void vSystemCallExit( uint32_t * pulSystemCallStack,
275 uint32_t ulLR ) PRIVILEGED_FUNCTION;
276
277 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
278
279 /**
280 * @brief Checks whether or not the calling task is privileged.
281 *
282 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
283 */
284 BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
285 /*-----------------------------------------------------------*/
286
287 /* Each task maintains its own interrupt status in the critical nesting
288 * variable. Note this is not saved as part of the task context as context
289 * switches can only occur when uxCriticalNesting is zero. */
290 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
291
292 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
293
294 /*
295 * This variable is set to pdTRUE when the scheduler is started.
296 */
297 PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
298
299 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
300
301 /*
302 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
303 * FreeRTOS API functions are not called from interrupts that have been assigned
304 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
305 */
306 #if ( configASSERT_DEFINED == 1 )
307 static uint8_t ucMaxSysCallPriority = 0;
308 static uint32_t ulMaxPRIGROUPValue = 0;
309 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
310 #endif /* configASSERT_DEFINED */
311
312 /*-----------------------------------------------------------*/
313
314 /*
315 * See header file for description.
316 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters,BaseType_t xRunPrivileged,xMPU_SETTINGS * xMPUSettings)317 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
318 TaskFunction_t pxCode,
319 void * pvParameters,
320 BaseType_t xRunPrivileged,
321 xMPU_SETTINGS * xMPUSettings )
322 {
323 if( xRunPrivileged == pdTRUE )
324 {
325 xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
326 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED;
327 }
328 else
329 {
330 xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
331 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
332 }
333
334 xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
335 xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
336 xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
337 xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
338 xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
339 xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
340 xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
341 xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
342 xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
343
344 xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
345 xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
346 xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
347 xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
348 xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
349 xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
350 xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
351 xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
352 xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
353
354 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
355 {
356 /* Ensure that the system call stack is double word aligned. */
357 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
358 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
359 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
360
361 /* This is not NULL only for the duration of a system call. */
362 xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
363 }
364 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
365
366 return &( xMPUSettings->ulContext[ 19 ] );
367 }
368 /*-----------------------------------------------------------*/
369
370 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
371
vPortSVCHandler(void)372 void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
373 {
374 __asm volatile
375 (
376 ".syntax unified \n"
377 ".extern vSVCHandler_C \n"
378 ".extern vSystemCallEnter \n"
379 ".extern vSystemCallExit \n"
380 " \n"
381 "tst lr, #4 \n"
382 "ite eq \n"
383 "mrseq r0, msp \n"
384 "mrsne r0, psp \n"
385 " \n"
386 "ldr r1, [r0, #24] \n"
387 "ldrb r2, [r1, #-2] \n"
388 "cmp r2, %0 \n"
389 "blt syscall_enter \n"
390 "cmp r2, %1 \n"
391 "beq syscall_exit \n"
392 "b vSVCHandler_C \n"
393 " \n"
394 "syscall_enter: \n"
395 " mov r1, lr \n"
396 " b vSystemCallEnter \n"
397 " \n"
398 "syscall_exit: \n"
399 " mov r1, lr \n"
400 " b vSystemCallExit \n"
401 " \n"
402 : /* No outputs. */
403 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
404 : "r0", "r1", "r2", "memory"
405 );
406 }
407
408 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
409
vPortSVCHandler(void)410 void vPortSVCHandler( void )
411 {
412 /* Assumes psp was in use. */
413 __asm volatile
414 (
415 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
416 " tst lr, #4 \n"
417 " ite eq \n"
418 " mrseq r0, msp \n"
419 " mrsne r0, psp \n"
420 #else
421 " mrs r0, psp \n"
422 #endif
423 " b %0 \n"
424 ::"i" ( vSVCHandler_C ) : "r0", "memory"
425 );
426 }
427
428 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
429 /*-----------------------------------------------------------*/
430
vSVCHandler_C(uint32_t * pulParam)431 void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
432 {
433 uint8_t ucSVCNumber;
434 uint32_t ulPC;
435
436 #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
437 #if defined( __ARMCC_VERSION )
438
439 /* Declaration when these variable are defined in code instead of being
440 * exported from linker scripts. */
441 extern uint32_t * __syscalls_flash_start__;
442 extern uint32_t * __syscalls_flash_end__;
443 #else
444 /* Declaration when these variable are exported from linker scripts. */
445 extern uint32_t __syscalls_flash_start__[];
446 extern uint32_t __syscalls_flash_end__[];
447 #endif /* #if defined( __ARMCC_VERSION ) */
448 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */
449
450 /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
451 * argument (r0) is pulParam[ 0 ]. */
452 ulPC = pulParam[ portOFFSET_TO_PC ];
453 ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
454
455 switch( ucSVCNumber )
456 {
457 case portSVC_START_SCHEDULER:
458 prvRestoreContextOfFirstTask();
459 break;
460
461 case portSVC_YIELD:
462 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
463
464 /* Barriers are normally not required
465 * but do ensure the code is completely
466 * within the specified behaviour for the
467 * architecture. */
468 __asm volatile ( "dsb" ::: "memory" );
469 __asm volatile ( "isb" );
470
471 break;
472
473 #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
474 #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
475 case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
476 * svc was raised from any of the
477 * system calls. */
478
479 if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
480 ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
481 {
482 __asm volatile
483 (
484 " mrs r1, control \n" /* Obtain current control value. */
485 " bic r1, #1 \n" /* Set privilege bit. */
486 " msr control, r1 \n" /* Write back new control value. */
487 ::: "r1", "memory"
488 );
489 }
490
491 break;
492 #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
493 case portSVC_RAISE_PRIVILEGE:
494 __asm volatile
495 (
496 " mrs r1, control \n" /* Obtain current control value. */
497 " bic r1, #1 \n" /* Set privilege bit. */
498 " msr control, r1 \n" /* Write back new control value. */
499 ::: "r1", "memory"
500 );
501 break;
502 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
503 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
504
505 default: /* Unknown SVC call. */
506 break;
507 }
508 }
509 /*-----------------------------------------------------------*/
510
511 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
512
vSystemCallEnter(uint32_t * pulTaskStack,uint32_t ulLR,uint8_t ucSystemCallNumber)513 void vSystemCallEnter( uint32_t * pulTaskStack,
514 uint32_t ulLR,
515 uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
516 {
517 extern TaskHandle_t pxCurrentTCB;
518 extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
519 xMPU_SETTINGS * pxMpuSettings;
520 uint32_t * pulSystemCallStack;
521 uint32_t ulStackFrameSize, ulSystemCallLocation, i;
522
523 #if defined( __ARMCC_VERSION )
524 /* Declaration when these variable are defined in code instead of being
525 * exported from linker scripts. */
526 extern uint32_t * __syscalls_flash_start__;
527 extern uint32_t * __syscalls_flash_end__;
528 #else
529 /* Declaration when these variable are exported from linker scripts. */
530 extern uint32_t __syscalls_flash_start__[];
531 extern uint32_t __syscalls_flash_end__[];
532 #endif /* #if defined( __ARMCC_VERSION ) */
533
534 ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
535 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
536
537 /* Checks:
538 * 1. SVC is raised from the system call section (i.e. application is
539 * not raising SVC directly).
540 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
541 * it is non-NULL only during the execution of a system call (i.e.
542 * between system call enter and exit).
543 * 3. System call is not for a kernel API disabled by the configuration
544 * in FreeRTOSConfig.h.
545 * 4. We do not need to check that ucSystemCallNumber is within range
546 * because the assembly SVC handler checks that before calling
547 * this function.
548 */
549 if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
550 ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
551 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
552 ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
553 {
554 pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
555
556 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
557 {
558 /* Extended frame i.e. FPU in use. */
559 ulStackFrameSize = 26;
560 __asm volatile (
561 " vpush {s0} \n" /* Trigger lazy stacking. */
562 " vpop {s0} \n" /* Nullify the affect of the above instruction. */
563 ::: "memory"
564 );
565 }
566 else
567 {
568 /* Standard frame i.e. FPU not in use. */
569 ulStackFrameSize = 8;
570 }
571
572 /* Make space on the system call stack for the stack frame. */
573 pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
574
575 /* Copy the stack frame. */
576 for( i = 0; i < ulStackFrameSize; i++ )
577 {
578 pulSystemCallStack[ i ] = pulTaskStack[ i ];
579 }
580
581 /* Use the pulSystemCallStack in thread mode. */
582 __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
583
584 /* Raise the privilege for the duration of the system call. */
585 __asm volatile (
586 " mrs r1, control \n" /* Obtain current control value. */
587 " bic r1, #1 \n" /* Clear nPRIV bit. */
588 " msr control, r1 \n" /* Write back new control value. */
589 ::: "r1", "memory"
590 );
591
592 /* Remember the location where we should copy the stack frame when we exit from
593 * the system call. */
594 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
595
596 /* Store the value of the Link Register before the SVC was raised.
597 * It contains the address of the caller of the System Call entry
598 * point (i.e. the caller of the MPU_<API>). We need to restore it
599 * when we exit from the system call. */
600 pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
601
602 /* Start executing the system call upon returning from this handler. */
603 pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
604 /* Raise a request to exit from the system call upon finishing the
605 * system call. */
606 pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
607
608 /* Record if the hardware used padding to force the stack pointer
609 * to be double word aligned. */
610 if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
611 {
612 pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
613 }
614 else
615 {
616 pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
617 }
618
619 /* We ensure in pxPortInitialiseStack that the system call stack is
620 * double word aligned and therefore, there is no need of padding.
621 * Clear the bit[9] of stacked xPSR. */
622 pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
623 }
624 }
625
626 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
627 /*-----------------------------------------------------------*/
628
629 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
630
vRequestSystemCallExit(void)631 void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
632 {
633 __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
634 }
635
636 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
637 /*-----------------------------------------------------------*/
638
639 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
640
vSystemCallExit(uint32_t * pulSystemCallStack,uint32_t ulLR)641 void vSystemCallExit( uint32_t * pulSystemCallStack,
642 uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
643 {
644 extern TaskHandle_t pxCurrentTCB;
645 xMPU_SETTINGS * pxMpuSettings;
646 uint32_t * pulTaskStack;
647 uint32_t ulStackFrameSize, ulSystemCallLocation, i;
648
649 #if defined( __ARMCC_VERSION )
650 /* Declaration when these variable are defined in code instead of being
651 * exported from linker scripts. */
652 extern uint32_t * __privileged_functions_start__;
653 extern uint32_t * __privileged_functions_end__;
654 #else
655 /* Declaration when these variable are exported from linker scripts. */
656 extern uint32_t __privileged_functions_start__[];
657 extern uint32_t __privileged_functions_end__[];
658 #endif /* #if defined( __ARMCC_VERSION ) */
659
660 ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
661 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
662
663 /* Checks:
664 * 1. SVC is raised from the privileged code (i.e. application is not
665 * raising SVC directly). This SVC is only raised from
666 * vRequestSystemCallExit which is in the privileged code section.
667 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
668 * this means that we previously entered a system call and the
669 * application is not attempting to exit without entering a system
670 * call.
671 */
672 if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
673 ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
674 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
675 {
676 pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
677
678 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
679 {
680 /* Extended frame i.e. FPU in use. */
681 ulStackFrameSize = 26;
682 __asm volatile (
683 " vpush {s0} \n" /* Trigger lazy stacking. */
684 " vpop {s0} \n" /* Nullify the affect of the above instruction. */
685 ::: "memory"
686 );
687 }
688 else
689 {
690 /* Standard frame i.e. FPU not in use. */
691 ulStackFrameSize = 8;
692 }
693
694 /* Make space on the task stack for the stack frame. */
695 pulTaskStack = pulTaskStack - ulStackFrameSize;
696
697 /* Copy the stack frame. */
698 for( i = 0; i < ulStackFrameSize; i++ )
699 {
700 pulTaskStack[ i ] = pulSystemCallStack[ i ];
701 }
702
703 /* Use the pulTaskStack in thread mode. */
704 __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
705
706 /* Drop the privilege before returning to the thread mode. */
707 __asm volatile (
708 " mrs r1, control \n" /* Obtain current control value. */
709 " orr r1, #1 \n" /* Set nPRIV bit. */
710 " msr control, r1 \n" /* Write back new control value. */
711 ::: "r1", "memory"
712 );
713
714 /* Return to the caller of the System Call entry point (i.e. the
715 * caller of the MPU_<API>). */
716 pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
717 /* Ensure that LR has a valid value.*/
718 pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
719
720 /* If the hardware used padding to force the stack pointer
721 * to be double word aligned, set the stacked xPSR bit[9],
722 * otherwise clear it. */
723 if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
724 {
725 pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
726 }
727 else
728 {
729 pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
730 }
731
732 /* This is not NULL only for the duration of the system call. */
733 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
734 }
735 }
736
737 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
738 /*-----------------------------------------------------------*/
739
xPortIsTaskPrivileged(void)740 BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
741 {
742 BaseType_t xTaskIsPrivileged = pdFALSE;
743 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
744
745 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
746 {
747 xTaskIsPrivileged = pdTRUE;
748 }
749
750 return xTaskIsPrivileged;
751 }
752 /*-----------------------------------------------------------*/
753
prvRestoreContextOfFirstTask(void)754 static void prvRestoreContextOfFirstTask( void )
755 {
756 __asm volatile
757 (
758 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
759 " ldr r0, [r0] \n"
760 " ldr r0, [r0] \n"
761 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
762 " \n"
763 /*------------ Program MPU. ------------ */
764 " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
765 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
766 " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
767 " \n"
768 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
769 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
770 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
771 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
772 " str r3, [r0] \n" /* Disable MPU. */
773 " \n"
774 " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
775 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
776 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
777 " \n"
778 #if ( configTOTAL_MPU_REGIONS == 16 )
779 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 8]. */
780 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 8]. */
781 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 9 - 12]. */
782 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 9 - 12]. */
783 #endif /* configTOTAL_MPU_REGIONS == 16. */
784 " \n"
785 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
786 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
787 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
788 " str r3, [r0] \n" /* Enable MPU. */
789 " dsb \n" /* Force memory writes before continuing. */
790 " \n"
791 /*---------- Restore Context. ---------- */
792 " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
793 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
794 " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
795 " \n"
796 " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
797 " msr psp, r0 \n"
798 " stmia r0, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
799 " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */
800 " msr control, r3 \n"
801 " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */
802 " \n"
803 " mov r0, #0 \n"
804 " msr basepri, r0 \n"
805 " bx lr \n"
806 " \n"
807 " .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
808 " .align 4 \n"
809 " pxCurrentTCBConst2: .word pxCurrentTCB\n"
810 );
811 }
812 /*-----------------------------------------------------------*/
813
814 /*
815 * See header file for description.
816 */
xPortStartScheduler(void)817 BaseType_t xPortStartScheduler( void )
818 {
819 /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
820 * and r0p1 cores. */
821 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
822 configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
823 #else
824
825 /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
826 * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
827 * FreeRTOSConfig.h. */
828 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
829 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
830 #endif
831
832 /* An application can install FreeRTOS interrupt handlers in one of the
833 * following ways:
834 * 1. Direct Routing - Install the functions vPortSVCHandler and
835 * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
836 * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
837 * interrupts and route program control from those handlers to
838 * vPortSVCHandler and xPortPendSVHandler functions.
839 *
840 * Applications that use Indirect Routing must set
841 * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
842 * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
843 * is 1, should be preferred when possible. */
844 #if ( configCHECK_HANDLER_INSTALLATION == 1 )
845 {
846 const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
847
848 /* Validate that the application has correctly installed the FreeRTOS
849 * handlers for SVCall and PendSV interrupts. We do not check the
850 * installation of the SysTick handler because the application may
851 * choose to drive the RTOS tick using a timer other than the SysTick
852 * timer by overriding the weak function vPortSetupTimerInterrupt().
853 *
854 * Assertion failures here indicate incorrect installation of the
855 * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
856 * https://www.FreeRTOS.org/FAQHelp.html.
857 *
858 * Systems with a configurable address for the interrupt vector table
859 * can also encounter assertion failures or even system faults here if
860 * VTOR is not set correctly to point to the application's vector table. */
861 configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
862 configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
863 }
864 #endif /* configCHECK_HANDLER_INSTALLATION */
865
866 #if ( configASSERT_DEFINED == 1 )
867 {
868 volatile uint8_t ucOriginalPriority;
869 volatile uint32_t ulImplementedPrioBits = 0;
870 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
871 volatile uint8_t ucMaxPriorityValue;
872
873 /* Determine the maximum priority from which ISR safe FreeRTOS API
874 * functions can be called. ISR safe functions are those that end in
875 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
876 * ensure interrupt entry is as fast and simple as possible.
877 *
878 * Save the interrupt priority value that is about to be clobbered. */
879 ucOriginalPriority = *pucFirstUserPriorityRegister;
880
881 /* Determine the number of priority bits available. First write to all
882 * possible bits. */
883 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
884
885 /* Read the value back to see how many bits stuck. */
886 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
887
888 /* Use the same mask on the maximum system call priority. */
889 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
890
891 /* Check that the maximum system call priority is nonzero after
892 * accounting for the number of priority bits supported by the
893 * hardware. A priority of 0 is invalid because setting the BASEPRI
894 * register to 0 unmasks all interrupts, and interrupts with priority 0
895 * cannot be masked using BASEPRI.
896 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
897 configASSERT( ucMaxSysCallPriority );
898
899 /* Check that the bits not implemented in hardware are zero in
900 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
901 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
902
903 /* Calculate the maximum acceptable priority group value for the number
904 * of bits read back. */
905
906 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
907 {
908 ulImplementedPrioBits++;
909 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
910 }
911
912 if( ulImplementedPrioBits == 8 )
913 {
914 /* When the hardware implements 8 priority bits, there is no way for
915 * the software to configure PRIGROUP to not have sub-priorities. As
916 * a result, the least significant bit is always used for sub-priority
917 * and there are 128 preemption priorities and 2 sub-priorities.
918 *
919 * This may cause some confusion in some cases - for example, if
920 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
921 * priority interrupts will be masked in Critical Sections as those
922 * are at the same preemption priority. This may appear confusing as
923 * 4 is higher (numerically lower) priority than
924 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
925 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
926 * to 4, this confusion does not happen and the behaviour remains the same.
927 *
928 * The following assert ensures that the sub-priority bit in the
929 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
930 * confusion. */
931 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
932 ulMaxPRIGROUPValue = 0;
933 }
934 else
935 {
936 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
937 }
938
939 /* Shift the priority group value back to its position within the AIRCR
940 * register. */
941 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
942 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
943
944 /* Restore the clobbered interrupt priority register to its original
945 * value. */
946 *pucFirstUserPriorityRegister = ucOriginalPriority;
947 }
948 #endif /* configASSERT_DEFINED */
949
950 /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
951 * the highest priority. */
952 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
953 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
954 portNVIC_SHPR2_REG = 0;
955
956 /* Configure the regions in the MPU that are common to all tasks. */
957 prvSetupMPU();
958
959 /* Start the timer that generates the tick ISR. Interrupts are disabled
960 * here already. */
961 vPortSetupTimerInterrupt();
962
963 /* Initialise the critical nesting count ready for the first task. */
964 uxCriticalNesting = 0;
965
966 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
967 {
968 xSchedulerRunning = pdTRUE;
969 }
970 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
971
972 /* Ensure the VFP is enabled - it should be anyway. */
973 vPortEnableVFP();
974
975 /* Lazy save always. */
976 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
977
978 /* Start the first task. This also clears the bit that indicates the FPU is
979 * in use in case the FPU was used before the scheduler was started - which
980 * would otherwise result in the unnecessary leaving of space in the SVC stack
981 * for lazy saving of FPU registers. */
982 __asm volatile (
983 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
984 " ldr r0, [r0] \n"
985 " ldr r0, [r0] \n"
986 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
987 " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
988 " msr control, r0 \n"
989 " cpsie i \n" /* Globally enable interrupts. */
990 " cpsie f \n"
991 " dsb \n"
992 " isb \n"
993 " svc %0 \n" /* System call to start first task. */
994 " nop \n"
995 " .ltorg \n"
996 ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
997
998 /* Should not get here! */
999 return 0;
1000 }
1001 /*-----------------------------------------------------------*/
1002
vPortEndScheduler(void)1003 void vPortEndScheduler( void )
1004 {
1005 /* Not implemented in ports where there is nothing to return to.
1006 * Artificially force an assert. */
1007 configASSERT( uxCriticalNesting == 1000UL );
1008 }
1009 /*-----------------------------------------------------------*/
1010
vPortEnterCritical(void)1011 void vPortEnterCritical( void )
1012 {
1013 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
1014 if( portIS_PRIVILEGED() == pdFALSE )
1015 {
1016 portRAISE_PRIVILEGE();
1017 portMEMORY_BARRIER();
1018
1019 portDISABLE_INTERRUPTS();
1020 uxCriticalNesting++;
1021 portMEMORY_BARRIER();
1022
1023 portRESET_PRIVILEGE();
1024 portMEMORY_BARRIER();
1025 }
1026 else
1027 {
1028 portDISABLE_INTERRUPTS();
1029 uxCriticalNesting++;
1030 }
1031 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1032 portDISABLE_INTERRUPTS();
1033 uxCriticalNesting++;
1034 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1035 }
1036 /*-----------------------------------------------------------*/
1037
vPortExitCritical(void)1038 void vPortExitCritical( void )
1039 {
1040 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
1041 if( portIS_PRIVILEGED() == pdFALSE )
1042 {
1043 portRAISE_PRIVILEGE();
1044 portMEMORY_BARRIER();
1045
1046 configASSERT( uxCriticalNesting );
1047 uxCriticalNesting--;
1048
1049 if( uxCriticalNesting == 0 )
1050 {
1051 portENABLE_INTERRUPTS();
1052 }
1053
1054 portMEMORY_BARRIER();
1055
1056 portRESET_PRIVILEGE();
1057 portMEMORY_BARRIER();
1058 }
1059 else
1060 {
1061 configASSERT( uxCriticalNesting );
1062 uxCriticalNesting--;
1063
1064 if( uxCriticalNesting == 0 )
1065 {
1066 portENABLE_INTERRUPTS();
1067 }
1068 }
1069 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1070 configASSERT( uxCriticalNesting );
1071 uxCriticalNesting--;
1072
1073 if( uxCriticalNesting == 0 )
1074 {
1075 portENABLE_INTERRUPTS();
1076 }
1077 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1078 }
1079 /*-----------------------------------------------------------*/
1080
xPortPendSVHandler(void)1081 void xPortPendSVHandler( void )
1082 {
1083 /* This is a naked function. */
1084
1085 __asm volatile
1086 (
1087 " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
1088 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
1089 " ldr r1, [r2] \n" /* r1 = Location where the context should be saved. */
1090 " \n"
1091 /*------------ Save Context. ----------- */
1092 " mrs r3, control \n"
1093 " mrs r0, psp \n"
1094 " isb \n"
1095 " \n"
1096 " add r0, r0, #0x20 \n" /* Move r0 to location where s0 is saved. */
1097 " tst lr, #0x10 \n"
1098 " ittt eq \n"
1099 " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */
1100 " vldmiaeq r0, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */
1101 " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */
1102 " sub r0, r0, #0x20 \n" /* Set r0 back to the location of hardware saved context. */
1103 " \n"
1104 " stmia r1!, {r3-r11, lr} \n" /* Store CONTROL register, r4-r11 and LR. */
1105 " ldmia r0, {r4-r11} \n" /* Copy hardware saved context into r4-r11. */
1106 " stmia r1!, {r0, r4-r11} \n" /* Store original PSP (after hardware has saved context) and the hardware saved context. */
1107 " str r1, [r2] \n" /* Save the location from where the context should be restored as the first member of TCB. */
1108 " \n"
1109 /*---------- Select next task. --------- */
1110 " mov r0, %0 \n"
1111 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
1112 " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
1113 #endif
1114 " msr basepri, r0 \n"
1115 " dsb \n"
1116 " isb \n"
1117 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
1118 " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
1119 #endif
1120 " bl vTaskSwitchContext \n"
1121 " mov r0, #0 \n"
1122 " msr basepri, r0 \n"
1123 " \n"
1124 /*------------ Program MPU. ------------ */
1125 " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
1126 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
1127 " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
1128 " \n"
1129 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
1130 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
1131 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
1132 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
1133 " str r3, [r0] \n" /* Disable MPU. */
1134 " \n"
1135 " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
1136 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
1137 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
1138 " \n"
1139 #if ( configTOTAL_MPU_REGIONS == 16 )
1140 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
1141 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
1142 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
1143 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
1144 #endif /* configTOTAL_MPU_REGIONS == 16. */
1145 " \n"
1146 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
1147 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
1148 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
1149 " str r3, [r0] \n" /* Enable MPU. */
1150 " dsb \n" /* Force memory writes before continuing. */
1151 " \n"
1152 /*---------- Restore Context. ---------- */
1153 " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
1154 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
1155 " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
1156 " \n"
1157 " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
1158 " msr psp, r0 \n"
1159 " stmia r0!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
1160 " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */
1161 " msr control, r3 \n"
1162
1163 " tst lr, #0x10 \n"
1164 " ittt eq \n"
1165 " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */
1166 " vstmiaeq r0!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */
1167 " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */
1168
1169 " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */
1170 " bx lr \n"
1171 " \n"
1172 " .ltorg \n" /* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */
1173 " .align 4 \n"
1174 " pxCurrentTCBConst: .word pxCurrentTCB \n"
1175 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
1176 );
1177 }
1178 /*-----------------------------------------------------------*/
1179
xPortSysTickHandler(void)1180 void xPortSysTickHandler( void )
1181 {
1182 uint32_t ulDummy;
1183
1184 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
1185 traceISR_ENTER();
1186 {
1187 /* Increment the RTOS tick. */
1188 if( xTaskIncrementTick() != pdFALSE )
1189 {
1190 traceISR_EXIT_TO_SCHEDULER();
1191 /* Pend a context switch. */
1192 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
1193 }
1194 else
1195 {
1196 traceISR_EXIT();
1197 }
1198 }
1199 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
1200 }
1201 /*-----------------------------------------------------------*/
1202
1203 /*
1204 * Setup the systick timer to generate the tick interrupts at the required
1205 * frequency.
1206 */
vPortSetupTimerInterrupt(void)1207 __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
1208 {
1209 /* Stop and clear the SysTick. */
1210 portNVIC_SYSTICK_CTRL_REG = 0UL;
1211 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
1212
1213 /* Configure SysTick to interrupt at the requested rate. */
1214 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
1215 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
1216 }
1217 /*-----------------------------------------------------------*/
1218
1219 /* This is a naked function. */
vPortEnableVFP(void)1220 static void vPortEnableVFP( void )
1221 {
1222 __asm volatile
1223 (
1224 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
1225 " ldr r1, [r0] \n"
1226 " \n"
1227 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
1228 " str r1, [r0] \n"
1229 " bx r14 \n"
1230 " .ltorg \n"
1231 );
1232 }
1233 /*-----------------------------------------------------------*/
1234
prvSetupMPU(void)1235 static void prvSetupMPU( void )
1236 {
1237 #if defined( __ARMCC_VERSION )
1238
1239 /* Declaration when these variable are defined in code instead of being
1240 * exported from linker scripts. */
1241 extern uint32_t * __privileged_functions_start__;
1242 extern uint32_t * __privileged_functions_end__;
1243 extern uint32_t * __FLASH_segment_start__;
1244 extern uint32_t * __FLASH_segment_end__;
1245 extern uint32_t * __privileged_data_start__;
1246 extern uint32_t * __privileged_data_end__;
1247 #else
1248 /* Declaration when these variable are exported from linker scripts. */
1249 extern uint32_t __privileged_functions_start__[];
1250 extern uint32_t __privileged_functions_end__[];
1251 extern uint32_t __FLASH_segment_start__[];
1252 extern uint32_t __FLASH_segment_end__[];
1253 extern uint32_t __privileged_data_start__[];
1254 extern uint32_t __privileged_data_end__[];
1255 #endif /* if defined( __ARMCC_VERSION ) */
1256
1257 /* The only permitted number of regions are 8 or 16. */
1258 configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
1259
1260 /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
1261 configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
1262
1263 /* Check the expected MPU is present. */
1264 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
1265 {
1266 /* First setup the unprivileged flash for unprivileged read only access. */
1267 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
1268 ( portMPU_REGION_VALID ) |
1269 ( portUNPRIVILEGED_FLASH_REGION );
1270
1271 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
1272 ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1273 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
1274 ( portMPU_REGION_ENABLE );
1275
1276 /* Setup the privileged flash for privileged only access. This is where
1277 * the kernel code is placed. */
1278 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
1279 ( portMPU_REGION_VALID ) |
1280 ( portPRIVILEGED_FLASH_REGION );
1281
1282 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
1283 ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1284 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
1285 ( portMPU_REGION_ENABLE );
1286
1287 /* Setup the privileged data RAM region. This is where the kernel data
1288 * is placed. */
1289 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
1290 ( portMPU_REGION_VALID ) |
1291 ( portPRIVILEGED_RAM_REGION );
1292
1293 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
1294 ( portMPU_REGION_EXECUTE_NEVER ) |
1295 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1296 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
1297 ( portMPU_REGION_ENABLE );
1298
1299 /* By default allow everything to access the general peripherals. The
1300 * system peripherals and registers are protected. */
1301 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
1302 ( portMPU_REGION_VALID ) |
1303 ( portGENERAL_PERIPHERALS_REGION );
1304
1305 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
1306 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
1307 ( portMPU_REGION_ENABLE );
1308
1309 /* Enable the memory fault exception. */
1310 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
1311
1312 /* Enable the MPU with the background region configured. */
1313 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
1314 }
1315 }
1316 /*-----------------------------------------------------------*/
1317
prvGetMPURegionSizeSetting(uint32_t ulActualSizeInBytes)1318 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
1319 {
1320 uint32_t ulRegionSize, ulReturnValue = 4;
1321
1322 /* 32 is the smallest region size, 31 is the largest valid value for
1323 * ulReturnValue. */
1324 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
1325 {
1326 if( ulActualSizeInBytes <= ulRegionSize )
1327 {
1328 break;
1329 }
1330 else
1331 {
1332 ulReturnValue++;
1333 }
1334 }
1335
1336 /* Shift the code by one before returning so it can be written directly
1337 * into the the correct bit position of the attribute register. */
1338 return( ulReturnValue << 1UL );
1339 }
1340 /*-----------------------------------------------------------*/
1341
xIsPrivileged(void)1342 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
1343 {
1344 __asm volatile
1345 (
1346 " mrs r0, control \n" /* r0 = CONTROL. */
1347 " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
1348 " ite ne \n"
1349 " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
1350 " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
1351 " bx lr \n" /* Return. */
1352 " \n"
1353 " .align 4 \n"
1354 ::: "r0", "memory"
1355 );
1356 }
1357 /*-----------------------------------------------------------*/
1358
vResetPrivilege(void)1359 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
1360 {
1361 __asm volatile
1362 (
1363 " mrs r0, control \n" /* r0 = CONTROL. */
1364 " orr r0, #1 \n" /* r0 = r0 | 1. */
1365 " msr control, r0 \n" /* CONTROL = r0. */
1366 " bx lr \n" /* Return to the caller. */
1367 ::: "r0", "memory"
1368 );
1369 }
1370 /*-----------------------------------------------------------*/
1371
vPortSwitchToUserMode(void)1372 void vPortSwitchToUserMode( void )
1373 {
1374 /* Load the current task's MPU settings from its TCB. */
1375 xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
1376
1377 /* Mark the task as unprivileged. */
1378 xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
1379
1380 /* Lower the processor's privilege level. */
1381 vResetPrivilege();
1382 }
1383 /*-----------------------------------------------------------*/
1384
vPortStoreTaskMPUSettings(xMPU_SETTINGS * xMPUSettings,const struct xMEMORY_REGION * const xRegions,StackType_t * pxBottomOfStack,configSTACK_DEPTH_TYPE uxStackDepth)1385 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
1386 const struct xMEMORY_REGION * const xRegions,
1387 StackType_t * pxBottomOfStack,
1388 configSTACK_DEPTH_TYPE uxStackDepth )
1389 {
1390 #if defined( __ARMCC_VERSION )
1391
1392 /* Declaration when these variable are defined in code instead of being
1393 * exported from linker scripts. */
1394 extern uint32_t * __SRAM_segment_start__;
1395 extern uint32_t * __SRAM_segment_end__;
1396 extern uint32_t * __privileged_data_start__;
1397 extern uint32_t * __privileged_data_end__;
1398 #else
1399 /* Declaration when these variable are exported from linker scripts. */
1400 extern uint32_t __SRAM_segment_start__[];
1401 extern uint32_t __SRAM_segment_end__[];
1402 extern uint32_t __privileged_data_start__[];
1403 extern uint32_t __privileged_data_end__[];
1404 #endif /* if defined( __ARMCC_VERSION ) */
1405
1406 int32_t lIndex;
1407 uint32_t ul;
1408
1409 if( xRegions == NULL )
1410 {
1411 /* No MPU regions are specified so allow access to all RAM. */
1412 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1413 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
1414 ( portMPU_REGION_VALID ) |
1415 ( portSTACK_REGION ); /* Region number. */
1416
1417 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1418 ( portMPU_REGION_READ_WRITE ) |
1419 ( portMPU_REGION_EXECUTE_NEVER ) |
1420 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1421 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
1422 ( portMPU_REGION_ENABLE );
1423
1424 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__;
1425 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__;
1426 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1427 tskMPU_WRITE_PERMISSION );
1428
1429 /* Invalidate user configurable regions. */
1430 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1431 {
1432 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1433 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1434 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1435 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1436 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1437 }
1438 }
1439 else
1440 {
1441 /* This function is called automatically when the task is created - in
1442 * which case the stack region parameters will be valid. At all other
1443 * times the stack parameters will not be valid and it is assumed that the
1444 * stack region has already been configured. */
1445 if( uxStackDepth > 0 )
1446 {
1447 /* Define the region that allows access to the stack. */
1448 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1449 ( ( uint32_t ) pxBottomOfStack ) |
1450 ( portMPU_REGION_VALID ) |
1451 ( portSTACK_REGION ); /* Region number. */
1452
1453 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1454 ( portMPU_REGION_READ_WRITE ) |
1455 ( portMPU_REGION_EXECUTE_NEVER ) |
1456 ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) |
1457 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1458 ( portMPU_REGION_ENABLE );
1459
1460 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
1461 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
1462 ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL );
1463 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1464 tskMPU_WRITE_PERMISSION );
1465 }
1466
1467 lIndex = 0;
1468
1469 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1470 {
1471 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
1472 {
1473 /* Translate the generic region definition contained in
1474 * xRegions into the CM4 specific MPU settings that are then
1475 * stored in xMPUSettings. */
1476 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
1477 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
1478 ( portMPU_REGION_VALID ) |
1479 ( ul - 1UL ); /* Region number. */
1480
1481 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
1482 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
1483 ( xRegions[ lIndex ].ulParameters ) |
1484 ( portMPU_REGION_ENABLE );
1485
1486 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
1487 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
1488 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1489
1490 if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
1491 ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
1492 {
1493 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
1494 }
1495
1496 if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
1497 {
1498 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
1499 }
1500 }
1501 else
1502 {
1503 /* Invalidate the region. */
1504 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1505 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1506 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1507 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1508 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1509 }
1510
1511 lIndex++;
1512 }
1513 }
1514 }
1515 /*-----------------------------------------------------------*/
1516
1517 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
1518
xPortIsAuthorizedToAccessBuffer(const void * pvBuffer,uint32_t ulBufferLength,uint32_t ulAccessRequested)1519 BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
1520 uint32_t ulBufferLength,
1521 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
1522
1523 {
1524 uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
1525 BaseType_t xAccessGranted = pdFALSE;
1526 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1527
1528 if( xSchedulerRunning == pdFALSE )
1529 {
1530 /* Grant access to all the kernel objects before the scheduler
1531 * is started. It is necessary because there is no task running
1532 * yet and therefore, we cannot use the permissions of any
1533 * task. */
1534 xAccessGranted = pdTRUE;
1535 }
1536 else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1537 {
1538 xAccessGranted = pdTRUE;
1539 }
1540 else
1541 {
1542 if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
1543 {
1544 ulBufferStartAddress = ( uint32_t ) pvBuffer;
1545 ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
1546
1547 for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
1548 {
1549 if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
1550 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1551 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1552 portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
1553 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1554 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1555 portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
1556 {
1557 xAccessGranted = pdTRUE;
1558 break;
1559 }
1560 }
1561 }
1562 }
1563
1564 return xAccessGranted;
1565 }
1566
1567 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
1568 /*-----------------------------------------------------------*/
1569
1570 #if ( configASSERT_DEFINED == 1 )
1571
vPortValidateInterruptPriority(void)1572 void vPortValidateInterruptPriority( void )
1573 {
1574 uint32_t ulCurrentInterrupt;
1575 uint8_t ucCurrentPriority;
1576
1577 /* Obtain the number of the currently executing interrupt. */
1578 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
1579
1580 /* Is the interrupt number a user defined interrupt? */
1581 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
1582 {
1583 /* Look up the interrupt's priority. */
1584 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
1585
1586 /* The following assertion will fail if a service routine (ISR) for
1587 * an interrupt that has been assigned a priority above
1588 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
1589 * function. ISR safe FreeRTOS API functions must *only* be called
1590 * from interrupts that have been assigned a priority at or below
1591 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1592 *
1593 * Numerically low interrupt priority numbers represent logically high
1594 * interrupt priorities, therefore the priority of the interrupt must
1595 * be set to a value equal to or numerically *higher* than
1596 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1597 *
1598 * Interrupts that use the FreeRTOS API must not be left at their
1599 * default priority of zero as that is the highest possible priority,
1600 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
1601 * and therefore also guaranteed to be invalid.
1602 *
1603 * FreeRTOS maintains separate thread and ISR API functions to ensure
1604 * interrupt entry is as fast and simple as possible.
1605 *
1606 * The following links provide detailed information:
1607 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
1608 * https://www.FreeRTOS.org/FAQHelp.html */
1609 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
1610 }
1611
1612 /* Priority grouping: The interrupt controller (NVIC) allows the bits
1613 * that define each interrupt's priority to be split between bits that
1614 * define the interrupt's pre-emption priority bits and bits that define
1615 * the interrupt's sub-priority. For simplicity all bits must be defined
1616 * to be pre-emption priority bits. The following assertion will fail if
1617 * this is not the case (if some bits represent a sub-priority).
1618 *
1619 * If the application only uses CMSIS libraries for interrupt
1620 * configuration then the correct setting can be achieved on all Cortex-M
1621 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
1622 * scheduler. Note however that some vendor specific peripheral libraries
1623 * assume a non-zero priority group setting, in which cases using a value
1624 * of zero will result in unpredictable behaviour. */
1625 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
1626 }
1627
1628 #endif /* configASSERT_DEFINED */
1629 /*-----------------------------------------------------------*/
1630
1631 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1632
vPortGrantAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1633 void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1634 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1635 {
1636 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1637 xMPU_SETTINGS * xTaskMpuSettings;
1638
1639 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1640 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1641
1642 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1643
1644 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
1645 }
1646
1647 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1648 /*-----------------------------------------------------------*/
1649
1650 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1651
vPortRevokeAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1652 void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1653 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1654 {
1655 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1656 xMPU_SETTINGS * xTaskMpuSettings;
1657
1658 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1659 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1660
1661 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1662
1663 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
1664 }
1665
1666 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1667 /*-----------------------------------------------------------*/
1668
1669 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
1670
1671 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
1672
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1673 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1674 {
1675 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1676 BaseType_t xAccessGranted = pdFALSE;
1677 const xMPU_SETTINGS * xTaskMpuSettings;
1678
1679 if( xSchedulerRunning == pdFALSE )
1680 {
1681 /* Grant access to all the kernel objects before the scheduler
1682 * is started. It is necessary because there is no task running
1683 * yet and therefore, we cannot use the permissions of any
1684 * task. */
1685 xAccessGranted = pdTRUE;
1686 }
1687 else
1688 {
1689 xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1690
1691 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1692 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1693
1694 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1695 {
1696 xAccessGranted = pdTRUE;
1697 }
1698 else
1699 {
1700 if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
1701 {
1702 xAccessGranted = pdTRUE;
1703 }
1704 }
1705 }
1706
1707 return xAccessGranted;
1708 }
1709
1710 #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1711
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1712 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1713 {
1714 ( void ) lInternalIndexOfKernelObject;
1715
1716 /* If Access Control List feature is not used, all the tasks have
1717 * access to all the kernel objects. */
1718 return pdTRUE;
1719 }
1720
1721 #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1722
1723 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
1724 /*-----------------------------------------------------------*/
1725
