1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM3 port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 /* Constants required to manipulate the core. Registers first... */
38 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
39 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
40 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
41 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
42 /* ...then bits in the registers. */
43 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
44 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
45 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
46 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
47 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
48 #define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
49 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
50
51 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
52 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
53 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
54
55 /* Constants required to check the validity of an interrupt priority. */
56 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
57 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
58 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
59 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
60 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
61 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
62 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
63 #define portPRIGROUP_SHIFT ( 8UL )
64
65 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
66 #define portVECTACTIVE_MASK ( 0xFFUL )
67
68 /* Constants required to set up the initial stack. */
69 #define portINITIAL_XPSR ( 0x01000000UL )
70
71 /* The systick is a 24-bit counter. */
72 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
73
74 /* A fiddle factor to estimate the number of SysTick counts that would have
75 * occurred while the SysTick counter is stopped during tickless idle
76 * calculations. */
77 #define portMISSED_COUNTS_FACTOR ( 94UL )
78
79 /* For strict compliance with the Cortex-M spec the task start address should
80 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
81 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
82
83 /* Let the user override the default SysTick clock rate. If defined by the
84 * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
85 * configuration register. */
86 #ifndef configSYSTICK_CLOCK_HZ
87 #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
88 /* Ensure the SysTick is clocked at the same frequency as the core. */
89 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
90 #else
91 /* Select the option to clock SysTick not at the same frequency as the core. */
92 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
93 #endif
94
95 /* Let the user override the pre-loading of the initial LR with the address of
96 * prvTaskExitError() in case it messes up unwinding of the stack in the
97 * debugger. */
98 #ifdef configTASK_RETURN_ADDRESS
99 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
100 #else
101 #define portTASK_RETURN_ADDRESS prvTaskExitError
102 #endif
103
104 /*
105 * Setup the timer to generate the tick interrupts. The implementation in this
106 * file is weak to allow application writers to change the timer used to
107 * generate the tick interrupt.
108 */
109 void vPortSetupTimerInterrupt( void );
110
111 /*
112 * Exception handlers.
113 */
114 void xPortPendSVHandler( void ) __attribute__( ( naked ) );
115 void xPortSysTickHandler( void );
116 void vPortSVCHandler( void ) __attribute__( ( naked ) );
117
118 /*
119 * Start first task is a separate function so it can be tested in isolation.
120 */
121 static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
122
123 /*
124 * Used to catch tasks that attempt to return from their implementing function.
125 */
126 static void prvTaskExitError( void );
127
128 /*-----------------------------------------------------------*/
129
130 /* Each task maintains its own interrupt status in the critical nesting
131 * variable. */
132 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
133
134 /*
135 * The number of SysTick increments that make up one tick period.
136 */
137 #if ( configUSE_TICKLESS_IDLE == 1 )
138 static uint32_t ulTimerCountsForOneTick = 0;
139 #endif /* configUSE_TICKLESS_IDLE */
140
141 /*
142 * The maximum number of tick periods that can be suppressed is limited by the
143 * 24 bit resolution of the SysTick timer.
144 */
145 #if ( configUSE_TICKLESS_IDLE == 1 )
146 static uint32_t xMaximumPossibleSuppressedTicks = 0;
147 #endif /* configUSE_TICKLESS_IDLE */
148
149 /*
150 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
151 * power functionality only.
152 */
153 #if ( configUSE_TICKLESS_IDLE == 1 )
154 static uint32_t ulStoppedTimerCompensation = 0;
155 #endif /* configUSE_TICKLESS_IDLE */
156
157 /*
158 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
159 * FreeRTOS API functions are not called from interrupts that have been assigned
160 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
161 */
162 #if ( configASSERT_DEFINED == 1 )
163 static uint8_t ucMaxSysCallPriority = 0;
164 static uint32_t ulMaxPRIGROUPValue = 0;
165 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
166 #endif /* configASSERT_DEFINED */
167
168 /*-----------------------------------------------------------*/
169
170 /*
171 * See header file for description.
172 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)173 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
174 TaskFunction_t pxCode,
175 void * pvParameters )
176 {
177 /* Simulate the stack frame as it would be created by a context switch
178 * interrupt. */
179 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
180 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
181 pxTopOfStack--;
182 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
183 pxTopOfStack--;
184 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
185 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
186 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
187 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
188
189 return pxTopOfStack;
190 }
191 /*-----------------------------------------------------------*/
192
prvTaskExitError(void)193 static void prvTaskExitError( void )
194 {
195 volatile uint32_t ulDummy = 0UL;
196
197 /* A function that implements a task must not exit or attempt to return to
198 * its caller as there is nothing to return to. If a task wants to exit it
199 * should instead call vTaskDelete( NULL ).
200 *
201 * Artificially force an assert() to be triggered if configASSERT() is
202 * defined, then stop here so application writers can catch the error. */
203 configASSERT( uxCriticalNesting == ~0UL );
204 portDISABLE_INTERRUPTS();
205
206 while( ulDummy == 0 )
207 {
208 /* This file calls prvTaskExitError() after the scheduler has been
209 * started to remove a compiler warning about the function being defined
210 * but never called. ulDummy is used purely to quieten other warnings
211 * about code appearing after this function is called - making ulDummy
212 * volatile makes the compiler think the function could return and
213 * therefore not output an 'unreachable code' warning for code that appears
214 * after it. */
215 }
216 }
217 /*-----------------------------------------------------------*/
218
vPortSVCHandler(void)219 void vPortSVCHandler( void )
220 {
221 __asm volatile (
222 " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */
223 " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
224 " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
225 " ldmia r0!, {r4-r11} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
226 " msr psp, r0 \n"/* Restore the task stack pointer. */
227 " isb \n"
228 " mov r0, #0 \n"
229 " msr basepri, r0 \n"
230 " orr r14, #0xd \n"
231 " bx r14 \n"
232 " \n"
233 " .align 4 \n"
234 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
235 );
236 }
237 /*-----------------------------------------------------------*/
238
prvPortStartFirstTask(void)239 static void prvPortStartFirstTask( void )
240 {
241 __asm volatile (
242 " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */
243 " ldr r0, [r0] \n"
244 " ldr r0, [r0] \n"
245 " msr msp, r0 \n"/* Set the msp back to the start of the stack. */
246 " cpsie i \n"/* Globally enable interrupts. */
247 " cpsie f \n"
248 " dsb \n"
249 " isb \n"
250 " svc 0 \n"/* System call to start first task. */
251 " nop \n"
252 " .ltorg \n"
253 );
254 }
255 /*-----------------------------------------------------------*/
256
257 /*
258 * See header file for description.
259 */
xPortStartScheduler(void)260 BaseType_t xPortStartScheduler( void )
261 {
262 #if ( configASSERT_DEFINED == 1 )
263 {
264 volatile uint8_t ucOriginalPriority;
265 volatile uint32_t ulImplementedPrioBits = 0;
266 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
267 volatile uint8_t ucMaxPriorityValue;
268
269 /* Determine the maximum priority from which ISR safe FreeRTOS API
270 * functions can be called. ISR safe functions are those that end in
271 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
272 * ensure interrupt entry is as fast and simple as possible.
273 *
274 * Save the interrupt priority value that is about to be clobbered. */
275 ucOriginalPriority = *pucFirstUserPriorityRegister;
276
277 /* Determine the number of priority bits available. First write to all
278 * possible bits. */
279 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
280
281 /* Read the value back to see how many bits stuck. */
282 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
283
284 /* Use the same mask on the maximum system call priority. */
285 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
286
287 /* Check that the maximum system call priority is nonzero after
288 * accounting for the number of priority bits supported by the
289 * hardware. A priority of 0 is invalid because setting the BASEPRI
290 * register to 0 unmasks all interrupts, and interrupts with priority 0
291 * cannot be masked using BASEPRI.
292 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
293 configASSERT( ucMaxSysCallPriority );
294
295 /* Check that the bits not implemented in hardware are zero in
296 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
297 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
298
299 /* Calculate the maximum acceptable priority group value for the number
300 * of bits read back. */
301
302 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
303 {
304 ulImplementedPrioBits++;
305 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
306 }
307
308 if( ulImplementedPrioBits == 8 )
309 {
310 /* When the hardware implements 8 priority bits, there is no way for
311 * the software to configure PRIGROUP to not have sub-priorities. As
312 * a result, the least significant bit is always used for sub-priority
313 * and there are 128 preemption priorities and 2 sub-priorities.
314 *
315 * This may cause some confusion in some cases - for example, if
316 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
317 * priority interrupts will be masked in Critical Sections as those
318 * are at the same preemption priority. This may appear confusing as
319 * 4 is higher (numerically lower) priority than
320 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
321 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
322 * to 4, this confusion does not happen and the behaviour remains the same.
323 *
324 * The following assert ensures that the sub-priority bit in the
325 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
326 * confusion. */
327 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
328 ulMaxPRIGROUPValue = 0;
329 }
330 else
331 {
332 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
333 }
334
335 /* Shift the priority group value back to its position within the AIRCR
336 * register. */
337 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
338 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
339
340 /* Restore the clobbered interrupt priority register to its original
341 * value. */
342 *pucFirstUserPriorityRegister = ucOriginalPriority;
343 }
344 #endif /* configASSERT_DEFINED */
345
346 /* Make PendSV and SysTick the lowest priority interrupts. */
347 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
348 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
349
350 /* Start the timer that generates the tick ISR. Interrupts are disabled
351 * here already. */
352 vPortSetupTimerInterrupt();
353
354 /* Initialise the critical nesting count ready for the first task. */
355 uxCriticalNesting = 0;
356
357 /* Start the first task. */
358 prvPortStartFirstTask();
359
360 /* Should never get here as the tasks will now be executing! Call the task
361 * exit error function to prevent compiler warnings about a static function
362 * not being called in the case that the application writer overrides this
363 * functionality by defining configTASK_RETURN_ADDRESS. Call
364 * vTaskSwitchContext() so link time optimisation does not remove the
365 * symbol. */
366 vTaskSwitchContext();
367 prvTaskExitError();
368
369 /* Should not get here! */
370 return 0;
371 }
372 /*-----------------------------------------------------------*/
373
vPortEndScheduler(void)374 void vPortEndScheduler( void )
375 {
376 /* Not implemented in ports where there is nothing to return to.
377 * Artificially force an assert. */
378 configASSERT( uxCriticalNesting == 1000UL );
379 }
380 /*-----------------------------------------------------------*/
381
vPortEnterCritical(void)382 void vPortEnterCritical( void )
383 {
384 portDISABLE_INTERRUPTS();
385 uxCriticalNesting++;
386
387 /* This is not the interrupt safe version of the enter critical function so
388 * assert() if it is being called from an interrupt context. Only API
389 * functions that end in "FromISR" can be used in an interrupt. Only assert if
390 * the critical nesting count is 1 to protect against recursive calls if the
391 * assert function also uses a critical section. */
392 if( uxCriticalNesting == 1 )
393 {
394 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
395 }
396 }
397 /*-----------------------------------------------------------*/
398
vPortExitCritical(void)399 void vPortExitCritical( void )
400 {
401 configASSERT( uxCriticalNesting );
402 uxCriticalNesting--;
403
404 if( uxCriticalNesting == 0 )
405 {
406 portENABLE_INTERRUPTS();
407 }
408 }
409 /*-----------------------------------------------------------*/
410
xPortPendSVHandler(void)411 void xPortPendSVHandler( void )
412 {
413 /* This is a naked function. */
414
415 __asm volatile
416 (
417 " mrs r0, psp \n"
418 " isb \n"
419 " \n"
420 " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
421 " ldr r2, [r3] \n"
422 " \n"
423 " stmdb r0!, {r4-r11} \n"/* Save the remaining registers. */
424 " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */
425 " \n"
426 " stmdb sp!, {r3, r14} \n"
427 " mov r0, %0 \n"
428 " msr basepri, r0 \n"
429 " bl vTaskSwitchContext \n"
430 " mov r0, #0 \n"
431 " msr basepri, r0 \n"
432 " ldmia sp!, {r3, r14} \n"
433 " \n"/* Restore the context, including the critical nesting count. */
434 " ldr r1, [r3] \n"
435 " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
436 " ldmia r0!, {r4-r11} \n"/* Pop the registers. */
437 " msr psp, r0 \n"
438 " isb \n"
439 " bx r14 \n"
440 " \n"
441 " .align 4 \n"
442 "pxCurrentTCBConst: .word pxCurrentTCB \n"
443 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
444 );
445 }
446 /*-----------------------------------------------------------*/
447
xPortSysTickHandler(void)448 void xPortSysTickHandler( void )
449 {
450 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
451 * executes all interrupts must be unmasked. There is therefore no need to
452 * save and then restore the interrupt mask value as its value is already
453 * known. */
454 portDISABLE_INTERRUPTS();
455 {
456 /* Increment the RTOS tick. */
457 if( xTaskIncrementTick() != pdFALSE )
458 {
459 /* A context switch is required. Context switching is performed in
460 * the PendSV interrupt. Pend the PendSV interrupt. */
461 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
462 }
463 }
464 portENABLE_INTERRUPTS();
465 }
466 /*-----------------------------------------------------------*/
467
468 #if ( configUSE_TICKLESS_IDLE == 1 )
469
vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)470 __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
471 {
472 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
473 TickType_t xModifiableIdleTime;
474
475 /* Make sure the SysTick reload value does not overflow the counter. */
476 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
477 {
478 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
479 }
480
481 /* Enter a critical section but don't use the taskENTER_CRITICAL()
482 * method as that will mask interrupts that should exit sleep mode. */
483 __asm volatile ( "cpsid i" ::: "memory" );
484 __asm volatile ( "dsb" );
485 __asm volatile ( "isb" );
486
487 /* If a context switch is pending or a task is waiting for the scheduler
488 * to be unsuspended then abandon the low power entry. */
489 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
490 {
491 /* Re-enable interrupts - see comments above the cpsid instruction
492 * above. */
493 __asm volatile ( "cpsie i" ::: "memory" );
494 }
495 else
496 {
497 /* Stop the SysTick momentarily. The time the SysTick is stopped for
498 * is accounted for as best it can be, but using the tickless mode will
499 * inevitably result in some tiny drift of the time maintained by the
500 * kernel with respect to calendar time. */
501 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
502
503 /* Use the SysTick current-value register to determine the number of
504 * SysTick decrements remaining until the next tick interrupt. If the
505 * current-value register is zero, then there are actually
506 * ulTimerCountsForOneTick decrements remaining, not zero, because the
507 * SysTick requests the interrupt when decrementing from 1 to 0. */
508 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
509
510 if( ulSysTickDecrementsLeft == 0 )
511 {
512 ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
513 }
514
515 /* Calculate the reload value required to wait xExpectedIdleTime
516 * tick periods. -1 is used because this code normally executes part
517 * way through the first tick period. But if the SysTick IRQ is now
518 * pending, then clear the IRQ, suppressing the first tick, and correct
519 * the reload value to reflect that the second tick period is already
520 * underway. The expected idle time is always at least two ticks. */
521 ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
522
523 if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
524 {
525 portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
526 ulReloadValue -= ulTimerCountsForOneTick;
527 }
528
529 if( ulReloadValue > ulStoppedTimerCompensation )
530 {
531 ulReloadValue -= ulStoppedTimerCompensation;
532 }
533
534 /* Set the new reload value. */
535 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
536
537 /* Clear the SysTick count flag and set the count value back to
538 * zero. */
539 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
540
541 /* Restart SysTick. */
542 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
543
544 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
545 * set its parameter to 0 to indicate that its implementation contains
546 * its own wait for interrupt or wait for event instruction, and so wfi
547 * should not be executed again. However, the original expected idle
548 * time variable must remain unmodified, so a copy is taken. */
549 xModifiableIdleTime = xExpectedIdleTime;
550 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
551
552 if( xModifiableIdleTime > 0 )
553 {
554 __asm volatile ( "dsb" ::: "memory" );
555 __asm volatile ( "wfi" );
556 __asm volatile ( "isb" );
557 }
558
559 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
560
561 /* Re-enable interrupts to allow the interrupt that brought the MCU
562 * out of sleep mode to execute immediately. See comments above
563 * the cpsid instruction above. */
564 __asm volatile ( "cpsie i" ::: "memory" );
565 __asm volatile ( "dsb" );
566 __asm volatile ( "isb" );
567
568 /* Disable interrupts again because the clock is about to be stopped
569 * and interrupts that execute while the clock is stopped will increase
570 * any slippage between the time maintained by the RTOS and calendar
571 * time. */
572 __asm volatile ( "cpsid i" ::: "memory" );
573 __asm volatile ( "dsb" );
574 __asm volatile ( "isb" );
575
576 /* Disable the SysTick clock without reading the
577 * portNVIC_SYSTICK_CTRL_REG register to ensure the
578 * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
579 * the time the SysTick is stopped for is accounted for as best it can
580 * be, but using the tickless mode will inevitably result in some tiny
581 * drift of the time maintained by the kernel with respect to calendar
582 * time*/
583 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
584
585 /* Determine whether the SysTick has already counted to zero. */
586 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
587 {
588 uint32_t ulCalculatedLoadValue;
589
590 /* The tick interrupt ended the sleep (or is now pending), and
591 * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
592 * with whatever remains of the new tick period. */
593 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
594
595 /* Don't allow a tiny value, or values that have somehow
596 * underflowed because the post sleep hook did something
597 * that took too long or because the SysTick current-value register
598 * is zero. */
599 if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
600 {
601 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
602 }
603
604 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
605
606 /* As the pending tick will be processed as soon as this
607 * function exits, the tick value maintained by the tick is stepped
608 * forward by one less than the time spent waiting. */
609 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
610 }
611 else
612 {
613 /* Something other than the tick interrupt ended the sleep. */
614
615 /* Use the SysTick current-value register to determine the
616 * number of SysTick decrements remaining until the expected idle
617 * time would have ended. */
618 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
619 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
620 {
621 /* If the SysTick is not using the core clock, the current-
622 * value register might still be zero here. In that case, the
623 * SysTick didn't load from the reload register, and there are
624 * ulReloadValue decrements remaining in the expected idle
625 * time, not zero. */
626 if( ulSysTickDecrementsLeft == 0 )
627 {
628 ulSysTickDecrementsLeft = ulReloadValue;
629 }
630 }
631 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
632
633 /* Work out how long the sleep lasted rounded to complete tick
634 * periods (not the ulReload value which accounted for part
635 * ticks). */
636 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
637
638 /* How many complete tick periods passed while the processor
639 * was waiting? */
640 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
641
642 /* The reload value is set to whatever fraction of a single tick
643 * period remains. */
644 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
645 }
646
647 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
648 * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
649 * the SysTick is not using the core clock, temporarily configure it to
650 * use the core clock. This configuration forces the SysTick to load
651 * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
652 * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
653 * to receive the standard value immediately. */
654 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
655 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
656 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
657 {
658 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
659 }
660 #else
661 {
662 /* The temporary usage of the core clock has served its purpose,
663 * as described above. Resume usage of the other clock. */
664 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
665
666 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
667 {
668 /* The partial tick period already ended. Be sure the SysTick
669 * counts it only once. */
670 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
671 }
672
673 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
674 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
675 }
676 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
677
678 /* Step the tick to account for any tick periods that elapsed. */
679 vTaskStepTick( ulCompleteTickPeriods );
680
681 /* Exit with interrupts enabled. */
682 __asm volatile ( "cpsie i" ::: "memory" );
683 }
684 }
685
686 #endif /* configUSE_TICKLESS_IDLE */
687 /*-----------------------------------------------------------*/
688
689 /*
690 * Setup the systick timer to generate the tick interrupts at the required
691 * frequency.
692 */
vPortSetupTimerInterrupt(void)693 __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
694 {
695 /* Calculate the constants required to configure the tick interrupt. */
696 #if ( configUSE_TICKLESS_IDLE == 1 )
697 {
698 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
699 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
700 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
701 }
702 #endif /* configUSE_TICKLESS_IDLE */
703
704 /* Stop and clear the SysTick. */
705 portNVIC_SYSTICK_CTRL_REG = 0UL;
706 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
707
708 /* Configure SysTick to interrupt at the requested rate. */
709 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
710 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
711 }
712 /*-----------------------------------------------------------*/
713
714 #if ( configASSERT_DEFINED == 1 )
715
vPortValidateInterruptPriority(void)716 void vPortValidateInterruptPriority( void )
717 {
718 uint32_t ulCurrentInterrupt;
719 uint8_t ucCurrentPriority;
720
721 /* Obtain the number of the currently executing interrupt. */
722 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
723
724 /* Is the interrupt number a user defined interrupt? */
725 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
726 {
727 /* Look up the interrupt's priority. */
728 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
729
730 /* The following assertion will fail if a service routine (ISR) for
731 * an interrupt that has been assigned a priority above
732 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
733 * function. ISR safe FreeRTOS API functions must *only* be called
734 * from interrupts that have been assigned a priority at or below
735 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
736 *
737 * Numerically low interrupt priority numbers represent logically high
738 * interrupt priorities, therefore the priority of the interrupt must
739 * be set to a value equal to or numerically *higher* than
740 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
741 *
742 * Interrupts that use the FreeRTOS API must not be left at their
743 * default priority of zero as that is the highest possible priority,
744 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
745 * and therefore also guaranteed to be invalid.
746 *
747 * FreeRTOS maintains separate thread and ISR API functions to ensure
748 * interrupt entry is as fast and simple as possible.
749 *
750 * The following links provide detailed information:
751 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
752 * https://www.FreeRTOS.org/FAQHelp.html */
753 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
754 }
755
756 /* Priority grouping: The interrupt controller (NVIC) allows the bits
757 * that define each interrupt's priority to be split between bits that
758 * define the interrupt's pre-emption priority bits and bits that define
759 * the interrupt's sub-priority. For simplicity all bits must be defined
760 * to be pre-emption priority bits. The following assertion will fail if
761 * this is not the case (if some bits represent a sub-priority).
762 *
763 * If the application only uses CMSIS libraries for interrupt
764 * configuration then the correct setting can be achieved on all Cortex-M
765 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
766 * scheduler. Note however that some vendor specific peripheral libraries
767 * assume a non-zero priority group setting, in which cases using a value
768 * of zero will result in unpredictable behaviour. */
769 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
770 }
771
772 #endif /* configASSERT_DEFINED */
