1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 /*-----------------------------------------------------------
31 * Implementation of functions defined in portable.h for the ARM7 port.
32 *
33 * Components that can be compiled to either ARM or THUMB mode are
34 * contained in this file. The ISR routines, which can only be compiled
35 * to ARM mode are contained in portISR.c.
36 *----------------------------------------------------------*/
37
38 /* Standard includes. */
39 #include <stdlib.h>
40
41 /* Scheduler includes. */
42 #include "FreeRTOS.h"
43 #include "task.h"
44
45 /* Processor constants. */
46 #include "AT91SAM7X256.h"
47
48 /* Constants required to setup the task context. */
49 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
50 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
51 #define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
52 #define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
53
54 /* Constants required to setup the tick ISR. */
55 #define portENABLE_TIMER ( ( uint8_t ) 0x01 )
56 #define portPRESCALE_VALUE 0x00
57 #define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
58 #define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
59
60 /* Constants required to setup the PIT. */
61 #define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )
62 #define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
63
64 #define portINT_LEVEL_SENSITIVE 0
65 #define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )
66 #define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )
67 /*-----------------------------------------------------------*/
68
69 /* Setup the timer to generate the tick interrupts. */
70 static void prvSetupTimerInterrupt( void );
71
72 /*
73 * The scheduler can only be started from ARM mode, so
74 * vPortISRStartFirstSTask() is defined in portISR.c.
75 */
76 extern void vPortISRStartFirstTask( void );
77
78 /*-----------------------------------------------------------*/
79
80 /*
81 * Initialise the stack of a task to look exactly as if a call to
82 * portSAVE_CONTEXT had been called.
83 *
84 * See header file for description.
85 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)86 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
87 TaskFunction_t pxCode,
88 void * pvParameters )
89 {
90 StackType_t * pxOriginalTOS;
91
92 pxOriginalTOS = pxTopOfStack;
93
94 /* To ensure asserts in tasks.c don't fail, although in this case the assert
95 * is not really required. */
96 pxTopOfStack--;
97
98 /* Setup the initial stack of the task. The stack is set exactly as
99 * expected by the portRESTORE_CONTEXT() macro. */
100
101 /* First on the stack is the return address - which in this case is the
102 * start of the task. The offset is added to make the return address appear
103 * as it would within an IRQ ISR. */
104 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
105 pxTopOfStack--;
106
107 *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */
108 pxTopOfStack--;
109 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
110 pxTopOfStack--;
111 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
112 pxTopOfStack--;
113 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
114 pxTopOfStack--;
115 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
116 pxTopOfStack--;
117 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
118 pxTopOfStack--;
119 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
120 pxTopOfStack--;
121 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
122 pxTopOfStack--;
123 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
124 pxTopOfStack--;
125 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
126 pxTopOfStack--;
127 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
128 pxTopOfStack--;
129 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
130 pxTopOfStack--;
131 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
132 pxTopOfStack--;
133 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
134 pxTopOfStack--;
135
136 /* When the task starts is will expect to find the function parameter in
137 * R0. */
138 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
139 pxTopOfStack--;
140
141 /* The last thing onto the stack is the status register, which is set for
142 * system mode, with interrupts enabled. */
143 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
144
145 #ifdef THUMB_INTERWORK
146 {
147 /* We want the task to start in thumb mode. */
148 *pxTopOfStack |= portTHUMB_MODE_BIT;
149 }
150 #endif
151
152 pxTopOfStack--;
153
154 /* Some optimisation levels use the stack differently to others. This
155 * means the interrupt flags cannot always be stored on the stack and will
156 * instead be stored in a variable, which is then saved as part of the
157 * tasks context. */
158 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
159
160 return pxTopOfStack;
161 }
162 /*-----------------------------------------------------------*/
163
xPortStartScheduler(void)164 BaseType_t xPortStartScheduler( void )
165 {
166 /* Start the timer that generates the tick ISR. Interrupts are disabled
167 * here already. */
168 prvSetupTimerInterrupt();
169
170 /* Start the first task. */
171 vPortISRStartFirstTask();
172
173 /* Should not get here! */
174 return 0;
175 }
176 /*-----------------------------------------------------------*/
177
vPortEndScheduler(void)178 void vPortEndScheduler( void )
179 {
180 /* It is unlikely that the ARM port will require this function as there
181 * is nothing to return to. */
182 }
183 /*-----------------------------------------------------------*/
184
185 /*
186 * Setup the timer 0 to generate the tick interrupts at the required frequency.
187 */
prvSetupTimerInterrupt(void)188 static void prvSetupTimerInterrupt( void )
189 {
190 AT91PS_PITC pxPIT = AT91C_BASE_PITC;
191
192 /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
193 * on whether the preemptive or cooperative scheduler is being used. */
194 #if configUSE_PREEMPTION == 0
195 extern void( vNonPreemptiveTick ) ( void );
196 AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vNonPreemptiveTick );
197 #else
198 extern void( vPreemptiveTick )( void );
199 AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPreemptiveTick );
200 #endif
201
202 /* Configure the PIT period. */
203 pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
204
205 /* Enable the interrupt. Global interrupts are disabled at this point so
206 * this is safe. */
207 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
208 }
209 /*-----------------------------------------------------------*/
210
