1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 /*-----------------------------------------------------------
31 * Implementation of functions defined in portable.h for the Atmel AT91R40008
32 * port.
33 *
34 * Components that can be compiled to either ARM or THUMB mode are
35 * contained in this file. The ISR routines, which can only be compiled
36 * to ARM mode are contained in portISR.c.
37 *----------------------------------------------------------*/
38
39 /* Standard includes. */
40 #include <stdlib.h>
41
42 /* Scheduler includes. */
43 #include "FreeRTOS.h"
44 #include "task.h"
45
46 /* Hardware specific definitions. */
47 #include "AT91R40008.h"
48 #include "pio.h"
49 #include "aic.h"
50 #include "tc.h"
51
52 /* Constants required to setup the task context. */
53 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
54 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
55 #define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
56 #define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
57 #define portTICK_PRIORITY_6 ( 6 )
58 /*-----------------------------------------------------------*/
59
60 /* Setup the timer to generate the tick interrupts. */
61 static void prvSetupTimerInterrupt( void );
62
63 /*
64 * The scheduler can only be started from ARM mode, so
65 * vPortISRStartFirstSTask() is defined in portISR.c.
66 */
67 extern void vPortISRStartFirstTask( void );
68
69 /*-----------------------------------------------------------*/
70
71 /*
72 * Initialise the stack of a task to look exactly as if a call to
73 * portSAVE_CONTEXT had been called.
74 *
75 * See header file for description.
76 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)77 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
78 TaskFunction_t pxCode,
79 void * pvParameters )
80 {
81 StackType_t * pxOriginalTOS;
82
83 pxOriginalTOS = pxTopOfStack;
84
85 /* To ensure asserts in tasks.c don't fail, although in this case the assert
86 * is not really required. */
87 pxTopOfStack--;
88
89 /* Setup the initial stack of the task. The stack is set exactly as
90 * expected by the portRESTORE_CONTEXT() macro. */
91
92 /* First on the stack is the return address - which in this case is the
93 * start of the task. The offset is added to make the return address appear
94 * as it would within an IRQ ISR. */
95 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
96 pxTopOfStack--;
97
98 *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
99 pxTopOfStack--;
100 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
101 pxTopOfStack--;
102 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
103 pxTopOfStack--;
104 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
105 pxTopOfStack--;
106 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
107 pxTopOfStack--;
108 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
109 pxTopOfStack--;
110 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
111 pxTopOfStack--;
112 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
113 pxTopOfStack--;
114 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
115 pxTopOfStack--;
116 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
117 pxTopOfStack--;
118 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
119 pxTopOfStack--;
120 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
121 pxTopOfStack--;
122 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
123 pxTopOfStack--;
124 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
125 pxTopOfStack--;
126
127 /* When the task starts is will expect to find the function parameter in
128 * R0. */
129 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
130 pxTopOfStack--;
131
132 /* The last thing onto the stack is the status register, which is set for
133 * system mode, with interrupts enabled. */
134 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
135
136 #ifdef THUMB_INTERWORK
137 {
138 /* We want the task to start in thumb mode. */
139 *pxTopOfStack |= portTHUMB_MODE_BIT;
140 }
141 #endif
142
143 pxTopOfStack--;
144
145 /* Some optimisation levels use the stack differently to others. This
146 * means the interrupt flags cannot always be stored on the stack and will
147 * instead be stored in a variable, which is then saved as part of the
148 * tasks context. */
149 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
150
151 return pxTopOfStack;
152 }
153 /*-----------------------------------------------------------*/
154
xPortStartScheduler(void)155 BaseType_t xPortStartScheduler( void )
156 {
157 /* Start the timer that generates the tick ISR. Interrupts are disabled
158 * here already. */
159 prvSetupTimerInterrupt();
160
161 /* Start the first task. */
162 vPortISRStartFirstTask();
163
164 /* Should not get here! */
165 return 0;
166 }
167 /*-----------------------------------------------------------*/
168
vPortEndScheduler(void)169 void vPortEndScheduler( void )
170 {
171 /* It is unlikely that the ARM port will require this function as there
172 * is nothing to return to. */
173 }
174 /*-----------------------------------------------------------*/
175
176 /*
177 * Setup the tick timer to generate the tick interrupts at the required frequency.
178 */
prvSetupTimerInterrupt(void)179 static void prvSetupTimerInterrupt( void )
180 {
181 volatile uint32_t ulDummy;
182
183 /* Enable clock to the tick timer... */
184 AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
185
186 /* Stop the tick timer... */
187 portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
188
189 /* Start with tick timer interrupts disabled... */
190 portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
191
192 /* Clear any pending tick timer interrupts... */
193 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
194
195 /* Store interrupt handler function address in tick timer vector register...
196 * The ISR installed depends on whether the preemptive or cooperative
197 * scheduler is being used. */
198 #if configUSE_PREEMPTION == 1
199 {
200 extern void( vPreemptiveTick )( void );
201 AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vPreemptiveTick;
202 }
203 #else // else use cooperative scheduler
204 {
205 extern void( vNonPreemptiveTick )( void );
206 AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vNonPreemptiveTick;
207 }
208 #endif
209
210 /* Tick timer interrupt level-sensitive, priority 6... */
211 AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
212
213 /* Enable the tick timer interrupt...
214 *
215 * First at timer level */
216 portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
217
218 /* Then at the AIC level. */
219 AT91C_BASE_AIC->AIC_IECR = ( 1 << portTIMER_AIC_CHANNEL );
220
221 /* Calculate timer compare value to achieve the desired tick rate... */
222 if( ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 ) ) <= 0xFFFF )
223 {
224 /* The tick rate is fast enough for us to use the faster timer input
225 * clock (main clock / 2). */
226 portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
227 portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 );
228 }
229 else
230 {
231 /* We must use a slower timer input clock (main clock / 8) because the
232 * tick rate is too slow for the faster input clock. */
233 portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
234 portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 8 );
235 }
236
237 /* Start tick timer... */
238 portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
239 }
240 /*-----------------------------------------------------------*/
241
