1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM3 port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 #if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
38 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
39 #endif
40
41 /* Constants required to manipulate the core. Registers first... */
42 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
43 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
44 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
45 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
46 /* ...then bits in the registers. */
47 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
48 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
49 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
50 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
51 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
52 #define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
53 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
54
55 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
56 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
57 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
58
59 /* Constants required to check the validity of an interrupt priority. */
60 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
61 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
62 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
63 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
64 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
65 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
66 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
67 #define portPRIGROUP_SHIFT ( 8UL )
68
69 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
70 #define portVECTACTIVE_MASK ( 0xFFUL )
71
72 /* Constants required to set up the initial stack. */
73 #define portINITIAL_XPSR ( 0x01000000 )
74
75 /* The systick is a 24-bit counter. */
76 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
77
78 /* A fiddle factor to estimate the number of SysTick counts that would have
79 * occurred while the SysTick counter is stopped during tickless idle
80 * calculations. */
81 #define portMISSED_COUNTS_FACTOR ( 94UL )
82
83 /* For strict compliance with the Cortex-M spec the task start address should
84 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
85 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
86
87 /* Let the user override the default SysTick clock rate. If defined by the
88 * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
89 * configuration register. */
90 #ifndef configSYSTICK_CLOCK_HZ
91 #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
92 /* Ensure the SysTick is clocked at the same frequency as the core. */
93 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
94 #else
95 /* Select the option to clock SysTick not at the same frequency as the core. */
96 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
97 #endif
98
99 /*
100 * Setup the timer to generate the tick interrupts. The implementation in this
101 * file is weak to allow application writers to change the timer used to
102 * generate the tick interrupt.
103 */
104 void vPortSetupTimerInterrupt( void );
105
106 /*
107 * Exception handlers.
108 */
109 void xPortSysTickHandler( void );
110
111 /*
112 * Start first task is a separate function so it can be tested in isolation.
113 */
114 extern void vPortStartFirstTask( void );
115
116 /*
117 * Used to catch tasks that attempt to return from their implementing function.
118 */
119 static void prvTaskExitError( void );
120
121 /*-----------------------------------------------------------*/
122
123 /* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY
124 * setting. */
125 const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
126
127 /* Each task maintains its own interrupt status in the critical nesting
128 * variable. */
129 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
130
131 /*
132 * The number of SysTick increments that make up one tick period.
133 */
134 #if ( configUSE_TICKLESS_IDLE == 1 )
135 static uint32_t ulTimerCountsForOneTick = 0;
136 #endif /* configUSE_TICKLESS_IDLE */
137
138 /*
139 * The maximum number of tick periods that can be suppressed is limited by the
140 * 24 bit resolution of the SysTick timer.
141 */
142 #if ( configUSE_TICKLESS_IDLE == 1 )
143 static uint32_t xMaximumPossibleSuppressedTicks = 0;
144 #endif /* configUSE_TICKLESS_IDLE */
145
146 /*
147 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
148 * power functionality only.
149 */
150 #if ( configUSE_TICKLESS_IDLE == 1 )
151 static uint32_t ulStoppedTimerCompensation = 0;
152 #endif /* configUSE_TICKLESS_IDLE */
153
154 /*
155 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
156 * FreeRTOS API functions are not called from interrupts that have been assigned
157 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
158 */
159 #if ( configASSERT_DEFINED == 1 )
160 static uint8_t ucMaxSysCallPriority = 0;
161 static uint32_t ulMaxPRIGROUPValue = 0;
162 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
163 #endif /* configASSERT_DEFINED */
164
165 /*-----------------------------------------------------------*/
166
167 /*
168 * See header file for description.
169 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)170 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
171 TaskFunction_t pxCode,
172 void * pvParameters )
173 {
174 /* Simulate the stack frame as it would be created by a context switch
175 * interrupt. */
176
177 /* Offset added to account for the way the MCU uses the stack on entry/exit
178 * of interrupts, and to ensure alignment. */
179 pxTopOfStack--;
180
181 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
182 pxTopOfStack--;
183 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
184 pxTopOfStack--;
185 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
186
187 /* Save code space by skipping register initialisation. */
188 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
189 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
190
191 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
192
193 return pxTopOfStack;
194 }
195 /*-----------------------------------------------------------*/
196
prvTaskExitError(void)197 static void prvTaskExitError( void )
198 {
199 /* A function that implements a task must not exit or attempt to return to
200 * its caller as there is nothing to return to. If a task wants to exit it
201 * should instead call vTaskDelete( NULL ).
202 *
203 * Artificially force an assert() to be triggered if configASSERT() is
204 * defined, then stop here so application writers can catch the error. */
205 configASSERT( uxCriticalNesting == ~0UL );
206 portDISABLE_INTERRUPTS();
207
208 for( ; ; )
209 {
210 }
211 }
212 /*-----------------------------------------------------------*/
213
214 /*
215 * See header file for description.
216 */
xPortStartScheduler(void)217 BaseType_t xPortStartScheduler( void )
218 {
219 #if ( configASSERT_DEFINED == 1 )
220 {
221 volatile uint8_t ucOriginalPriority;
222 volatile uint32_t ulImplementedPrioBits = 0;
223 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
224 volatile uint8_t ucMaxPriorityValue;
225
226 /* Determine the maximum priority from which ISR safe FreeRTOS API
227 * functions can be called. ISR safe functions are those that end in
228 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
229 * ensure interrupt entry is as fast and simple as possible.
230 *
231 * Save the interrupt priority value that is about to be clobbered. */
232 ucOriginalPriority = *pucFirstUserPriorityRegister;
233
234 /* Determine the number of priority bits available. First write to all
235 * possible bits. */
236 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
237
238 /* Read the value back to see how many bits stuck. */
239 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
240
241 /* Use the same mask on the maximum system call priority. */
242 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
243
244 /* Check that the maximum system call priority is nonzero after
245 * accounting for the number of priority bits supported by the
246 * hardware. A priority of 0 is invalid because setting the BASEPRI
247 * register to 0 unmasks all interrupts, and interrupts with priority 0
248 * cannot be masked using BASEPRI.
249 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
250 configASSERT( ucMaxSysCallPriority );
251
252 /* Check that the bits not implemented in hardware are zero in
253 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
254 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
255
256 /* Calculate the maximum acceptable priority group value for the number
257 * of bits read back. */
258
259 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
260 {
261 ulImplementedPrioBits++;
262 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
263 }
264
265 if( ulImplementedPrioBits == 8 )
266 {
267 /* When the hardware implements 8 priority bits, there is no way for
268 * the software to configure PRIGROUP to not have sub-priorities. As
269 * a result, the least significant bit is always used for sub-priority
270 * and there are 128 preemption priorities and 2 sub-priorities.
271 *
272 * This may cause some confusion in some cases - for example, if
273 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
274 * priority interrupts will be masked in Critical Sections as those
275 * are at the same preemption priority. This may appear confusing as
276 * 4 is higher (numerically lower) priority than
277 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
278 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
279 * to 4, this confusion does not happen and the behaviour remains the same.
280 *
281 * The following assert ensures that the sub-priority bit in the
282 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
283 * confusion. */
284 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
285 ulMaxPRIGROUPValue = 0;
286 }
287 else
288 {
289 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
290 }
291
292 /* Shift the priority group value back to its position within the AIRCR
293 * register. */
294 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
295 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
296
297 /* Restore the clobbered interrupt priority register to its original
298 * value. */
299 *pucFirstUserPriorityRegister = ucOriginalPriority;
300 }
301 #endif /* configASSERT_DEFINED */
302
303 /* Make PendSV and SysTick the lowest priority interrupts. */
304 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
305 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
306
307 /* Start the timer that generates the tick ISR. Interrupts are disabled
308 * here already. */
309 vPortSetupTimerInterrupt();
310
311 /* Initialise the critical nesting count ready for the first task. */
312 uxCriticalNesting = 0;
313
314 /* Start the first task. */
315 vPortStartFirstTask();
316
317 /* Should not get here! */
318 return 0;
319 }
320 /*-----------------------------------------------------------*/
321
vPortEndScheduler(void)322 void vPortEndScheduler( void )
323 {
324 /* Not implemented in ports where there is nothing to return to.
325 * Artificially force an assert. */
326 configASSERT( uxCriticalNesting == 1000UL );
327 }
328 /*-----------------------------------------------------------*/
329
vPortEnterCritical(void)330 void vPortEnterCritical( void )
331 {
332 portDISABLE_INTERRUPTS();
333 uxCriticalNesting++;
334
335 /* This is not the interrupt safe version of the enter critical function so
336 * assert() if it is being called from an interrupt context. Only API
337 * functions that end in "FromISR" can be used in an interrupt. Only assert if
338 * the critical nesting count is 1 to protect against recursive calls if the
339 * assert function also uses a critical section. */
340 if( uxCriticalNesting == 1 )
341 {
342 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
343 }
344 }
345 /*-----------------------------------------------------------*/
346
vPortExitCritical(void)347 void vPortExitCritical( void )
348 {
349 configASSERT( uxCriticalNesting );
350 uxCriticalNesting--;
351
352 if( uxCriticalNesting == 0 )
353 {
354 portENABLE_INTERRUPTS();
355 }
356 }
357 /*-----------------------------------------------------------*/
358
xPortSysTickHandler(void)359 void xPortSysTickHandler( void )
360 {
361 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
362 * executes all interrupts must be unmasked. There is therefore no need to
363 * save and then restore the interrupt mask value as its value is already
364 * known. */
365 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
366 {
367 /* Increment the RTOS tick. */
368 if( xTaskIncrementTick() != pdFALSE )
369 {
370 /* A context switch is required. Context switching is performed in
371 * the PendSV interrupt. Pend the PendSV interrupt. */
372 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
373 }
374 }
375 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
376 }
377 /*-----------------------------------------------------------*/
378
379 #if ( configUSE_TICKLESS_IDLE == 1 )
380
381 #pragma WEAK( vPortSuppressTicksAndSleep )
vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)382 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
383 {
384 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
385 TickType_t xModifiableIdleTime;
386
387 /* Make sure the SysTick reload value does not overflow the counter. */
388 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
389 {
390 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
391 }
392
393 /* Enter a critical section but don't use the taskENTER_CRITICAL()
394 * method as that will mask interrupts that should exit sleep mode. */
395 __asm( " cpsid i" );
396 __asm( " dsb" );
397 __asm( " isb" );
398
399 /* If a context switch is pending or a task is waiting for the scheduler
400 * to be unsuspended then abandon the low power entry. */
401 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
402 {
403 /* Re-enable interrupts - see comments above the cpsid instruction
404 * above. */
405 __asm( " cpsie i" );
406 }
407 else
408 {
409 /* Stop the SysTick momentarily. The time the SysTick is stopped for
410 * is accounted for as best it can be, but using the tickless mode will
411 * inevitably result in some tiny drift of the time maintained by the
412 * kernel with respect to calendar time. */
413 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
414
415 /* Use the SysTick current-value register to determine the number of
416 * SysTick decrements remaining until the next tick interrupt. If the
417 * current-value register is zero, then there are actually
418 * ulTimerCountsForOneTick decrements remaining, not zero, because the
419 * SysTick requests the interrupt when decrementing from 1 to 0. */
420 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
421
422 if( ulSysTickDecrementsLeft == 0 )
423 {
424 ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
425 }
426
427 /* Calculate the reload value required to wait xExpectedIdleTime
428 * tick periods. -1 is used because this code normally executes part
429 * way through the first tick period. But if the SysTick IRQ is now
430 * pending, then clear the IRQ, suppressing the first tick, and correct
431 * the reload value to reflect that the second tick period is already
432 * underway. The expected idle time is always at least two ticks. */
433 ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
434
435 if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
436 {
437 portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
438 ulReloadValue -= ulTimerCountsForOneTick;
439 }
440
441 if( ulReloadValue > ulStoppedTimerCompensation )
442 {
443 ulReloadValue -= ulStoppedTimerCompensation;
444 }
445
446 /* Set the new reload value. */
447 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
448
449 /* Clear the SysTick count flag and set the count value back to
450 * zero. */
451 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
452
453 /* Restart SysTick. */
454 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
455
456 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
457 * set its parameter to 0 to indicate that its implementation contains
458 * its own wait for interrupt or wait for event instruction, and so wfi
459 * should not be executed again. However, the original expected idle
460 * time variable must remain unmodified, so a copy is taken. */
461 xModifiableIdleTime = xExpectedIdleTime;
462 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
463
464 if( xModifiableIdleTime > 0 )
465 {
466 __asm( " dsb" );
467 __asm( " wfi" );
468 __asm( " isb" );
469 }
470
471 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
472
473 /* Re-enable interrupts to allow the interrupt that brought the MCU
474 * out of sleep mode to execute immediately. See comments above
475 * the cpsid instruction above. */
476 __asm( " cpsie i" );
477 __asm( " dsb" );
478 __asm( " isb" );
479
480 /* Disable interrupts again because the clock is about to be stopped
481 * and interrupts that execute while the clock is stopped will increase
482 * any slippage between the time maintained by the RTOS and calendar
483 * time. */
484 __asm( " cpsid i" );
485 __asm( " dsb" );
486 __asm( " isb" );
487
488 /* Disable the SysTick clock without reading the
489 * portNVIC_SYSTICK_CTRL_REG register to ensure the
490 * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
491 * the time the SysTick is stopped for is accounted for as best it can
492 * be, but using the tickless mode will inevitably result in some tiny
493 * drift of the time maintained by the kernel with respect to calendar
494 * time*/
495 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
496
497 /* Determine whether the SysTick has already counted to zero. */
498 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
499 {
500 uint32_t ulCalculatedLoadValue;
501
502 /* The tick interrupt ended the sleep (or is now pending), and
503 * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
504 * with whatever remains of the new tick period. */
505 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
506
507 /* Don't allow a tiny value, or values that have somehow
508 * underflowed because the post sleep hook did something
509 * that took too long or because the SysTick current-value register
510 * is zero. */
511 if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
512 {
513 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
514 }
515
516 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
517
518 /* As the pending tick will be processed as soon as this
519 * function exits, the tick value maintained by the tick is stepped
520 * forward by one less than the time spent waiting. */
521 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
522 }
523 else
524 {
525 /* Something other than the tick interrupt ended the sleep. */
526
527 /* Use the SysTick current-value register to determine the
528 * number of SysTick decrements remaining until the expected idle
529 * time would have ended. */
530 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
531 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
532 {
533 /* If the SysTick is not using the core clock, the current-
534 * value register might still be zero here. In that case, the
535 * SysTick didn't load from the reload register, and there are
536 * ulReloadValue decrements remaining in the expected idle
537 * time, not zero. */
538 if( ulSysTickDecrementsLeft == 0 )
539 {
540 ulSysTickDecrementsLeft = ulReloadValue;
541 }
542 }
543 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
544
545 /* Work out how long the sleep lasted rounded to complete tick
546 * periods (not the ulReload value which accounted for part
547 * ticks). */
548 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
549
550 /* How many complete tick periods passed while the processor
551 * was waiting? */
552 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
553
554 /* The reload value is set to whatever fraction of a single tick
555 * period remains. */
556 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
557 }
558
559 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
560 * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
561 * the SysTick is not using the core clock, temporarily configure it to
562 * use the core clock. This configuration forces the SysTick to load
563 * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
564 * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
565 * to receive the standard value immediately. */
566 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
567 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
568 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
569 {
570 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
571 }
572 #else
573 {
574 /* The temporary usage of the core clock has served its purpose,
575 * as described above. Resume usage of the other clock. */
576 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
577
578 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
579 {
580 /* The partial tick period already ended. Be sure the SysTick
581 * counts it only once. */
582 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
583 }
584
585 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
586 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
587 }
588 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
589
590 /* Step the tick to account for any tick periods that elapsed. */
591 vTaskStepTick( ulCompleteTickPeriods );
592
593 /* Exit with interrupts enabled. */
594 __asm( " cpsie i" );
595 }
596 }
597
598 #endif /* configUSE_TICKLESS_IDLE */
599 /*-----------------------------------------------------------*/
600
601 /*
602 * Setup the systick timer to generate the tick interrupts at the required
603 * frequency.
604 */
605 #pragma WEAK( vPortSetupTimerInterrupt )
vPortSetupTimerInterrupt(void)606 void vPortSetupTimerInterrupt( void )
607 {
608 /* Calculate the constants required to configure the tick interrupt. */
609 #if ( configUSE_TICKLESS_IDLE == 1 )
610 {
611 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
612 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
613 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
614 }
615 #endif /* configUSE_TICKLESS_IDLE */
616
617 /* Stop and clear the SysTick. */
618 portNVIC_SYSTICK_CTRL_REG = 0UL;
619 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
620
621 /* Configure SysTick to interrupt at the requested rate. */
622 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
623 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
624 }
625 /*-----------------------------------------------------------*/
626
627 #if ( configASSERT_DEFINED == 1 )
628
vPortValidateInterruptPriority(void)629 void vPortValidateInterruptPriority( void )
630 {
631 extern uint32_t ulPortGetIPSR( void );
632 uint32_t ulCurrentInterrupt;
633 uint8_t ucCurrentPriority;
634
635 ulCurrentInterrupt = ulPortGetIPSR();
636
637 /* Is the interrupt number a user defined interrupt? */
638 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
639 {
640 /* Look up the interrupt's priority. */
641 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
642
643 /* The following assertion will fail if a service routine (ISR) for
644 * an interrupt that has been assigned a priority above
645 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
646 * function. ISR safe FreeRTOS API functions must *only* be called
647 * from interrupts that have been assigned a priority at or below
648 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
649 *
650 * Numerically low interrupt priority numbers represent logically high
651 * interrupt priorities, therefore the priority of the interrupt must
652 * be set to a value equal to or numerically *higher* than
653 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
654 *
655 * Interrupts that use the FreeRTOS API must not be left at their
656 * default priority of zero as that is the highest possible priority,
657 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
658 * and therefore also guaranteed to be invalid.
659 *
660 * FreeRTOS maintains separate thread and ISR API functions to ensure
661 * interrupt entry is as fast and simple as possible.
662 *
663 * The following links provide detailed information:
664 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
665 * https://www.FreeRTOS.org/FAQHelp.html */
666 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
667 }
668
669 /* Priority grouping: The interrupt controller (NVIC) allows the bits
670 * that define each interrupt's priority to be split between bits that
671 * define the interrupt's pre-emption priority bits and bits that define
672 * the interrupt's sub-priority. For simplicity all bits must be defined
673 * to be pre-emption priority bits. The following assertion will fail if
674 * this is not the case (if some bits represent a sub-priority).
675 *
676 * If the application only uses CMSIS libraries for interrupt
677 * configuration then the correct setting can be achieved on all Cortex-M
678 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
679 * scheduler. Note however that some vendor specific peripheral libraries
680 * assume a non-zero priority group setting, in which cases using a value
681 * of zero will result in unpredictable behaviour. */
682 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
683 }
684
685 #endif /* configASSERT_DEFINED */
686
