1 /** 2 ****************************************************************************** 3 * @file stm32fxx_hal_eth.c 4 * @author MCD Application Team 5 * @version V1.3.2 6 * @date 26-June-2015 7 * @brief ETH HAL module driver. 8 * This file provides firmware functions to manage the following 9 * functionalities of the Ethernet (ETH) peripheral: 10 * + Initialization and de-initialization functions 11 * + IO operation functions 12 * + Peripheral Control functions 13 * + Peripheral State and Errors functions 14 * 15 * @verbatim 16 * ============================================================================== 17 ##### How to use this driver ##### 18 #####============================================================================== 19 #####[..] 20 #####(#)Declare a ETH_HandleTypeDef handle structure, for example: 21 ##### ETH_HandleTypeDef heth; 22 ##### 23 #####(#)Fill parameters of Init structure in heth handle 24 ##### 25 #####(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) 26 ##### 27 #####(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: 28 ##### (##) Enable the Ethernet interface clock using 29 ##### (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); 30 ##### (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); 31 ##### (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); 32 ##### 33 ##### (##) Initialize the related GPIO clocks 34 ##### (##) Configure Ethernet pin-out 35 ##### (##) Configure Ethernet NVIC interrupt (IT mode) 36 ##### 37 #####(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: 38 ##### (##) HAL_ETH_DMATxDescListInit(); for Transmission process 39 ##### (##) HAL_ETH_DMARxDescListInit(); for Reception process 40 ##### 41 #####(#)Enable MAC and DMA transmission and reception: 42 ##### (##) HAL_ETH_Start(); 43 ##### 44 #####(#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer 45 ##### the frame to MAC TX FIFO: 46 ##### (##) HAL_ETH_TransmitFrame(); 47 ##### 48 #####(#)Poll for a received frame in ETH RX DMA Descriptors and get received 49 ##### frame parameters 50 ##### (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) 51 ##### 52 #####(#) Get a received frame when an ETH RX interrupt occurs: 53 ##### (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) 54 ##### 55 #####(#) Communicate with external PHY device: 56 ##### (##) Read a specific register from the PHY 57 ##### HAL_ETH_ReadPHYRegister(); 58 ##### (##) Write data to a specific RHY register: 59 ##### HAL_ETH_WritePHYRegister(); 60 ##### 61 #####(#) Configure the Ethernet MAC after ETH peripheral initialization 62 ##### HAL_ETH_ConfigMAC(); all MAC parameters should be filled. 63 ##### 64 #####(#) Configure the Ethernet DMA after ETH peripheral initialization 65 ##### HAL_ETH_ConfigDMA(); all DMA parameters should be filled. 66 ##### 67 #####-@- The PTP protocol and the DMA descriptors ring mode are not supported 68 ##### in this driver 69 ##### 70 #####@endverbatim 71 ****************************************************************************** 72 * @attention 73 * 74 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 75 * 76 * Redistribution and use in source and binary forms, with or without modification, 77 * are permitted provided that the following conditions are met: 78 * 1. Redistributions of source code must retain the above copyright notice, 79 * this list of conditions and the following disclaimer. 80 * 2. Redistributions in binary form must reproduce the above copyright notice, 81 * this list of conditions and the following disclaimer in the documentation 82 * and/or other materials provided with the distribution. 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors 84 * may be used to endorse or promote products derived from this software 85 * without specific prior written permission. 86 * 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 97 * 98 ****************************************************************************** 99 */ 100 101 /* Includes ------------------------------------------------------------------*/ 102 #include "stm32fxx_hal_eth.h" 103 104 #if defined( STM32F7xx ) 105 #include "stm32f7xx_hal.h" 106 #define stm_is_F7 1 107 #elif defined( STM32F4xx ) 108 #include "stm32f4xx_hal.h" 109 #define stm_is_F4 1 110 #elif defined( STM32F2xx ) 111 #include "stm32f2xx_hal.h" 112 #define stm_is_F2 1 113 #elif defined( STM32F1xx ) 114 #include "stm32f1xx_hal.h" 115 #define stm_is_F1 1 116 #else /* if defined( STM32F7xx ) */ 117 #error For what part should this be compiled? 118 #endif /* if defined( STM32F7xx ) */ 119 120 /** @addtogroup STM32F4xx_HAL_Driver 121 * @{ 122 */ 123 124 /** @defgroup ETH ETH 125 * @brief ETH HAL module driver 126 * @{ 127 */ 128 129 #if !defined( ARRAY_SIZE ) 130 #define ARRAY_SIZE( x ) ( sizeof( x ) / sizeof( x )[ 0 ] ) 131 #endif 132 133 #ifdef HAL_ETH_MODULE_ENABLED 134 135 #if ( stm_is_F1 != 0 || stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 ) 136 137 /* Private typedef -----------------------------------------------------------*/ 138 /* Private define ------------------------------------------------------------*/ 139 140 /** @defgroup ETH_Private_Constants ETH Private Constants 141 * @{ 142 */ 143 /* Some macros have been renamed through time. */ 144 #ifndef ETH_MACMIIAR_CR_Div16 145 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_DIV16 146 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_DIV26 147 #define ETH_MACMIIAR_CR_Div42 ETH_MACMIIAR_CR_DIV42 148 #endif 149 150 /** 151 * @} 152 */ 153 /* Private macro -------------------------------------------------------------*/ 154 /* Private variables ---------------------------------------------------------*/ 155 /* Private function prototypes -----------------------------------------------*/ 156 157 /** @defgroup ETH_Private_Functions ETH Private Functions 158 * @{ 159 */ 160 static void ETH_MACDMAConfig( ETH_HandleTypeDef * heth, 161 uint32_t err ); 162 static void ETH_MACAddressConfig( ETH_HandleTypeDef * heth, 163 uint32_t MacAddr, 164 uint8_t * Addr ); 165 static void ETH_MACReceptionEnable( ETH_HandleTypeDef * heth ); 166 static void ETH_MACReceptionDisable( ETH_HandleTypeDef * heth ); 167 static void ETH_MACTransmissionEnable( ETH_HandleTypeDef * heth ); 168 static void ETH_MACTransmissionDisable( ETH_HandleTypeDef * heth ); 169 static void ETH_DMATransmissionEnable( ETH_HandleTypeDef * heth ); 170 static void ETH_DMATransmissionDisable( ETH_HandleTypeDef * heth ); 171 static void ETH_DMAReceptionEnable( ETH_HandleTypeDef * heth ); 172 static void ETH_DMAReceptionDisable( ETH_HandleTypeDef * heth ); 173 static void ETH_FlushTransmitFIFO( ETH_HandleTypeDef * heth ); 174 175 /** 176 * @} 177 */ 178 /* Private functions ---------------------------------------------------------*/ 179 180 /** @defgroup ETH_Exported_Functions ETH Exported Functions 181 * @{ 182 */ 183 184 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions 185 * @brief Initialization and Configuration functions 186 * 187 * @verbatim 188 * =============================================================================== 189 ##### Initialization and de-initialization functions ##### 190 #####=============================================================================== 191 #####[..] This section provides functions allowing to: 192 #####(+) Initialize and configure the Ethernet peripheral 193 #####(+) De-initialize the Ethernet peripheral 194 ##### 195 #####@endverbatim 196 * @{ 197 */ 198 extern void vMACBProbePhy( void ); 199 200 /** 201 * @brief Initializes the Ethernet MAC and DMA according to default 202 * parameters. 203 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 204 * the configuration information for ETHERNET module 205 * @retval HAL status 206 */ HAL_ETH_Init(ETH_HandleTypeDef * heth)207 HAL_StatusTypeDef HAL_ETH_Init( ETH_HandleTypeDef * heth ) 208 { 209 uint32_t tmpreg = 0uL; 210 uint32_t hclk = 60000000uL; 211 uint32_t err = ETH_SUCCESS; 212 213 /* Check the ETH peripheral state */ 214 if( heth == NULL ) 215 { 216 return HAL_ERROR; 217 } 218 219 /* Check parameters */ 220 assert_param( IS_ETH_AUTONEGOTIATION( heth->Init.AutoNegotiation ) ); 221 assert_param( IS_ETH_RX_MODE( heth->Init.RxMode ) ); 222 assert_param( IS_ETH_CHECKSUM_MODE( heth->Init.ChecksumMode ) ); 223 assert_param( IS_ETH_MEDIA_INTERFACE( heth->Init.MediaInterface ) ); 224 225 if( heth->State == HAL_ETH_STATE_RESET ) 226 { 227 /* Init the low level hardware : GPIO, CLOCK, NVIC. */ 228 HAL_ETH_MspInit( heth ); 229 } 230 231 /* Enable SYSCFG Clock */ 232 __HAL_RCC_SYSCFG_CLK_ENABLE(); 233 234 /* Select MII or RMII Mode*/ 235 SYSCFG->PMC &= ~( SYSCFG_PMC_MII_RMII_SEL ); 236 SYSCFG->PMC |= ( uint32_t ) heth->Init.MediaInterface; 237 238 /* Ethernet Software reset */ 239 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ 240 /* After reset all the registers holds their respective reset values */ 241 /* Also enable EDFE: Enhanced descriptor format enable. */ 242 heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE; 243 244 /* Wait for software reset */ 245 while( ( heth->Instance->DMABMR & ETH_DMABMR_SR ) != ( uint32_t ) RESET ) 246 { 247 /* If your program hangs here, please check the value of 'ipconfigUSE_RMII'. */ 248 } 249 250 /*-------------------------------- MAC Initialization ----------------------*/ 251 /* Get the ETHERNET MACMIIAR value */ 252 tmpreg = heth->Instance->MACMIIAR; 253 /* Clear CSR Clock Range CR[2:0] bits */ 254 tmpreg &= ETH_MACMIIAR_CR_MASK; 255 256 /* Get hclk frequency value (e.g. 168,000,000) */ 257 hclk = HAL_RCC_GetHCLKFreq(); 258 #if !defined( STM32F2xx ) 259 /* Set CR bits depending on hclk value */ 260 if( ( hclk >= 20000000uL ) && ( hclk < 35000000uL ) ) 261 { 262 /* CSR Clock Range between 20-35 MHz */ 263 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div16; 264 } 265 else if( ( hclk >= 35000000uL ) && ( hclk < 60000000uL ) ) 266 { 267 /* CSR Clock Range between 35-60 MHz */ 268 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26; 269 } 270 else 271 { 272 #if ( stm_is_F1 != 0 ) 273 { 274 /* The STM32F1xx has a frequency up to 72 MHz. */ 275 /* CSR Clock Range between 60-72 MHz */ 276 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div42; 277 } 278 #else 279 { 280 if( ( hclk >= 60000000uL ) && ( hclk < 100000000uL ) ) 281 { 282 /* CSR Clock Range between 60-100 MHz */ 283 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div42; 284 } 285 else if( ( hclk >= 100000000uL ) && ( hclk < 150000000uL ) ) 286 { 287 /* CSR Clock Range between 100-150 MHz */ 288 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div62; 289 } 290 else /* ( ( hclk >= 150000000uL ) && ( hclk <= 183000000uL ) ) */ 291 { 292 /* CSR Clock Range between 150-183 MHz */ 293 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div102; 294 } 295 } 296 #endif /* if ( stm_is_F1 != 0 ) */ 297 } 298 #else /* if !defined( STM32F2xx ) */ 299 /* Clock settings for STM32F2 only. */ 300 /* Set CR bits depending on hclk value */ 301 if( ( hclk >= 20000000U ) && ( hclk < 35000000U ) ) 302 { 303 /* CSR Clock Range between 20-35 MHz */ 304 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div16; 305 } 306 else if( ( hclk >= 35000000U ) && ( hclk < 60000000U ) ) 307 { 308 /* CSR Clock Range between 35-60 MHz */ 309 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26; 310 } 311 else if( ( hclk >= 60000000U ) && ( hclk < 100000000U ) ) 312 { 313 /* CSR Clock Range between 60-100 MHz */ 314 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div42; 315 } 316 else /* ((hclk >= 100000000)&&(hclk < 120000000)) */ 317 { 318 /* CSR Clock Range between 100-120 MHz */ 319 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div62; 320 } 321 #endif /* defined(STM32F2xx) */ 322 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ 323 heth->Instance->MACMIIAR = ( uint32_t ) tmpreg; 324 325 /* Initialise the MACB and set all PHY properties */ 326 vMACBProbePhy(); 327 328 /* Config MAC and DMA */ 329 ETH_MACDMAConfig( heth, err ); 330 331 /* Set ETH HAL State to Ready */ 332 heth->State = HAL_ETH_STATE_READY; 333 334 /* 335 * Disable the interrupts that are related to the MMC counters. 336 * These interrupts are enabled by default. The interrupt can 337 * only be acknowledged by reading the corresponding counter. 338 */ 339 340 heth->Instance->MACIMR = ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM; 341 heth->Instance->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM; 342 heth->Instance->MMCTIMR = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | ETH_MMCTIMR_TGFSCM; 343 344 /* Return function status */ 345 return HAL_OK; 346 } 347 348 /** 349 * @brief De-Initializes the ETH peripheral. 350 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 351 * the configuration information for ETHERNET module 352 * @retval HAL status 353 */ HAL_ETH_DeInit(ETH_HandleTypeDef * heth)354 HAL_StatusTypeDef HAL_ETH_DeInit( ETH_HandleTypeDef * heth ) 355 { 356 /* Set the ETH peripheral state to BUSY */ 357 heth->State = HAL_ETH_STATE_BUSY; 358 359 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ 360 HAL_ETH_MspDeInit( heth ); 361 362 /* Set ETH HAL state to Disabled */ 363 heth->State = HAL_ETH_STATE_RESET; 364 365 /* Release Lock */ 366 __HAL_UNLOCK( heth ); 367 368 /* Return function status */ 369 return HAL_OK; 370 } 371 372 /** 373 * @brief Initializes the ETH MSP. 374 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 375 * the configuration information for ETHERNET module 376 * @retval None 377 */ HAL_ETH_MspInit(ETH_HandleTypeDef * heth)378 __weak void HAL_ETH_MspInit( ETH_HandleTypeDef * heth ) 379 { 380 /* NOTE : This function Should not be modified, when the callback is needed, 381 * the HAL_ETH_MspInit could be implemented in the user file 382 */ 383 ( void ) heth; 384 } 385 386 /** 387 * @brief DeInitializes ETH MSP. 388 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 389 * the configuration information for ETHERNET module 390 * @retval None 391 */ HAL_ETH_MspDeInit(ETH_HandleTypeDef * heth)392 __weak void HAL_ETH_MspDeInit( ETH_HandleTypeDef * heth ) 393 { 394 /* NOTE : This function Should not be modified, when the callback is needed, 395 * the HAL_ETH_MspDeInit could be implemented in the user file 396 */ 397 ( void ) heth; 398 } 399 400 /** 401 * @} 402 */ 403 404 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions 405 * @brief Data transfers functions 406 * 407 * @verbatim 408 * ============================================================================== 409 ##### IO operation functions ##### 410 #####============================================================================== 411 #####[..] This section provides functions allowing to: 412 ##### (+) Transmit a frame 413 ##### HAL_ETH_TransmitFrame(); 414 ##### (+) Receive a frame 415 ##### HAL_ETH_GetReceivedFrame(); 416 ##### HAL_ETH_GetReceivedFrame_IT(); 417 ##### (+) Read from an External PHY register 418 ##### HAL_ETH_ReadPHYRegister(); 419 ##### (+) Write to an External PHY register 420 ##### HAL_ETH_WritePHYRegister(); 421 ##### 422 #####@endverbatim 423 ##### 424 * @{ 425 */ 426 427 #define ETH_DMA_ALL_INTS \ 428 ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \ 429 ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \ 430 ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T ) 431 432 #define INT_MASK ( ( uint32_t ) ~( ETH_DMA_IT_TBU ) ) HAL_ETH_IRQHandler(ETH_HandleTypeDef * heth)433 void HAL_ETH_IRQHandler( ETH_HandleTypeDef * heth ) 434 { 435 uint32_t dmasr; 436 437 dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS; 438 heth->Instance->DMASR = dmasr; 439 440 /* Frame received */ 441 if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 ) 442 { 443 /* Receive complete callback */ 444 HAL_ETH_RxCpltCallback( heth ); 445 } 446 447 /* Frame transmitted */ 448 if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 ) 449 { 450 /* Transfer complete callback */ 451 HAL_ETH_TxCpltCallback( heth ); 452 } 453 454 /* ETH DMA Error */ 455 if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 ) 456 { 457 /* Ethernet Error callback */ 458 HAL_ETH_ErrorCallback( heth ); 459 } 460 } 461 462 /** 463 * @brief Tx Transfer completed callbacks. 464 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 465 * the configuration information for ETHERNET module 466 * @retval None 467 */ HAL_ETH_TxCpltCallback(ETH_HandleTypeDef * heth)468 __weak void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth ) 469 { 470 /* NOTE : This function Should not be modified, when the callback is needed, 471 * the HAL_ETH_TxCpltCallback could be implemented in the user file 472 */ 473 ( void ) heth; 474 } 475 476 /** 477 * @brief Rx Transfer completed callbacks. 478 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 479 * the configuration information for ETHERNET module 480 * @retval None 481 */ HAL_ETH_RxCpltCallback(ETH_HandleTypeDef * heth)482 __weak void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth ) 483 { 484 /* NOTE : This function Should not be modified, when the callback is needed, 485 * the HAL_ETH_TxCpltCallback could be implemented in the user file 486 */ 487 ( void ) heth; 488 } 489 490 /** 491 * @brief Ethernet transfer error callbacks 492 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 493 * the configuration information for ETHERNET module 494 * @retval None 495 */ HAL_ETH_ErrorCallback(ETH_HandleTypeDef * heth)496 __weak void HAL_ETH_ErrorCallback( ETH_HandleTypeDef * heth ) 497 { 498 /* NOTE : This function Should not be modified, when the callback is needed, 499 * the HAL_ETH_TxCpltCallback could be implemented in the user file 500 */ 501 ( void ) heth; 502 } 503 504 /** 505 * @brief Reads a PHY register 506 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 507 * the configuration information for ETHERNET module 508 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 509 * This parameter can be one of the following values: 510 * PHY_BCR: Transceiver Basic Control Register, 511 * PHY_BSR: Transceiver Basic Status Register. 512 * More PHY register could be read depending on the used PHY 513 * @param RegValue: PHY register value 514 * @retval HAL status 515 */ HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef * heth,uint16_t PHYReg,uint32_t * RegValue)516 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister( ETH_HandleTypeDef * heth, 517 uint16_t PHYReg, 518 uint32_t * RegValue ) 519 { 520 uint32_t tmpreg = 0uL; 521 uint32_t tickstart = 0uL; 522 HAL_StatusTypeDef xResult; 523 524 /* Check parameters */ 525 assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) ); 526 527 /* Check the ETH peripheral state */ 528 if( heth->State == HAL_ETH_STATE_BUSY_RD ) 529 { 530 xResult = HAL_BUSY; 531 } 532 else 533 { 534 __HAL_LOCK( heth ); 535 536 /* Set ETH HAL State to BUSY_RD */ 537 heth->State = HAL_ETH_STATE_BUSY_RD; 538 539 /* Get the ETHERNET MACMIIAR value */ 540 tmpreg = heth->Instance->MACMIIAR; 541 542 /* Keep only the CSR Clock Range CR[2:0] bits value */ 543 tmpreg &= ~ETH_MACMIIAR_CR_MASK; 544 545 /* Prepare the MII address register value */ 546 tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */ 547 tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */ 548 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ 549 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ 550 551 /* Write the result value into the MII Address register */ 552 heth->Instance->MACMIIAR = tmpreg; 553 554 /* Get tick */ 555 tickstart = HAL_GetTick(); 556 557 /* Check for the Busy flag */ 558 while( 1 ) 559 { 560 tmpreg = heth->Instance->MACMIIAR; 561 562 if( ( tmpreg & ETH_MACMIIAR_MB ) == 0uL ) 563 { 564 /* Get MACMIIDR value */ 565 *RegValue = ( uint32_t ) heth->Instance->MACMIIDR; 566 xResult = HAL_OK; 567 break; 568 } 569 570 /* Check for the Timeout */ 571 if( ( HAL_GetTick() - tickstart ) > PHY_READ_TO ) 572 { 573 xResult = HAL_TIMEOUT; 574 break; 575 } 576 } 577 578 /* Set ETH HAL State to READY */ 579 heth->State = HAL_ETH_STATE_READY; 580 581 /* Process Unlocked */ 582 __HAL_UNLOCK( heth ); 583 } 584 585 /* Return function status */ 586 return xResult; 587 } 588 589 /** 590 * @brief Writes to a PHY register. 591 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 592 * the configuration information for ETHERNET module 593 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 594 * This parameter can be one of the following values: 595 * PHY_BCR: Transceiver Control Register. 596 * More PHY register could be written depending on the used PHY 597 * @param RegValue: the value to write 598 * @retval HAL status 599 */ HAL_ETH_WritePHYRegister(ETH_HandleTypeDef * heth,uint16_t PHYReg,uint32_t RegValue)600 HAL_StatusTypeDef HAL_ETH_WritePHYRegister( ETH_HandleTypeDef * heth, 601 uint16_t PHYReg, 602 uint32_t RegValue ) 603 { 604 uint32_t tmpreg = 0; 605 uint32_t tickstart = 0; 606 HAL_StatusTypeDef xResult; 607 608 /* Check parameters */ 609 assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) ); 610 611 /* Check the ETH peripheral state */ 612 if( heth->State == HAL_ETH_STATE_BUSY_WR ) 613 { 614 xResult = HAL_BUSY; 615 } 616 else 617 { 618 __HAL_LOCK( heth ); 619 620 /* Set ETH HAL State to BUSY_WR */ 621 heth->State = HAL_ETH_STATE_BUSY_WR; 622 623 /* Get the ETHERNET MACMIIAR value */ 624 tmpreg = heth->Instance->MACMIIAR; 625 626 /* Keep only the CSR Clock Range CR[2:0] bits value */ 627 tmpreg &= ~ETH_MACMIIAR_CR_MASK; 628 629 /* Prepare the MII register address value */ 630 tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */ 631 tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */ 632 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ 633 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ 634 635 /* Give the value to the MII data register */ 636 heth->Instance->MACMIIDR = ( uint16_t ) RegValue; 637 638 /* Write the result value into the MII Address register */ 639 heth->Instance->MACMIIAR = tmpreg; 640 641 /* Get tick */ 642 tickstart = HAL_GetTick(); 643 644 /* Check for the Busy flag */ 645 while( 1 ) 646 { 647 tmpreg = heth->Instance->MACMIIAR; 648 649 if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul ) 650 { 651 xResult = HAL_OK; 652 break; 653 } 654 655 /* Check for the Timeout */ 656 if( ( HAL_GetTick() - tickstart ) > PHY_WRITE_TO ) 657 { 658 xResult = HAL_TIMEOUT; 659 break; 660 } 661 } 662 663 /* Set ETH HAL State to READY */ 664 heth->State = HAL_ETH_STATE_READY; 665 /* Process Unlocked */ 666 __HAL_UNLOCK( heth ); 667 } 668 669 /* Return function status */ 670 return xResult; 671 } 672 673 /** 674 * @} 675 */ 676 677 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions 678 * @brief Peripheral Control functions 679 * 680 * @verbatim 681 * =============================================================================== 682 ##### Peripheral Control functions ##### 683 #####=============================================================================== 684 #####[..] This section provides functions allowing to: 685 #####(+) Enable MAC and DMA transmission and reception. 686 ##### HAL_ETH_Start(); 687 #####(+) Disable MAC and DMA transmission and reception. 688 ##### HAL_ETH_Stop(); 689 #####(+) Set the MAC configuration in runtime mode 690 ##### HAL_ETH_ConfigMAC(); 691 #####(+) Set the DMA configuration in runtime mode 692 ##### HAL_ETH_ConfigDMA(); 693 ##### 694 #####@endverbatim 695 * @{ 696 */ 697 698 /** 699 * @brief Enables Ethernet MAC and DMA reception/transmission 700 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 701 * the configuration information for ETHERNET module 702 * @retval HAL status 703 */ HAL_ETH_Start(ETH_HandleTypeDef * heth)704 HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef * heth ) 705 { 706 /* Process Locked */ 707 __HAL_LOCK( heth ); 708 709 /* Set the ETH peripheral state to BUSY */ 710 heth->State = HAL_ETH_STATE_BUSY; 711 712 /* Enable transmit state machine of the MAC for transmission on the MII */ 713 ETH_MACTransmissionEnable( heth ); 714 715 /* Enable receive state machine of the MAC for reception from the MII */ 716 ETH_MACReceptionEnable( heth ); 717 718 /* Flush Transmit FIFO */ 719 ETH_FlushTransmitFIFO( heth ); 720 721 /* Start DMA transmission */ 722 ETH_DMATransmissionEnable( heth ); 723 724 /* Start DMA reception */ 725 ETH_DMAReceptionEnable( heth ); 726 727 /* Set the ETH state to READY*/ 728 heth->State = HAL_ETH_STATE_READY; 729 730 /* Process Unlocked */ 731 __HAL_UNLOCK( heth ); 732 733 /* Return function status */ 734 return HAL_OK; 735 } 736 737 /** 738 * @brief Stop Ethernet MAC and DMA reception/transmission 739 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 740 * the configuration information for ETHERNET module 741 * @retval HAL status 742 */ HAL_ETH_Stop(ETH_HandleTypeDef * heth)743 HAL_StatusTypeDef HAL_ETH_Stop( ETH_HandleTypeDef * heth ) 744 { 745 /* Process Locked */ 746 __HAL_LOCK( heth ); 747 748 /* Set the ETH peripheral state to BUSY */ 749 heth->State = HAL_ETH_STATE_BUSY; 750 751 /* Stop DMA transmission */ 752 ETH_DMATransmissionDisable( heth ); 753 754 /* Stop DMA reception */ 755 ETH_DMAReceptionDisable( heth ); 756 757 /* Disable receive state machine of the MAC for reception from the MII */ 758 ETH_MACReceptionDisable( heth ); 759 760 /* Flush Transmit FIFO */ 761 ETH_FlushTransmitFIFO( heth ); 762 763 /* Disable transmit state machine of the MAC for transmission on the MII */ 764 ETH_MACTransmissionDisable( heth ); 765 766 /* Set the ETH state*/ 767 heth->State = HAL_ETH_STATE_READY; 768 769 /* Process Unlocked */ 770 __HAL_UNLOCK( heth ); 771 772 /* Return function status */ 773 return HAL_OK; 774 } 775 vRegisterDelay()776 static void vRegisterDelay() 777 { 778 uint32_t uxCount; 779 780 /* 781 * Regarding the HAL delay functions, I noticed that HAL delay is being used to workaround the 782 * "Successive write operations to the same register might not be fully taken into account" errata. 783 * The workaround requires a delay of four TX_CLK/RX_CLK clock cycles. For a 10 Mbit connection, 784 * these clocks are running at 2.5 MHz, so this delay would be at most 1.6 microseconds. 785 * 180 Mhz = 288 loops 786 * 168 Mhz = 269 loops 787 * 100 Mhz = 160 loops 788 * 84 Mhz = 134 loops 789 */ 790 #define WAIT_TIME_NS 1600uL /* 1.6 microseconds */ 791 #define CPU_MAX_FREQ SystemCoreClock /* 84, 100, 168 or 180 MHz */ 792 uint32_t NOP_COUNT = ( WAIT_TIME_NS * ( CPU_MAX_FREQ / 1000uL ) ) / 1000000uL; 793 794 for( uxCount = NOP_COUNT; uxCount > 0uL; uxCount-- ) 795 { 796 __NOP(); 797 } 798 } 799 prvWriteMACFCR(ETH_HandleTypeDef * heth,uint32_t ulValue)800 static void prvWriteMACFCR( ETH_HandleTypeDef * heth, 801 uint32_t ulValue ) 802 { 803 /* Enable the MAC transmission */ 804 heth->Instance->MACFCR = ulValue; 805 806 /* Wait until the write operation will be taken into account: 807 * at least four TX_CLK/RX_CLK clock cycles. 808 * Read it back, wait a ms and */ 809 ( void ) heth->Instance->MACFCR; 810 811 vRegisterDelay(); 812 813 heth->Instance->MACFCR = ulValue; 814 } 815 prvWriteDMAOMR(ETH_HandleTypeDef * heth,uint32_t ulValue)816 static void prvWriteDMAOMR( ETH_HandleTypeDef * heth, 817 uint32_t ulValue ) 818 { 819 /* Enable the MAC transmission */ 820 heth->Instance->DMAOMR = ulValue; 821 822 /* Wait until the write operation will be taken into account: 823 * at least four TX_CLK/RX_CLK clock cycles. 824 * Read it back, wait a ms and */ 825 ( void ) heth->Instance->DMAOMR; 826 827 vRegisterDelay(); 828 829 heth->Instance->DMAOMR = ulValue; 830 } 831 prvWriteMACCR(ETH_HandleTypeDef * heth,uint32_t ulValue)832 static void prvWriteMACCR( ETH_HandleTypeDef * heth, 833 uint32_t ulValue ) 834 { 835 /* Enable the MAC transmission */ 836 heth->Instance->MACCR = ulValue; 837 838 /* Wait until the write operation will be taken into account: 839 * at least four TX_CLK/RX_CLK clock cycles. 840 * Read it back, wait a ms and */ 841 ( void ) heth->Instance->MACCR; 842 843 vRegisterDelay(); 844 845 heth->Instance->MACCR = ulValue; 846 } 847 848 /** 849 * @brief Set ETH MAC Configuration. 850 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 851 * the configuration information for ETHERNET module 852 * @param macconf: MAC Configuration structure 853 * @retval HAL status 854 */ HAL_ETH_ConfigMAC(ETH_HandleTypeDef * heth,ETH_MACInitTypeDef * macconf)855 HAL_StatusTypeDef HAL_ETH_ConfigMAC( ETH_HandleTypeDef * heth, 856 ETH_MACInitTypeDef * macconf ) 857 { 858 uint32_t tmpreg = 0uL; 859 860 /* Process Locked */ 861 __HAL_LOCK( heth ); 862 863 /* Set the ETH peripheral state to BUSY */ 864 heth->State = HAL_ETH_STATE_BUSY; 865 866 assert_param( IS_ETH_SPEED( heth->Init.Speed ) ); 867 assert_param( IS_ETH_DUPLEX_MODE( heth->Init.DuplexMode ) ); 868 869 if( macconf != NULL ) 870 { 871 /* Check the parameters */ 872 assert_param( IS_ETH_WATCHDOG( macconf->Watchdog ) ); 873 assert_param( IS_ETH_JABBER( macconf->Jabber ) ); 874 assert_param( IS_ETH_INTER_FRAME_GAP( macconf->InterFrameGap ) ); 875 assert_param( IS_ETH_CARRIER_SENSE( macconf->CarrierSense ) ); 876 assert_param( IS_ETH_RECEIVE_OWN( macconf->ReceiveOwn ) ); 877 assert_param( IS_ETH_LOOPBACK_MODE( macconf->LoopbackMode ) ); 878 assert_param( IS_ETH_CHECKSUM_OFFLOAD( macconf->ChecksumOffload ) ); 879 assert_param( IS_ETH_RETRY_TRANSMISSION( macconf->RetryTransmission ) ); 880 assert_param( IS_ETH_AUTOMATIC_PADCRC_STRIP( macconf->AutomaticPadCRCStrip ) ); 881 assert_param( IS_ETH_BACKOFF_LIMIT( macconf->BackOffLimit ) ); 882 assert_param( IS_ETH_DEFERRAL_CHECK( macconf->DeferralCheck ) ); 883 assert_param( IS_ETH_RECEIVE_ALL( macconf->ReceiveAll ) ); 884 assert_param( IS_ETH_SOURCE_ADDR_FILTER( macconf->SourceAddrFilter ) ); 885 assert_param( IS_ETH_CONTROL_FRAMES( macconf->PassControlFrames ) ); 886 assert_param( IS_ETH_BROADCAST_FRAMES_RECEPTION( macconf->BroadcastFramesReception ) ); 887 assert_param( IS_ETH_DESTINATION_ADDR_FILTER( macconf->DestinationAddrFilter ) ); 888 assert_param( IS_ETH_PROMISCUOUS_MODE( macconf->PromiscuousMode ) ); 889 assert_param( IS_ETH_MULTICAST_FRAMES_FILTER( macconf->MulticastFramesFilter ) ); 890 assert_param( IS_ETH_UNICAST_FRAMES_FILTER( macconf->UnicastFramesFilter ) ); 891 assert_param( IS_ETH_PAUSE_TIME( macconf->PauseTime ) ); 892 assert_param( IS_ETH_ZEROQUANTA_PAUSE( macconf->ZeroQuantaPause ) ); 893 assert_param( IS_ETH_PAUSE_LOW_THRESHOLD( macconf->PauseLowThreshold ) ); 894 assert_param( IS_ETH_UNICAST_PAUSE_FRAME_DETECT( macconf->UnicastPauseFrameDetect ) ); 895 assert_param( IS_ETH_RECEIVE_FLOWCONTROL( macconf->ReceiveFlowControl ) ); 896 assert_param( IS_ETH_TRANSMIT_FLOWCONTROL( macconf->TransmitFlowControl ) ); 897 assert_param( IS_ETH_VLAN_TAG_COMPARISON( macconf->VLANTagComparison ) ); 898 assert_param( IS_ETH_VLAN_TAG_IDENTIFIER( macconf->VLANTagIdentifier ) ); 899 900 /*------------------------ ETHERNET MACCR Configuration --------------------*/ 901 /* Get the ETHERNET MACCR value */ 902 tmpreg = heth->Instance->MACCR; 903 /* Clear WD, PCE, PS, TE and RE bits */ 904 tmpreg &= ETH_MACCR_CLEAR_MASK; 905 906 tmpreg |= ( uint32_t ) ( 907 macconf->Watchdog | 908 macconf->Jabber | 909 macconf->InterFrameGap | 910 macconf->CarrierSense | 911 heth->Init.Speed | 912 macconf->ReceiveOwn | 913 macconf->LoopbackMode | 914 heth->Init.DuplexMode | 915 macconf->ChecksumOffload | 916 macconf->RetryTransmission | 917 macconf->AutomaticPadCRCStrip | 918 macconf->BackOffLimit | 919 macconf->DeferralCheck ); 920 921 /* Write to ETHERNET MACCR */ 922 prvWriteMACCR( heth, tmpreg ); 923 924 /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 925 /* Write to ETHERNET MACFFR */ 926 heth->Instance->MACFFR = ( uint32_t ) ( 927 macconf->ReceiveAll | 928 macconf->SourceAddrFilter | 929 macconf->PassControlFrames | 930 macconf->BroadcastFramesReception | 931 macconf->DestinationAddrFilter | 932 macconf->PromiscuousMode | 933 macconf->MulticastFramesFilter | 934 macconf->UnicastFramesFilter ); 935 936 /* Wait until the write operation will be taken into account : 937 * at least four TX_CLK/RX_CLK clock cycles */ 938 tmpreg = heth->Instance->MACFFR; 939 vRegisterDelay(); 940 heth->Instance->MACFFR = tmpreg; 941 942 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ 943 /* Write to ETHERNET MACHTHR */ 944 heth->Instance->MACHTHR = ( uint32_t ) macconf->HashTableHigh; 945 946 /* Write to ETHERNET MACHTLR */ 947 heth->Instance->MACHTLR = ( uint32_t ) macconf->HashTableLow; 948 /*----------------------- ETHERNET MACFCR Configuration --------------------*/ 949 950 /* Get the ETHERNET MACFCR value */ 951 tmpreg = heth->Instance->MACFCR; 952 /* Clear xx bits */ 953 tmpreg &= ETH_MACFCR_CLEAR_MASK; 954 955 tmpreg |= ( uint32_t ) ( ( 956 macconf->PauseTime << 16 ) | 957 macconf->ZeroQuantaPause | 958 macconf->PauseLowThreshold | 959 macconf->UnicastPauseFrameDetect | 960 macconf->ReceiveFlowControl | 961 macconf->TransmitFlowControl ); 962 963 /* Write to ETHERNET MACFCR */ 964 prvWriteMACFCR( heth, tmpreg ); 965 966 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ 967 heth->Instance->MACVLANTR = ( uint32_t ) ( macconf->VLANTagComparison | 968 macconf->VLANTagIdentifier ); 969 970 /* Wait until the write operation will be taken into account : 971 * at least four TX_CLK/RX_CLK clock cycles */ 972 tmpreg = heth->Instance->MACVLANTR; 973 vRegisterDelay(); 974 heth->Instance->MACVLANTR = tmpreg; 975 } 976 else /* macconf == NULL : here we just configure Speed and Duplex mode */ 977 { 978 /*------------------------ ETHERNET MACCR Configuration --------------------*/ 979 /* Get the ETHERNET MACCR value */ 980 tmpreg = heth->Instance->MACCR; 981 982 /* Clear FES and DM bits */ 983 tmpreg &= ~( ( uint32_t ) 0x00004800uL ); 984 985 tmpreg |= ( uint32_t ) ( heth->Init.Speed | heth->Init.DuplexMode ); 986 987 /* Write to ETHERNET MACCR */ 988 prvWriteMACCR( heth, tmpreg ); 989 } 990 991 /* Set the ETH state to Ready */ 992 heth->State = HAL_ETH_STATE_READY; 993 994 /* Process Unlocked */ 995 __HAL_UNLOCK( heth ); 996 997 /* Return function status */ 998 return HAL_OK; 999 } 1000 1001 /** 1002 * @brief Sets ETH DMA Configuration. 1003 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1004 * the configuration information for ETHERNET module 1005 * @param dmaconf: DMA Configuration structure 1006 * @retval HAL status 1007 */ HAL_ETH_ConfigDMA(ETH_HandleTypeDef * heth,ETH_DMAInitTypeDef * dmaconf)1008 HAL_StatusTypeDef HAL_ETH_ConfigDMA( ETH_HandleTypeDef * heth, 1009 ETH_DMAInitTypeDef * dmaconf ) 1010 { 1011 uint32_t tmpreg = 0uL; 1012 1013 /* Process Locked */ 1014 __HAL_LOCK( heth ); 1015 1016 /* Set the ETH peripheral state to BUSY */ 1017 heth->State = HAL_ETH_STATE_BUSY; 1018 1019 /* Check parameters */ 1020 assert_param( IS_ETH_DROP_TCPIP_CHECKSUM_FRAME( dmaconf->DropTCPIPChecksumErrorFrame ) ); 1021 assert_param( IS_ETH_RECEIVE_STORE_FORWARD( dmaconf->ReceiveStoreForward ) ); 1022 assert_param( IS_ETH_FLUSH_RECEIVE_FRAME( dmaconf->FlushReceivedFrame ) ); 1023 assert_param( IS_ETH_TRANSMIT_STORE_FORWARD( dmaconf->TransmitStoreForward ) ); 1024 assert_param( IS_ETH_TRANSMIT_THRESHOLD_CONTROL( dmaconf->TransmitThresholdControl ) ); 1025 assert_param( IS_ETH_FORWARD_ERROR_FRAMES( dmaconf->ForwardErrorFrames ) ); 1026 assert_param( IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES( dmaconf->ForwardUndersizedGoodFrames ) ); 1027 assert_param( IS_ETH_RECEIVE_THRESHOLD_CONTROL( dmaconf->ReceiveThresholdControl ) ); 1028 assert_param( IS_ETH_SECOND_FRAME_OPERATE( dmaconf->SecondFrameOperate ) ); 1029 assert_param( IS_ETH_ADDRESS_ALIGNED_BEATS( dmaconf->AddressAlignedBeats ) ); 1030 assert_param( IS_ETH_FIXED_BURST( dmaconf->FixedBurst ) ); 1031 assert_param( IS_ETH_RXDMA_BURST_LENGTH( dmaconf->RxDMABurstLength ) ); 1032 assert_param( IS_ETH_TXDMA_BURST_LENGTH( dmaconf->TxDMABurstLength ) ); 1033 assert_param( IS_ETH_ENHANCED_DESCRIPTOR_FORMAT( dmaconf->EnhancedDescriptorFormat ) ); 1034 assert_param( IS_ETH_DMA_DESC_SKIP_LENGTH( dmaconf->DescriptorSkipLength ) ); 1035 assert_param( IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX( dmaconf->DMAArbitration ) ); 1036 1037 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ 1038 /* Get the ETHERNET DMAOMR value */ 1039 tmpreg = heth->Instance->DMAOMR; 1040 /* Clear xx bits */ 1041 tmpreg &= ETH_DMAOMR_CLEAR_MASK; 1042 1043 tmpreg |= ( uint32_t ) ( 1044 dmaconf->DropTCPIPChecksumErrorFrame | 1045 dmaconf->ReceiveStoreForward | 1046 dmaconf->FlushReceivedFrame | 1047 dmaconf->TransmitStoreForward | 1048 dmaconf->TransmitThresholdControl | 1049 dmaconf->ForwardErrorFrames | 1050 dmaconf->ForwardUndersizedGoodFrames | 1051 dmaconf->ReceiveThresholdControl | 1052 dmaconf->SecondFrameOperate ); 1053 1054 /* Write to ETHERNET DMAOMR */ 1055 prvWriteDMAOMR( heth, tmpreg ); 1056 1057 /*----------------------- ETHERNET DMABMR Configuration --------------------*/ 1058 heth->Instance->DMABMR = ( uint32_t ) ( dmaconf->AddressAlignedBeats | 1059 dmaconf->FixedBurst | 1060 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ 1061 dmaconf->TxDMABurstLength | 1062 dmaconf->EnhancedDescriptorFormat | 1063 ( dmaconf->DescriptorSkipLength << 2 ) | 1064 dmaconf->DMAArbitration | 1065 ETH_DMABMR_USP ); /* Enable use of separate PBL for Rx and Tx */ 1066 1067 /* Wait until the write operation will be taken into account: 1068 * at least four TX_CLK/RX_CLK clock cycles */ 1069 tmpreg = heth->Instance->DMABMR; 1070 vRegisterDelay(); 1071 heth->Instance->DMABMR = tmpreg; 1072 1073 /* Set the ETH state to Ready */ 1074 heth->State = HAL_ETH_STATE_READY; 1075 1076 /* Process Unlocked */ 1077 __HAL_UNLOCK( heth ); 1078 1079 /* Return function status */ 1080 return HAL_OK; 1081 } 1082 1083 /** 1084 * @} 1085 */ 1086 1087 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions 1088 * @brief Peripheral State functions 1089 * 1090 * @verbatim 1091 * =============================================================================== 1092 ##### Peripheral State functions ##### 1093 #####=============================================================================== 1094 #####[..] 1095 #####This subsection permits to get in run-time the status of the peripheral 1096 #####and the data flow. 1097 ##### (+) Get the ETH handle state: 1098 ##### HAL_ETH_GetState(); 1099 ##### 1100 ##### 1101 #####@endverbatim 1102 * @{ 1103 */ 1104 1105 /** 1106 * @brief Return the ETH HAL state 1107 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1108 * the configuration information for ETHERNET module 1109 * @retval HAL state 1110 */ HAL_ETH_GetState(ETH_HandleTypeDef * heth)1111 HAL_ETH_StateTypeDef HAL_ETH_GetState( ETH_HandleTypeDef * heth ) 1112 { 1113 /* Return ETH state */ 1114 return heth->State; 1115 } 1116 1117 /** 1118 * @} 1119 */ 1120 1121 /** 1122 * @} 1123 */ 1124 1125 /** @addtogroup ETH_Private_Functions 1126 * @{ 1127 */ 1128 1129 /** 1130 * @brief Configures Ethernet MAC and DMA with default parameters. 1131 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1132 * the configuration information for ETHERNET module 1133 * @param err: Ethernet Init error 1134 * @retval HAL status 1135 */ ETH_MACDMAConfig(ETH_HandleTypeDef * heth,uint32_t err)1136 static void ETH_MACDMAConfig( ETH_HandleTypeDef * heth, 1137 uint32_t err ) 1138 { 1139 ETH_MACInitTypeDef macinit; 1140 ETH_DMAInitTypeDef dmainit; 1141 uint32_t tmpreg = 0uL; 1142 1143 if( err != ETH_SUCCESS ) /* Auto-negotiation failed */ 1144 { 1145 /* Set Ethernet duplex mode to Full-duplex */ 1146 heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX; 1147 1148 /* Set Ethernet speed to 100M */ 1149 heth->Init.Speed = ETH_SPEED_100M; 1150 } 1151 1152 /* Ethernet MAC default initialization **************************************/ 1153 macinit.Watchdog = ETH_WATCHDOG_ENABLE; 1154 macinit.Jabber = ETH_JABBER_ENABLE; 1155 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; 1156 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; 1157 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; 1158 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; 1159 1160 if( heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE ) 1161 { 1162 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; 1163 } 1164 else 1165 { 1166 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; 1167 } 1168 1169 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; 1170 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; 1171 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; 1172 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; 1173 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; 1174 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; 1175 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; 1176 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; 1177 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; 1178 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; 1179 /* Allow all multicast addresses while testing. */ 1180 /* macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; */ 1181 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE; 1182 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; 1183 macinit.HashTableHigh = 0x0uL; 1184 macinit.HashTableLow = 0x0uL; 1185 macinit.PauseTime = 0x0uL; 1186 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; 1187 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; 1188 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; 1189 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; 1190 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; 1191 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; 1192 macinit.VLANTagIdentifier = 0x0uL; 1193 1194 /*------------------------ ETHERNET MACCR Configuration --------------------*/ 1195 /* Get the ETHERNET MACCR value */ 1196 tmpreg = heth->Instance->MACCR; 1197 /* Clear WD, PCE, PS, TE and RE bits */ 1198 tmpreg &= ETH_MACCR_CLEAR_MASK; 1199 /* Set the WD bit according to ETH Watchdog value */ 1200 /* Set the JD: bit according to ETH Jabber value */ 1201 /* Set the IFG bit according to ETH InterFrameGap value */ 1202 /* Set the DCRS bit according to ETH CarrierSense value */ 1203 /* Set the FES bit according to ETH Speed value */ 1204 /* Set the DO bit according to ETH ReceiveOwn value */ 1205 /* Set the LM bit according to ETH LoopbackMode value */ 1206 /* Set the DM bit according to ETH Mode value */ 1207 /* Set the IPCO bit according to ETH ChecksumOffload value */ 1208 /* Set the DR bit according to ETH RetryTransmission value */ 1209 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ 1210 /* Set the BL bit according to ETH BackOffLimit value */ 1211 /* Set the DC bit according to ETH DeferralCheck value */ 1212 tmpreg |= ( uint32_t ) ( macinit.Watchdog | 1213 macinit.Jabber | 1214 macinit.InterFrameGap | 1215 macinit.CarrierSense | 1216 heth->Init.Speed | 1217 macinit.ReceiveOwn | 1218 macinit.LoopbackMode | 1219 heth->Init.DuplexMode | 1220 macinit.ChecksumOffload | 1221 macinit.RetryTransmission | 1222 macinit.AutomaticPadCRCStrip | 1223 macinit.BackOffLimit | 1224 macinit.DeferralCheck ); 1225 1226 /* Write to ETHERNET MACCR */ 1227 prvWriteMACCR( heth, tmpreg ); 1228 1229 /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 1230 /* Set the RA bit according to ETH ReceiveAll value */ 1231 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ 1232 /* Set the PCF bit according to ETH PassControlFrames value */ 1233 /* Set the DBF bit according to ETH BroadcastFramesReception value */ 1234 /* Set the DAIF bit according to ETH DestinationAddrFilter value */ 1235 /* Set the PR bit according to ETH PromiscuousMode value */ 1236 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ 1237 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ 1238 /* Write to ETHERNET MACFFR */ 1239 heth->Instance->MACFFR = ( uint32_t ) ( macinit.ReceiveAll | 1240 macinit.SourceAddrFilter | 1241 macinit.PassControlFrames | 1242 macinit.BroadcastFramesReception | 1243 macinit.DestinationAddrFilter | 1244 macinit.PromiscuousMode | 1245 macinit.MulticastFramesFilter | 1246 macinit.UnicastFramesFilter ); 1247 1248 /* Wait until the write operation will be taken into account: 1249 * at least four TX_CLK/RX_CLK clock cycles */ 1250 tmpreg = heth->Instance->MACFFR; 1251 vRegisterDelay(); 1252 heth->Instance->MACFFR = tmpreg; 1253 1254 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ 1255 /* Write to ETHERNET MACHTHR */ 1256 heth->Instance->MACHTHR = ( uint32_t ) macinit.HashTableHigh; 1257 1258 /* Write to ETHERNET MACHTLR */ 1259 heth->Instance->MACHTLR = ( uint32_t ) macinit.HashTableLow; 1260 /*----------------------- ETHERNET MACFCR Configuration -------------------*/ 1261 1262 /* Get the ETHERNET MACFCR value */ 1263 tmpreg = heth->Instance->MACFCR; 1264 /* Clear xx bits */ 1265 tmpreg &= ETH_MACFCR_CLEAR_MASK; 1266 1267 /* Set the PT bit according to ETH PauseTime value */ 1268 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ 1269 /* Set the PLT bit according to ETH PauseLowThreshold value */ 1270 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ 1271 /* Set the RFE bit according to ETH ReceiveFlowControl value */ 1272 /* Set the TFE bit according to ETH TransmitFlowControl value */ 1273 tmpreg |= ( uint32_t ) ( ( macinit.PauseTime << 16 ) | 1274 macinit.ZeroQuantaPause | 1275 macinit.PauseLowThreshold | 1276 macinit.UnicastPauseFrameDetect | 1277 macinit.ReceiveFlowControl | 1278 macinit.TransmitFlowControl ); 1279 1280 /* Write to ETHERNET MACFCR */ 1281 prvWriteMACFCR( heth, tmpreg ); 1282 1283 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ 1284 /* Set the ETV bit according to ETH VLANTagComparison value */ 1285 /* Set the VL bit according to ETH VLANTagIdentifier value */ 1286 heth->Instance->MACVLANTR = ( uint32_t ) ( macinit.VLANTagComparison | 1287 macinit.VLANTagIdentifier ); 1288 1289 /* Wait until the write operation will be taken into account: 1290 * at least four TX_CLK/RX_CLK clock cycles */ 1291 tmpreg = heth->Instance->MACVLANTR; 1292 vRegisterDelay(); 1293 heth->Instance->MACVLANTR = tmpreg; 1294 1295 /* Ethernet DMA default initialization ************************************/ 1296 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; 1297 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; 1298 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; 1299 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; 1300 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; 1301 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; 1302 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; 1303 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; 1304 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; 1305 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; 1306 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; 1307 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; 1308 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; 1309 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; 1310 dmainit.DescriptorSkipLength = 0x0uL; 1311 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; 1312 1313 /* Get the ETHERNET DMAOMR value */ 1314 tmpreg = heth->Instance->DMAOMR; 1315 /* Clear xx bits */ 1316 tmpreg &= ETH_DMAOMR_CLEAR_MASK; 1317 1318 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ 1319 /* Set the RSF bit according to ETH ReceiveStoreForward value */ 1320 /* Set the DFF bit according to ETH FlushReceivedFrame value */ 1321 /* Set the TSF bit according to ETH TransmitStoreForward value */ 1322 /* Set the TTC bit according to ETH TransmitThresholdControl value */ 1323 /* Set the FEF bit according to ETH ForwardErrorFrames value */ 1324 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ 1325 /* Set the RTC bit according to ETH ReceiveThresholdControl value */ 1326 /* Set the OSF bit according to ETH SecondFrameOperate value */ 1327 tmpreg |= ( uint32_t ) ( dmainit.DropTCPIPChecksumErrorFrame | 1328 dmainit.ReceiveStoreForward | 1329 dmainit.FlushReceivedFrame | 1330 dmainit.TransmitStoreForward | 1331 dmainit.TransmitThresholdControl | 1332 dmainit.ForwardErrorFrames | 1333 dmainit.ForwardUndersizedGoodFrames | 1334 dmainit.ReceiveThresholdControl | 1335 dmainit.SecondFrameOperate ); 1336 1337 /* Write to ETHERNET DMAOMR */ 1338 prvWriteDMAOMR( heth, tmpreg ); 1339 1340 /*----------------------- ETHERNET DMABMR Configuration ------------------*/ 1341 /* Set the AAL bit according to ETH AddressAlignedBeats value */ 1342 /* Set the FB bit according to ETH FixedBurst value */ 1343 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ 1344 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ 1345 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ 1346 /* Set the DSL bit according to ETH DesciptorSkipLength value */ 1347 /* Set the PR and DA bits according to ETH DMAArbitration value */ 1348 heth->Instance->DMABMR = ( uint32_t ) ( dmainit.AddressAlignedBeats | 1349 dmainit.FixedBurst | 1350 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ 1351 dmainit.TxDMABurstLength | 1352 dmainit.EnhancedDescriptorFormat | 1353 ( dmainit.DescriptorSkipLength << 2 ) | 1354 dmainit.DMAArbitration | 1355 ETH_DMABMR_USP ); /* Enable use of separate PBL for Rx and Tx */ 1356 1357 /* Wait until the write operation will be taken into account: 1358 * at least four TX_CLK/RX_CLK clock cycles */ 1359 tmpreg = heth->Instance->DMABMR; 1360 vRegisterDelay(); 1361 heth->Instance->DMABMR = tmpreg; 1362 1363 if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE ) 1364 { 1365 /* Enable the Ethernet Rx Interrupt */ 1366 __HAL_ETH_DMA_ENABLE_IT( ( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R ); 1367 } 1368 1369 /* Initialize MAC address in ethernet MAC */ 1370 ETH_MACAddressConfig( heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr ); 1371 } 1372 1373 /** 1374 * @brief Configures the selected MAC address. 1375 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1376 * the configuration information for ETHERNET module 1377 * @param MacAddr: The MAC address to configure 1378 * This parameter can be one of the following values: 1379 * @arg ETH_MAC_Address0: MAC Address0 1380 * @arg ETH_MAC_Address1: MAC Address1 1381 * @arg ETH_MAC_Address2: MAC Address2 1382 * @arg ETH_MAC_Address3: MAC Address3 1383 * @param Addr: Pointer to MAC address buffer data (6 bytes) 1384 * @retval HAL status 1385 */ ETH_MACAddressConfig(ETH_HandleTypeDef * heth,uint32_t MacAddr,uint8_t * Addr)1386 static void ETH_MACAddressConfig( ETH_HandleTypeDef * heth, 1387 uint32_t MacAddr, 1388 uint8_t * Addr ) 1389 { 1390 uint32_t tmpreg; 1391 1392 ( void ) heth; 1393 1394 /* Check the parameters */ 1395 assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) ); 1396 1397 /* Calculate the selected MAC address high register */ 1398 /* Register ETH_MACA0HR: Bit 31 MO: Always 1. */ 1399 tmpreg = 0x80000000uL | ( ( uint32_t ) Addr[ 5 ] << 8 ) | ( uint32_t ) Addr[ 4 ]; 1400 /* Load the selected MAC address high register */ 1401 ( *( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg; 1402 /* Calculate the selected MAC address low register */ 1403 tmpreg = ( ( uint32_t ) Addr[ 3 ] << 24 ) | ( ( uint32_t ) Addr[ 2 ] << 16 ) | ( ( uint32_t ) Addr[ 1 ] << 8 ) | Addr[ 0 ]; 1404 1405 /* Load the selected MAC address low register */ 1406 ( *( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg; 1407 } 1408 1409 /** 1410 * @brief Enables the MAC transmission. 1411 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1412 * the configuration information for ETHERNET module 1413 * @retval None 1414 */ ETH_MACTransmissionEnable(ETH_HandleTypeDef * heth)1415 static void ETH_MACTransmissionEnable( ETH_HandleTypeDef * heth ) 1416 { 1417 uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE; 1418 1419 prvWriteMACCR( heth, tmpreg ); 1420 } 1421 1422 /** 1423 * @brief Disables the MAC transmission. 1424 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1425 * the configuration information for ETHERNET module 1426 * @retval None 1427 */ ETH_MACTransmissionDisable(ETH_HandleTypeDef * heth)1428 static void ETH_MACTransmissionDisable( ETH_HandleTypeDef * heth ) 1429 { 1430 uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE ); 1431 1432 prvWriteMACCR( heth, tmpreg ); 1433 } 1434 1435 /** 1436 * @brief Enables the MAC reception. 1437 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1438 * the configuration information for ETHERNET module 1439 * @retval None 1440 */ ETH_MACReceptionEnable(ETH_HandleTypeDef * heth)1441 static void ETH_MACReceptionEnable( ETH_HandleTypeDef * heth ) 1442 { 1443 __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE; 1444 1445 prvWriteMACCR( heth, tmpreg ); 1446 } 1447 1448 /** 1449 * @brief Disables the MAC reception. 1450 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1451 * the configuration information for ETHERNET module 1452 * @retval None 1453 */ ETH_MACReceptionDisable(ETH_HandleTypeDef * heth)1454 static void ETH_MACReceptionDisable( ETH_HandleTypeDef * heth ) 1455 { 1456 __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE ); 1457 1458 prvWriteMACCR( heth, tmpreg ); 1459 } 1460 1461 /** 1462 * @brief Enables the DMA transmission. 1463 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1464 * the configuration information for ETHERNET module 1465 * @retval None 1466 */ ETH_DMATransmissionEnable(ETH_HandleTypeDef * heth)1467 static void ETH_DMATransmissionEnable( ETH_HandleTypeDef * heth ) 1468 { 1469 /* Enable the DMA transmission */ 1470 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST; 1471 1472 prvWriteDMAOMR( heth, tmpreg ); 1473 } 1474 1475 /** 1476 * @brief Disables the DMA transmission. 1477 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1478 * the configuration information for ETHERNET module 1479 * @retval None 1480 */ ETH_DMATransmissionDisable(ETH_HandleTypeDef * heth)1481 static void ETH_DMATransmissionDisable( ETH_HandleTypeDef * heth ) 1482 { 1483 /* Disable the DMA transmission */ 1484 __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST ); 1485 1486 prvWriteDMAOMR( heth, tmpreg ); 1487 } 1488 1489 /** 1490 * @brief Enables the DMA reception. 1491 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1492 * the configuration information for ETHERNET module 1493 * @retval None 1494 */ ETH_DMAReceptionEnable(ETH_HandleTypeDef * heth)1495 static void ETH_DMAReceptionEnable( ETH_HandleTypeDef * heth ) 1496 { 1497 /* Enable the DMA reception */ 1498 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR; 1499 1500 prvWriteDMAOMR( heth, tmpreg ); 1501 } 1502 1503 /** 1504 * @brief Disables the DMA reception. 1505 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1506 * the configuration information for ETHERNET module 1507 * @retval None 1508 */ ETH_DMAReceptionDisable(ETH_HandleTypeDef * heth)1509 static void ETH_DMAReceptionDisable( ETH_HandleTypeDef * heth ) 1510 { 1511 /* Disable the DMA reception */ 1512 __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR ); 1513 1514 prvWriteDMAOMR( heth, tmpreg ); 1515 } 1516 1517 /** 1518 * @brief Clears the ETHERNET transmit FIFO. 1519 * @param heth: pointer to a ETH_HandleTypeDef structure that contains 1520 * the configuration information for ETHERNET module 1521 * @retval None 1522 */ ETH_FlushTransmitFIFO(ETH_HandleTypeDef * heth)1523 static void ETH_FlushTransmitFIFO( ETH_HandleTypeDef * heth ) 1524 { 1525 /* Set the Flush Transmit FIFO bit */ 1526 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF; 1527 1528 prvWriteDMAOMR( heth, tmpreg ); 1529 } 1530 1531 /** 1532 * @} 1533 */ 1534 #endif /* stm_is_F1 != 0 || stm_is_F2 != 0 || stm_is_F4 != 0 || stm_is_F7 */ 1535 1536 #endif /* HAL_ETH_MODULE_ENABLED */ 1537 1538 /** 1539 * @} 1540 */ 1541 1542 /** 1543 * @} 1544 */ 1545 1546 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1547
xref:
/FreeRTOS-Plus-TCP-v4.0.0/source/portable/NetworkInterface/STM32Fxx/stm32fxx_hal_eth.c
(revision 2d3f4daa567ffe71aeda2e0f6d0bc02850db0627)