1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the RXv3 DPFPU port.
31 *----------------------------------------------------------*/
32
33 #warning Testing for DFPU support in this port is not yet complete
34
35 /* Scheduler includes. */
36 #include "FreeRTOS.h"
37 #include "task.h"
38
39 /* Library includes. */
40 #include "string.h"
41
42 /* Hardware specifics. */
43 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
44
45 #include "platform.h"
46
47 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
48
49 #include "iodefine.h"
50
51 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
52
53 /*-----------------------------------------------------------*/
54
55 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
56 * PSW is set with U and I set, and PM and IPL clear. */
57 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
58 #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
59 #define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 )
60 #define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 )
61 #define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 )
62
63 /* Tasks are not created with a DPFPU context, but can be given a DPFPU context
64 * after they have been created. A variable is stored as part of the tasks context
65 * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or
66 * any other value if the task does have a DPFPU context. */
67 #define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 )
68 #define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 )
69
70 /* The space on the stack required to hold the DPFPU data registers. This is 16
71 * 64-bit registers. */
72 #define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 )
73
74 /* These macros allow a critical section to be added around the call to
75 * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
76 * priority - ie a known priority. Therefore these local macros are a slight
77 * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
78 * which would require the old IPL to be read first and stored in a local variable. */
79 #define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
80 #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
81
82 /*-----------------------------------------------------------*/
83
84 /*
85 * Function to start the first task executing - written in asm code as direct
86 * access to registers is required.
87 */
88 static void prvStartFirstTask( void ) __attribute__( ( naked ) );
89
90 /*
91 * Software interrupt handler. Performs the actual context switch (saving and
92 * restoring of registers). Written in asm code as direct register access is
93 * required.
94 */
95 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
96
97 R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
98 R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
99
100 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
101
102 void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
103
104 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
105
106 /*
107 * The tick ISR handler. The peripheral used is configured by the application
108 * via a hook/callback function.
109 */
110 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
111
112 R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
113 R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
114
115 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
116
117 void vTickISR( void ) __attribute__( ( interrupt ) );
118
119 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
120
121 /*-----------------------------------------------------------*/
122
123 /* Saved as part of the task context. If ulPortTaskHasDPFPUContext is non-zero
124 * then a DPFPU context must be saved and restored for the task. */
125 #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
126
127 StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT;
128
129 #endif /* configUSE_TASK_DPFPU_SUPPORT */
130
131 /* This is accessed by the inline assembler functions so is file scope for
132 * convenience. */
133 extern void * pxCurrentTCB;
134 extern void vTaskSwitchContext( void );
135
136 /*-----------------------------------------------------------*/
137
138 /*
139 * See header file for description.
140 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)141 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
142 TaskFunction_t pxCode,
143 void * pvParameters )
144 {
145 /* R0 is not included as it is the stack pointer. */
146
147 *pxTopOfStack = 0x00;
148 pxTopOfStack--;
149 *pxTopOfStack = portINITIAL_PSW;
150 pxTopOfStack--;
151 *pxTopOfStack = ( StackType_t ) pxCode;
152
153 /* When debugging it can be useful if every register is set to a known
154 * value. Otherwise code space can be saved by just setting the registers
155 * that need to be set. */
156 #ifdef USE_FULL_REGISTER_INITIALISATION
157 {
158 pxTopOfStack--;
159 *pxTopOfStack = 0xffffffff; /* r15. */
160 pxTopOfStack--;
161 *pxTopOfStack = 0xeeeeeeee;
162 pxTopOfStack--;
163 *pxTopOfStack = 0xdddddddd;
164 pxTopOfStack--;
165 *pxTopOfStack = 0xcccccccc;
166 pxTopOfStack--;
167 *pxTopOfStack = 0xbbbbbbbb;
168 pxTopOfStack--;
169 *pxTopOfStack = 0xaaaaaaaa;
170 pxTopOfStack--;
171 *pxTopOfStack = 0x99999999;
172 pxTopOfStack--;
173 *pxTopOfStack = 0x88888888;
174 pxTopOfStack--;
175 *pxTopOfStack = 0x77777777;
176 pxTopOfStack--;
177 *pxTopOfStack = 0x66666666;
178 pxTopOfStack--;
179 *pxTopOfStack = 0x55555555;
180 pxTopOfStack--;
181 *pxTopOfStack = 0x44444444;
182 pxTopOfStack--;
183 *pxTopOfStack = 0x33333333;
184 pxTopOfStack--;
185 *pxTopOfStack = 0x22222222;
186 pxTopOfStack--;
187 }
188 #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
189 {
190 pxTopOfStack -= 15;
191 }
192 #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
193
194 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
195 pxTopOfStack--;
196 *pxTopOfStack = portINITIAL_FPSW;
197 pxTopOfStack--;
198 *pxTopOfStack = 0x11111111; /* Accumulator 1. */
199 pxTopOfStack--;
200 *pxTopOfStack = 0x22222222; /* Accumulator 1. */
201 pxTopOfStack--;
202 *pxTopOfStack = 0x33333333; /* Accumulator 1. */
203 pxTopOfStack--;
204 *pxTopOfStack = 0x44444444; /* Accumulator 0. */
205 pxTopOfStack--;
206 *pxTopOfStack = 0x55555555; /* Accumulator 0. */
207 pxTopOfStack--;
208 *pxTopOfStack = 0x66666666; /* Accumulator 0. */
209
210 #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
211 {
212 /* The task will start without a DPFPU context. A task that
213 * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
214 * executing any floating point instructions. */
215 pxTopOfStack--;
216 *pxTopOfStack = portNO_DPFPU_CONTEXT;
217 }
218 #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
219 {
220 /* The task will start with a DPFPU context. Leave enough
221 * space for the registers - and ensure they are initialised if desired. */
222 #ifdef USE_FULL_REGISTER_INITIALISATION
223 {
224 pxTopOfStack -= 2;
225 *( double * ) pxTopOfStack = 1515.1515; /* DR15. */
226 pxTopOfStack -= 2;
227 *( double * ) pxTopOfStack = 1414.1414; /* DR14. */
228 pxTopOfStack -= 2;
229 *( double * ) pxTopOfStack = 1313.1313; /* DR13. */
230 pxTopOfStack -= 2;
231 *( double * ) pxTopOfStack = 1212.1212; /* DR12. */
232 pxTopOfStack -= 2;
233 *( double * ) pxTopOfStack = 1111.1111; /* DR11. */
234 pxTopOfStack -= 2;
235 *( double * ) pxTopOfStack = 1010.1010; /* DR10. */
236 pxTopOfStack -= 2;
237 *( double * ) pxTopOfStack = 909.0909; /* DR9. */
238 pxTopOfStack -= 2;
239 *( double * ) pxTopOfStack = 808.0808; /* DR8. */
240 pxTopOfStack -= 2;
241 *( double * ) pxTopOfStack = 707.0707; /* DR7. */
242 pxTopOfStack -= 2;
243 *( double * ) pxTopOfStack = 606.0606; /* DR6. */
244 pxTopOfStack -= 2;
245 *( double * ) pxTopOfStack = 505.0505; /* DR5. */
246 pxTopOfStack -= 2;
247 *( double * ) pxTopOfStack = 404.0404; /* DR4. */
248 pxTopOfStack -= 2;
249 *( double * ) pxTopOfStack = 303.0303; /* DR3. */
250 pxTopOfStack -= 2;
251 *( double * ) pxTopOfStack = 202.0202; /* DR2. */
252 pxTopOfStack -= 2;
253 *( double * ) pxTopOfStack = 101.0101; /* DR1. */
254 pxTopOfStack -= 2;
255 *( double * ) pxTopOfStack = 9876.54321; /* DR0. */
256 }
257 #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
258 {
259 pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
260 memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
261 }
262 #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
263 pxTopOfStack--;
264 *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
265 pxTopOfStack--;
266 *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */
267 pxTopOfStack--;
268 *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */
269 }
270 #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 )
271 {
272 /* Omit DPFPU support. */
273 }
274 #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
275 {
276 #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
277 }
278 #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
279
280 return pxTopOfStack;
281 }
282 /*-----------------------------------------------------------*/
283
284 #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
285
vPortTaskUsesDPFPU(void)286 void vPortTaskUsesDPFPU( void )
287 {
288 /* A task is registering the fact that it needs a DPFPU context. Set the
289 * DPFPU flag (which is saved as part of the task context). */
290 ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT;
291 }
292
293 #endif /* configUSE_TASK_DPFPU_SUPPORT */
294 /*-----------------------------------------------------------*/
295
xPortStartScheduler(void)296 BaseType_t xPortStartScheduler( void )
297 {
298 extern void vApplicationSetupTimerInterrupt( void );
299
300 /* Use pxCurrentTCB just so it does not get optimised away. */
301 if( pxCurrentTCB != NULL )
302 {
303 /* Call an application function to set up the timer that will generate the
304 * tick interrupt. This way the application can decide which peripheral to
305 * use. A demo application is provided to show a suitable example. */
306 vApplicationSetupTimerInterrupt();
307
308 /* Enable the software interrupt. */
309 _IEN( _ICU_SWINT ) = 1;
310
311 /* Ensure the software interrupt is clear. */
312 _IR( _ICU_SWINT ) = 0;
313
314 /* Ensure the software interrupt is set to the kernel priority. */
315 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
316
317 /* Start the first task. */
318 prvStartFirstTask();
319 }
320
321 /* Should not get here. */
322 return pdFAIL;
323 }
324 /*-----------------------------------------------------------*/
325
vPortEndScheduler(void)326 void vPortEndScheduler( void )
327 {
328 /* Not implemented in ports where there is nothing to return to.
329 * Artificially force an assert. */
330 configASSERT( pxCurrentTCB == NULL );
331 }
332 /*-----------------------------------------------------------*/
333
prvStartFirstTask(void)334 static void prvStartFirstTask( void )
335 {
336 __asm volatile
337 (
338
339 /* When starting the scheduler there is nothing that needs moving to the
340 * interrupt stack because the function is not called from an interrupt.
341 * Just ensure the current stack is the user stack. */
342 "SETPSW U \n" \
343
344
345 /* Obtain the location of the stack associated with which ever task
346 * pxCurrentTCB is currently pointing to. */
347 "MOV.L #_pxCurrentTCB, R15 \n" \
348 "MOV.L [R15], R15 \n" \
349 "MOV.L [R15], R0 \n" \
350
351
352 /* Restore the registers from the stack of the task pointed to by
353 * pxCurrentTCB. */
354
355 #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
356
357 /* The restored ulPortTaskHasDPFPUContext is to be zero here.
358 * So, it is never necessary to restore the DPFPU context here. */
359 "POP R15 \n" \
360 "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \
361 "MOV.L R15, [R14] \n" \
362
363 #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
364 /* Restore the DPFPU context. */
365 "DPOPM.L DPSW-DECNT \n" \
366 "DPOPM.D DR0-DR15 \n" \
367
368 #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
369
370 "POP R15 \n" \
371
372 /* Accumulator low 32 bits. */
373 "MVTACLO R15, A0 \n" \
374 "POP R15 \n" \
375
376 /* Accumulator high 32 bits. */
377 "MVTACHI R15, A0 \n" \
378 "POP R15 \n" \
379
380 /* Accumulator guard. */
381 "MVTACGU R15, A0 \n" \
382 "POP R15 \n" \
383
384 /* Accumulator low 32 bits. */
385 "MVTACLO R15, A1 \n" \
386 "POP R15 \n" \
387
388 /* Accumulator high 32 bits. */
389 "MVTACHI R15, A1 \n" \
390 "POP R15 \n" \
391
392 /* Accumulator guard. */
393 "MVTACGU R15, A1 \n" \
394 "POP R15 \n" \
395
396 /* Floating point status word. */
397 "MVTC R15, FPSW \n" \
398
399 /* R1 to R15 - R0 is not included as it is the SP. */
400 "POPM R1-R15 \n" \
401
402 /* This pops the remaining registers. */
403 "RTE \n" \
404 "NOP \n" \
405 "NOP \n"
406 );
407 }
408 /*-----------------------------------------------------------*/
409
vSoftwareInterruptISR(void)410 void vSoftwareInterruptISR( void )
411 {
412 __asm volatile
413 (
414 /* Re-enable interrupts. */
415 "SETPSW I \n" \
416
417
418 /* Move the data that was automatically pushed onto the interrupt stack when
419 * the interrupt occurred from the interrupt stack to the user stack.
420 *
421 * R15 is saved before it is clobbered. */
422 "PUSH.L R15 \n" \
423
424 /* Read the user stack pointer. */
425 "MVFC USP, R15 \n" \
426
427 /* Move the address down to the data being moved. */
428 "SUB #12, R15 \n" \
429 "MVTC R15, USP \n" \
430
431 /* Copy the data across, R15, then PC, then PSW. */
432 "MOV.L [ R0 ], [ R15 ] \n" \
433 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
434 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
435
436 /* Move the interrupt stack pointer to its new correct position. */
437 "ADD #12, R0 \n" \
438
439 /* All the rest of the registers are saved directly to the user stack. */
440 "SETPSW U \n" \
441
442 /* Save the rest of the general registers (R15 has been saved already). */
443 "PUSHM R1-R14 \n" \
444
445 /* Save the FPSW and accumulators. */
446 "MVFC FPSW, R15 \n" \
447 "PUSH.L R15 \n" \
448 "MVFACGU #0, A1, R15 \n" \
449 "PUSH.L R15 \n" \
450 "MVFACHI #0, A1, R15 \n" \
451 "PUSH.L R15 \n" \
452 "MVFACLO #0, A1, R15 \n" /* Low order word. */ \
453 "PUSH.L R15 \n" \
454 "MVFACGU #0, A0, R15 \n" \
455 "PUSH.L R15 \n" \
456 "MVFACHI #0, A0, R15 \n" \
457 "PUSH.L R15 \n" \
458 "MVFACLO #0, A0, R15 \n" /* Low order word. */ \
459 "PUSH.L R15 \n" \
460
461 #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
462
463 /* Does the task have a DPFPU context that needs saving? If
464 * ulPortTaskHasDPFPUContext is 0 then no. */
465 "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n" \
466 "MOV.L [R15], R15 \n" \
467 "CMP #0, R15 \n" \
468
469 /* Save the DPFPU context, if any. */
470 "BEQ.B ?+ \n" \
471 "DPUSHM.D DR0-DR15 \n" \
472 "DPUSHM.L DPSW-DECNT \n" \
473 "?: \n" \
474
475 /* Save ulPortTaskHasDPFPUContext itself. */
476 "PUSH.L R15 \n" \
477
478 #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
479 /* Save the DPFPU context, always. */
480 "DPUSHM.D DR0-DR15 \n" \
481 "DPUSHM.L DPSW-DECNT \n" \
482
483 #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
484
485
486 /* Save the stack pointer to the TCB. */
487 "MOV.L #_pxCurrentTCB, R15 \n" \
488 "MOV.L [ R15 ], R15 \n" \
489 "MOV.L R0, [ R15 ] \n" \
490
491
492 /* Ensure the interrupt mask is set to the syscall priority while the kernel
493 * structures are being accessed. */
494 "MVTIPL %0 \n" \
495
496 /* Select the next task to run. */
497 "BSR.A _vTaskSwitchContext \n" \
498
499 /* Reset the interrupt mask as no more data structure access is required. */
500 "MVTIPL %1 \n" \
501
502
503 /* Load the stack pointer of the task that is now selected as the Running
504 * state task from its TCB. */
505 "MOV.L #_pxCurrentTCB,R15 \n" \
506 "MOV.L [ R15 ], R15 \n" \
507 "MOV.L [ R15 ], R0 \n" \
508
509
510 /* Restore the context of the new task. The PSW (Program Status Word) and
511 * PC will be popped by the RTE instruction. */
512
513 #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
514
515 /* Is there a DPFPU context to restore? If the restored
516 * ulPortTaskHasDPFPUContext is zero then no. */
517 "POP R15 \n" \
518 "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \
519 "MOV.L R15, [R14] \n" \
520 "CMP #0, R15 \n" \
521
522 /* Restore the DPFPU context, if any. */
523 "BEQ.B ?+ \n" \
524 "DPOPM.L DPSW-DECNT \n" \
525 "DPOPM.D DR0-DR15 \n" \
526 "?: \n" \
527
528 #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
529 /* Restore the DPFPU context, always. */
530 "DPOPM.L DPSW-DECNT \n" \
531 "DPOPM.D DR0-DR15 \n" \
532
533 #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
534
535 "POP R15 \n" \
536
537 /* Accumulator low 32 bits. */
538 "MVTACLO R15, A0 \n" \
539 "POP R15 \n" \
540
541 /* Accumulator high 32 bits. */
542 "MVTACHI R15, A0 \n" \
543 "POP R15 \n" \
544
545 /* Accumulator guard. */
546 "MVTACGU R15, A0 \n" \
547 "POP R15 \n" \
548
549 /* Accumulator low 32 bits. */
550 "MVTACLO R15, A1 \n" \
551 "POP R15 \n" \
552
553 /* Accumulator high 32 bits. */
554 "MVTACHI R15, A1 \n" \
555 "POP R15 \n" \
556
557 /* Accumulator guard. */
558 "MVTACGU R15, A1 \n" \
559 "POP R15 \n" \
560 "MVTC R15, FPSW \n" \
561 "POPM R1-R15 \n" \
562 "RTE \n" \
563 "NOP \n" \
564 "NOP "
565 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
566 );
567 }
568 /*-----------------------------------------------------------*/
569
vTickISR(void)570 void vTickISR( void )
571 {
572 /* Re-enabled interrupts. */
573 __asm volatile ( "SETPSW I" );
574
575 /* Increment the tick, and perform any processing the new tick value
576 * necessitates. Ensure IPL is at the max syscall value first. */
577 portMASK_INTERRUPTS_FROM_KERNEL_ISR();
578 {
579 if( xTaskIncrementTick() != pdFALSE )
580 {
581 taskYIELD();
582 }
583 }
584 portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
585 }
586 /*-----------------------------------------------------------*/
587
ulPortGetIPL(void)588 uint32_t ulPortGetIPL( void )
589 {
590 __asm volatile
591 (
592 "MVFC PSW, R1 \n" \
593 "SHLR #24, R1 \n" \
594 "RTS "
595 );
596
597 /* This will never get executed, but keeps the compiler from complaining. */
598 return 0;
599 }
600 /*-----------------------------------------------------------*/
601
vPortSetIPL(uint32_t ulNewIPL)602 void vPortSetIPL( uint32_t ulNewIPL )
603 {
604 /* Avoid compiler warning about unreferenced parameter. */
605 ( void ) ulNewIPL;
606
607 __asm volatile
608 (
609 "PUSH R5 \n" \
610 "MVFC PSW, R5 \n" \
611 "SHLL #24, R1 \n" \
612 "AND #-0F000001H, R5 \n" \
613 "OR R1, R5 \n" \
614 "MVTC R5, PSW \n" \
615 "POP R5 \n" \
616 "RTS "
617 );
618 }
619 /*-----------------------------------------------------------*/
620
