1 /*
2  * FreeRTOS Kernel V11.1.0
3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4  *
5  * SPDX-License-Identifier: MIT
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy of
8  * this software and associated documentation files (the "Software"), to deal in
9  * the Software without restriction, including without limitation the rights to
10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11  * the Software, and to permit persons to whom the Software is furnished to do so,
12  * subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in all
15  * copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * https://www.FreeRTOS.org
25  * https://github.com/FreeRTOS
26  *
27  */
28 
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the MicroBlaze port.
31 *----------------------------------------------------------*/
32 
33 
34 /* Scheduler includes. */
35 #include "FreeRTOS.h"
36 #include "task.h"
37 
38 /* Standard includes. */
39 #include <string.h>
40 
41 /* Hardware includes. */
42 #include <xintc.h>
43 #include <xintc_i.h>
44 #include <xtmrctr.h>
45 
46 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
47     #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
48 #endif
49 
50 /* Tasks are started with interrupts enabled. */
51 #define portINITIAL_MSR_STATE        ( ( StackType_t ) 0x02 )
52 
53 /* Tasks are started with a critical section nesting of 0 - however prior
54  * to the scheduler being commenced we don't want the critical nesting level
55  * to reach zero, so it is initialised to a high value. */
56 #define portINITIAL_NESTING_VALUE    ( 0xff )
57 
58 /* Our hardware setup only uses one counter. */
59 #define portCOUNTER_0                0
60 
61 /* The stack used by the ISR is filled with a known value to assist in
62  * debugging. */
63 #define portISR_STACK_FILL_VALUE     0x55555555
64 
65 /* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
66  * maintains it's own count, so this variable is saved as part of the task
67  * context. */
68 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
69 
70 /* To limit the amount of stack required by each task, this port uses a
71  * separate stack for interrupts. */
72 uint32_t * pulISRStack;
73 
74 /*-----------------------------------------------------------*/
75 
76 /*
77  * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
78  * could have alternatively used the watchdog timer or timer 1.
79  */
80 static void prvSetupTimerInterrupt( void );
81 /*-----------------------------------------------------------*/
82 
83 /*
84  * Initialise the stack of a task to look exactly as if a call to
85  * portSAVE_CONTEXT had been made.
86  *
87  * See the header file portable.h.
88  */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)89 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
90                                      TaskFunction_t pxCode,
91                                      void * pvParameters )
92 {
93     extern void * _SDA2_BASE_;
94     extern void * _SDA_BASE_;
95     const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
96     const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
97 
98     /* Place a few bytes of known values on the bottom of the stack.
99      * This is essential for the Microblaze port and these lines must
100      * not be omitted.  The parameter value will overwrite the
101      * 0x22222222 value during the function prologue. */
102     *pxTopOfStack = ( StackType_t ) 0x11111111;
103     pxTopOfStack--;
104     *pxTopOfStack = ( StackType_t ) 0x22222222;
105     pxTopOfStack--;
106     *pxTopOfStack = ( StackType_t ) 0x33333333;
107     pxTopOfStack--;
108 
109     /* First stack an initial value for the critical section nesting.  This
110      *  is initialised to zero as tasks are started with interrupts enabled. */
111     *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */
112 
113     /* Place an initial value for all the general purpose registers. */
114     pxTopOfStack--;
115     *pxTopOfStack = ( StackType_t ) ulR2;         /* R2 - small data area. */
116     pxTopOfStack--;
117     *pxTopOfStack = ( StackType_t ) 0x03;         /* R3. */
118     pxTopOfStack--;
119     *pxTopOfStack = ( StackType_t ) 0x04;         /* R4. */
120     pxTopOfStack--;
121     *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
122     pxTopOfStack--;
123     *pxTopOfStack = ( StackType_t ) 0x06;         /* R6. */
124     pxTopOfStack--;
125     *pxTopOfStack = ( StackType_t ) 0x07;         /* R7. */
126     pxTopOfStack--;
127     *pxTopOfStack = ( StackType_t ) 0x08;         /* R8. */
128     pxTopOfStack--;
129     *pxTopOfStack = ( StackType_t ) 0x09;         /* R9. */
130     pxTopOfStack--;
131     *pxTopOfStack = ( StackType_t ) 0x0a;         /* R10. */
132     pxTopOfStack--;
133     *pxTopOfStack = ( StackType_t ) 0x0b;         /* R11. */
134     pxTopOfStack--;
135     *pxTopOfStack = ( StackType_t ) 0x0c;         /* R12. */
136     pxTopOfStack--;
137     *pxTopOfStack = ( StackType_t ) ulR13;        /* R13 - small data read write area. */
138     pxTopOfStack--;
139     *pxTopOfStack = ( StackType_t ) pxCode;       /* R14. */
140     pxTopOfStack--;
141     *pxTopOfStack = ( StackType_t ) 0x0f;         /* R15. */
142     pxTopOfStack--;
143     *pxTopOfStack = ( StackType_t ) 0x10;         /* R16. */
144     pxTopOfStack--;
145     *pxTopOfStack = ( StackType_t ) 0x11;         /* R17. */
146     pxTopOfStack--;
147     *pxTopOfStack = ( StackType_t ) 0x12;         /* R18. */
148     pxTopOfStack--;
149     *pxTopOfStack = ( StackType_t ) 0x13;         /* R19. */
150     pxTopOfStack--;
151     *pxTopOfStack = ( StackType_t ) 0x14;         /* R20. */
152     pxTopOfStack--;
153     *pxTopOfStack = ( StackType_t ) 0x15;         /* R21. */
154     pxTopOfStack--;
155     *pxTopOfStack = ( StackType_t ) 0x16;         /* R22. */
156     pxTopOfStack--;
157     *pxTopOfStack = ( StackType_t ) 0x17;         /* R23. */
158     pxTopOfStack--;
159     *pxTopOfStack = ( StackType_t ) 0x18;         /* R24. */
160     pxTopOfStack--;
161     *pxTopOfStack = ( StackType_t ) 0x19;         /* R25. */
162     pxTopOfStack--;
163     *pxTopOfStack = ( StackType_t ) 0x1a;         /* R26. */
164     pxTopOfStack--;
165     *pxTopOfStack = ( StackType_t ) 0x1b;         /* R27. */
166     pxTopOfStack--;
167     *pxTopOfStack = ( StackType_t ) 0x1c;         /* R28. */
168     pxTopOfStack--;
169     *pxTopOfStack = ( StackType_t ) 0x1d;         /* R29. */
170     pxTopOfStack--;
171     *pxTopOfStack = ( StackType_t ) 0x1e;         /* R30. */
172     pxTopOfStack--;
173 
174     /* The MSR is stacked between R30 and R31. */
175     *pxTopOfStack = portINITIAL_MSR_STATE;
176     pxTopOfStack--;
177 
178     *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */
179     pxTopOfStack--;
180 
181     /* Return a pointer to the top of the stack we have generated so this can
182      * be stored in the task control block for the task. */
183     return pxTopOfStack;
184 }
185 /*-----------------------------------------------------------*/
186 
xPortStartScheduler(void)187 BaseType_t xPortStartScheduler( void )
188 {
189     extern void( __FreeRTOS_interrupt_Handler )( void );
190     extern void( vStartFirstTask )( void );
191 
192 
193     /* Setup the FreeRTOS interrupt handler.  Code copied from crt0.s. */
194     asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler        \n\t" \
195                    "sw r6, r1, r0                                  \n\t" \
196                    "lhu r7, r1, r0                                 \n\t" \
197                    "shi r7, r0, 0x12                               \n\t" \
198                    "shi r6, r0, 0x16 " );
199 
200     /* Setup the hardware to generate the tick.  Interrupts are disabled when
201      * this function is called. */
202     prvSetupTimerInterrupt();
203 
204     /* Allocate the stack to be used by the interrupt handler. */
205     pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
206 
207     /* Restore the context of the first task that is going to run. */
208     if( pulISRStack != NULL )
209     {
210         /* Fill the ISR stack with a known value to facilitate debugging. */
211         memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
212         pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
213 
214         /* Kick off the first task. */
215         vStartFirstTask();
216     }
217 
218     /* Should not get here as the tasks are now running! */
219     return pdFALSE;
220 }
221 /*-----------------------------------------------------------*/
222 
vPortEndScheduler(void)223 void vPortEndScheduler( void )
224 {
225     /* Not implemented. */
226 }
227 /*-----------------------------------------------------------*/
228 
229 /*
230  * Manual context switch called by portYIELD or taskYIELD.
231  */
vPortYield(void)232 void vPortYield( void )
233 {
234     extern void VPortYieldASM( void );
235 
236     /* Perform the context switch in a critical section to assure it is
237      * not interrupted by the tick ISR.  It is not a problem to do this as
238      * each task maintains it's own interrupt status. */
239     portENTER_CRITICAL();
240 
241     /* Jump directly to the yield function to ensure there is no
242      * compiler generated prologue code. */
243     asm volatile ( "bralid r14, VPortYieldASM      \n\t" \
244                    "or r0, r0, r0                  \n\t" );
245     portEXIT_CRITICAL();
246 }
247 /*-----------------------------------------------------------*/
248 
249 /*
250  * Hardware initialisation to generate the RTOS tick.
251  */
prvSetupTimerInterrupt(void)252 static void prvSetupTimerInterrupt( void )
253 {
254     XTmrCtr xTimer;
255     const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
256     UBaseType_t uxMask;
257 
258     /* The OPB timer1 is used to generate the tick.  Use the provided library
259      * functions to enable the timer and set the tick frequency. */
260     XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
261     XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
262     XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
263     XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_occurred_MASK );
264 
265     /* Set the timer interrupt enable bit while maintaining the other bit
266      * states. */
267     uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
268     uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
269     XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
270 
271     XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
272     XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_occurred_MASK );
273     XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
274 }
275 /*-----------------------------------------------------------*/
276 
277 /*
278  * The interrupt handler placed in the interrupt vector when the scheduler is
279  * started.  The task context has already been saved when this is called.
280  * This handler determines the interrupt source and calls the relevant
281  * peripheral handler.
282  */
vTaskISRHandler(void)283 void vTaskISRHandler( void )
284 {
285     static uint32_t ulPending;
286 
287     /* Which interrupts are pending? */
288     ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
289 
290     if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
291     {
292         static XIntc_VectorTableEntry * pxTablePtr;
293         static XIntc_Config * pxConfig;
294         static uint32_t ulInterruptMask;
295 
296         ulInterruptMask = ( uint32_t ) 1 << ulPending;
297 
298         /* Get the configuration data using the device ID */
299         pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
300 
301         pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
302 
303         if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
304         {
305             XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
306             pxTablePtr->Handler( pxTablePtr->CallBackRef );
307         }
308         else
309         {
310             pxTablePtr->Handler( pxTablePtr->CallBackRef );
311             XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
312         }
313     }
314 }
315 /*-----------------------------------------------------------*/
316 
317 /*
318  * Handler for the timer interrupt.
319  */
vTickISR(void * pvBaseAddress)320 void vTickISR( void * pvBaseAddress )
321 {
322     uint32_t ulCSR;
323 
324     /* Increment the RTOS tick - this might cause a task to unblock. */
325     if( xTaskIncrementTick() != pdFALSE )
326     {
327         vTaskSwitchContext();
328     }
329 
330     /* Clear the timer interrupt */
331     ulCSR = XTmrCtr_mGetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, 0 );
332     XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
333 }
334 /*-----------------------------------------------------------*/
335