1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdint.h>
31
32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
33 * is defined correctly and privileged functions are placed in correct sections. */
34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
35
36 /* Portasm includes. */
37 #include "portasm.h"
38
39 /* System call numbers includes. */
40 #include "mpu_syscall_numbers.h"
41
42 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
43 * header files. */
44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
45
46 #if ( configENABLE_MPU == 1 )
47
vRestoreContextOfFirstTask(void)48 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
49 {
50 __asm volatile
51 (
52 " .syntax unified \n"
53 " \n"
54 " program_mpu_first_task: \n"
55 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
56 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
57 " \n"
58 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
59 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
60 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
61 " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
62 " str r2, [r1] \n" /* Disable MPU. */
63 " \n"
64 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
65 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
66 " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
67 " str r1, [r2] \n" /* Program MAIR0. */
68 " \n"
69 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
70 " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
71 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
72 " \n"
73 " movs r3, #4 \n" /* r3 = 4. */
74 " str r3, [r1] \n" /* Program RNR = 4. */
75 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
76 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
77 " \n"
78 #if ( configTOTAL_MPU_REGIONS == 16 )
79 " movs r3, #8 \n" /* r3 = 8. */
80 " str r3, [r1] \n" /* Program RNR = 8. */
81 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
82 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
83 " movs r3, #12 \n" /* r3 = 12. */
84 " str r3, [r1] \n" /* Program RNR = 12. */
85 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
86 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
87 #endif /* configTOTAL_MPU_REGIONS == 16 */
88 " \n"
89 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
90 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
91 " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
92 " str r2, [r1] \n" /* Enable MPU. */
93 " dsb \n" /* Force memory writes before continuing. */
94 " \n"
95 " restore_context_first_task: \n"
96 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
97 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
98 " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
99 " \n"
100 " restore_special_regs_first_task: \n"
101 " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
102 " msr psp, r2 \n"
103 " msr psplim, r3 \n"
104 " msr control, r4 \n"
105 " \n"
106 " restore_general_regs_first_task: \n"
107 " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
108 " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
109 " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */
110 " \n"
111 " restore_context_done_first_task: \n"
112 " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
113 " mov r0, #0 \n"
114 " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
115 " bx lr \n"
116 );
117 }
118
119 #else /* configENABLE_MPU */
120
vRestoreContextOfFirstTask(void)121 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
122 {
123 __asm volatile
124 (
125 " .syntax unified \n"
126 " \n"
127 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
128 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
129 " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
130 " \n"
131 " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
132 " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
133 " movs r1, #2 \n" /* r1 = 2. */
134 " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
135 " adds r0, #32 \n" /* Discard everything up to r0. */
136 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
137 " isb \n"
138 " mov r0, #0 \n"
139 " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
140 " bx r2 \n" /* Finally, branch to EXC_RETURN. */
141 );
142 }
143
144 #endif /* configENABLE_MPU */
145 /*-----------------------------------------------------------*/
146
xIsPrivileged(void)147 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
148 {
149 __asm volatile
150 (
151 " .syntax unified \n"
152 " \n"
153 " mrs r0, control \n" /* r0 = CONTROL. */
154 " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
155 " ite ne \n"
156 " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
157 " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
158 " bx lr \n" /* Return. */
159 ::: "r0", "memory"
160 );
161 }
162 /*-----------------------------------------------------------*/
163
vRaisePrivilege(void)164 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
165 {
166 __asm volatile
167 (
168 " .syntax unified \n"
169 " \n"
170 " mrs r0, control \n" /* Read the CONTROL register. */
171 " bic r0, #1 \n" /* Clear the bit 0. */
172 " msr control, r0 \n" /* Write back the new CONTROL value. */
173 " bx lr \n" /* Return to the caller. */
174 ::: "r0", "memory"
175 );
176 }
177 /*-----------------------------------------------------------*/
178
vResetPrivilege(void)179 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
180 {
181 __asm volatile
182 (
183 " .syntax unified \n"
184 " \n"
185 " mrs r0, control \n" /* r0 = CONTROL. */
186 " orr r0, #1 \n" /* r0 = r0 | 1. */
187 " msr control, r0 \n" /* CONTROL = r0. */
188 " bx lr \n" /* Return to the caller. */
189 ::: "r0", "memory"
190 );
191 }
192 /*-----------------------------------------------------------*/
193
vStartFirstTask(void)194 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
195 {
196 __asm volatile
197 (
198 " .syntax unified \n"
199 " \n"
200 " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
201 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
202 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
203 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
204 " cpsie i \n" /* Globally enable interrupts. */
205 " cpsie f \n"
206 " dsb \n"
207 " isb \n"
208 " svc %0 \n" /* System call to start the first task. */
209 " nop \n"
210 ::"i" ( portSVC_START_SCHEDULER ) : "memory"
211 );
212 }
213 /*-----------------------------------------------------------*/
214
ulSetInterruptMask(void)215 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
216 {
217 __asm volatile
218 (
219 " .syntax unified \n"
220 " \n"
221 " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
222 " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
223 " msr basepri, r1 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
224 " dsb \n"
225 " isb \n"
226 " bx lr \n" /* Return. */
227 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
228 );
229 }
230 /*-----------------------------------------------------------*/
231
vClearInterruptMask(uint32_t ulMask)232 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
233 {
234 __asm volatile
235 (
236 " .syntax unified \n"
237 " \n"
238 " msr basepri, r0 \n" /* basepri = ulMask. */
239 " dsb \n"
240 " isb \n"
241 " bx lr \n" /* Return. */
242 ::: "memory"
243 );
244 }
245 /*-----------------------------------------------------------*/
246
247 #if ( configENABLE_MPU == 1 )
248
PendSV_Handler(void)249 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
250 {
251 __asm volatile
252 (
253 " .syntax unified \n"
254 " \n"
255 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
256 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
257 " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
258 " mrs r2, psp \n" /* r2 = PSP. */
259 " \n"
260 " save_general_regs: \n"
261 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
262 " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */
263 " tst lr, #0x10 \n"
264 " ittt eq \n"
265 " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */
266 " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */
267 " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */
268 " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */
269 #endif /* configENABLE_FPU || configENABLE_MVE */
270 " \n"
271 " stmia r1!, {r4-r11} \n" /* Store r4-r11. */
272 " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
273 " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */
274 " \n"
275 " save_special_regs: \n"
276 " mrs r3, psplim \n" /* r3 = PSPLIM. */
277 " mrs r4, control \n" /* r4 = CONTROL. */
278 " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
279 " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
280 " \n"
281 " select_next_task: \n"
282 " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
283 " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
284 " dsb \n"
285 " isb \n"
286 " bl vTaskSwitchContext \n"
287 " mov r0, #0 \n" /* r0 = 0. */
288 " msr basepri, r0 \n" /* Enable interrupts. */
289 " \n"
290 " program_mpu: \n"
291 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
292 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
293 " \n"
294 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
295 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
296 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
297 " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
298 " str r2, [r1] \n" /* Disable MPU. */
299 " \n"
300 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
301 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
302 " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
303 " str r1, [r2] \n" /* Program MAIR0. */
304 " \n"
305 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
306 " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
307 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
308 " \n"
309 " movs r3, #4 \n" /* r3 = 4. */
310 " str r3, [r1] \n" /* Program RNR = 4. */
311 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
312 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
313 " \n"
314 #if ( configTOTAL_MPU_REGIONS == 16 )
315 " movs r3, #8 \n" /* r3 = 8. */
316 " str r3, [r1] \n" /* Program RNR = 8. */
317 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
318 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
319 " movs r3, #12 \n" /* r3 = 12. */
320 " str r3, [r1] \n" /* Program RNR = 12. */
321 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
322 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
323 #endif /* configTOTAL_MPU_REGIONS == 16 */
324 " \n"
325 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
326 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
327 " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
328 " str r2, [r1] \n" /* Enable MPU. */
329 " dsb \n" /* Force memory writes before continuing. */
330 " \n"
331 " restore_context: \n"
332 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
333 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
334 " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
335 " \n"
336 " restore_special_regs: \n"
337 " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
338 " msr psp, r2 \n"
339 " msr psplim, r3 \n"
340 " msr control, r4 \n"
341 " \n"
342 " restore_general_regs: \n"
343 " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
344 " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
345 " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */
346 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
347 " tst lr, #0x10 \n"
348 " ittt eq \n"
349 " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */
350 " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */
351 " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */
352 #endif /* configENABLE_FPU || configENABLE_MVE */
353 " \n"
354 " restore_context_done: \n"
355 " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
356 " bx lr \n"
357 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
358 );
359 }
360
361 #else /* configENABLE_MPU */
362
PendSV_Handler(void)363 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
364 {
365 __asm volatile
366 (
367 " .syntax unified \n"
368 " \n"
369 " mrs r0, psp \n" /* Read PSP in r0. */
370 " \n"
371 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
372 " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
373 " it eq \n"
374 " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
375 #endif /* configENABLE_FPU || configENABLE_MVE */
376 " \n"
377 " mrs r2, psplim \n" /* r2 = PSPLIM. */
378 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
379 " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
380 " \n"
381 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
382 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
383 " str r0, [r1] \n" /* Save the new top of stack in TCB. */
384 " \n"
385 " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
386 " msr basepri, r0 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
387 " dsb \n"
388 " isb \n"
389 " bl vTaskSwitchContext \n"
390 " mov r0, #0 \n" /* r0 = 0. */
391 " msr basepri, r0 \n" /* Enable interrupts. */
392 " \n"
393 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
394 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
395 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
396 " \n"
397 " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
398 " \n"
399 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
400 " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
401 " it eq \n"
402 " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
403 #endif /* configENABLE_FPU || configENABLE_MVE */
404 " \n"
405 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
406 " msr psp, r0 \n" /* Remember the new top of stack for the task. */
407 " bx r3 \n"
408 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
409 );
410 }
411
412 #endif /* configENABLE_MPU */
413 /*-----------------------------------------------------------*/
414
415 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
416
SVC_Handler(void)417 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
418 {
419 __asm volatile
420 (
421 ".syntax unified \n"
422 ".extern vPortSVCHandler_C \n"
423 ".extern vSystemCallEnter \n"
424 ".extern vSystemCallExit \n"
425 " \n"
426 "tst lr, #4 \n"
427 "ite eq \n"
428 "mrseq r0, msp \n"
429 "mrsne r0, psp \n"
430 " \n"
431 "ldr r1, [r0, #24] \n"
432 "ldrb r2, [r1, #-2] \n"
433 "cmp r2, %0 \n"
434 "blt syscall_enter \n"
435 "cmp r2, %1 \n"
436 "beq syscall_exit \n"
437 "b vPortSVCHandler_C \n"
438 " \n"
439 "syscall_enter: \n"
440 " mov r1, lr \n"
441 " b vSystemCallEnter \n"
442 " \n"
443 "syscall_exit: \n"
444 " mov r1, lr \n"
445 " b vSystemCallExit \n"
446 " \n"
447 : /* No outputs. */
448 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
449 : "r0", "r1", "r2", "memory"
450 );
451 }
452
453 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
454
SVC_Handler(void)455 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
456 {
457 __asm volatile
458 (
459 " .syntax unified \n"
460 " \n"
461 " tst lr, #4 \n"
462 " ite eq \n"
463 " mrseq r0, msp \n"
464 " mrsne r0, psp \n"
465 " ldr r1, =vPortSVCHandler_C \n"
466 " bx r1 \n"
467 );
468 }
469
470 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
471 /*-----------------------------------------------------------*/
472
