1 /*
2 * FreeRTOS Kernel V11.0.1
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM3 MPU port.
31 *----------------------------------------------------------*/
32
33 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
34 * all the API functions to use the MPU wrappers. That should only be done when
35 * task.h is included from an application file. */
36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
37
38 /* Scheduler includes. */
39 #include "FreeRTOS.h"
40 #include "task.h"
41 #include "mpu_syscall_numbers.h"
42
43 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
44
45 #ifndef configSYSTICK_CLOCK_HZ
46 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
47 /* Ensure the SysTick is clocked at the same frequency as the core. */
48 #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
49 #else
50
51 /* The way the SysTick is clocked is not modified in case it is not the same
52 * as the core. */
53 #define portNVIC_SYSTICK_CLK ( 0 )
54 #endif
55
56 #ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
57 #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
58 #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
59 #endif
60
61 /* Prototype of all Interrupt Service Routines (ISRs). */
62 typedef void ( * portISR_t )( void );
63
64 /* Constants required to access and manipulate the NVIC. */
65 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
66 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
67 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
68 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
69 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
70 #define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
71 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
72
73 /* Constants required to access and manipulate the MPU. */
74 #define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
75 #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
76 #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
77 #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
78 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
79 #define portMPU_ENABLE ( 0x01UL )
80 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
81 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
82 #define portMPU_REGION_VALID ( 0x10UL )
83 #define portMPU_REGION_ENABLE ( 0x01UL )
84 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
85 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
86
87 /* Constants required to access and manipulate the SysTick. */
88 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
89 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
90 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
91 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
92 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
93
94 /* Constants required to set up the initial stack. */
95 #define portINITIAL_XPSR ( 0x01000000 )
96 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
97 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
98 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
99
100 /* Constants used to check the installation of the FreeRTOS interrupt handlers. */
101 #define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
102 #define portVECTOR_INDEX_SVC ( 11 )
103 #define portVECTOR_INDEX_PENDSV ( 14 )
104
105 /* Constants required to check the validity of an interrupt priority. */
106 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
107 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
108 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
109 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
110 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
111 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
112 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
113 #define portPRIGROUP_SHIFT ( 8UL )
114
115 /* Constants used during system call enter and exit. */
116 #define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
117
118 /* Offsets in the stack to the parameters when inside the SVC handler. */
119 #define portOFFSET_TO_LR ( 5 )
120 #define portOFFSET_TO_PC ( 6 )
121 #define portOFFSET_TO_PSR ( 7 )
122
123 /* For strict compliance with the Cortex-M spec the task start address should
124 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
125 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
126
127 /* Does addr lie within [start, end] address range? */
128 #define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
129 ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
130
131 /* Is the access request satisfied by the available permissions? */
132 #define portIS_AUTHORIZED( accessRequest, permissions ) \
133 ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
134
135 /* Max value that fits in a uint32_t type. */
136 #define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
137
138 /* Check if adding a and b will result in overflow. */
139 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
140 /*-----------------------------------------------------------*/
141
142 /*
143 * Configure a number of standard MPU regions that are used by all tasks.
144 */
145 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
146
147 /*
148 * Return the smallest MPU region size that a given number of bytes will fit
149 * into. The region size is returned as the value that should be programmed
150 * into the region attribute register for that region.
151 */
152 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
153
154 /*
155 * Setup the timer to generate the tick interrupts. The implementation in this
156 * file is weak to allow application writers to change the timer used to
157 * generate the tick interrupt.
158 */
159 void vPortSetupTimerInterrupt( void );
160
161 /*
162 * Standard FreeRTOS exception handlers.
163 */
164 void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
165 void xPortSysTickHandler( void ) __attribute__( ( optimize( "3" ) ) ) PRIVILEGED_FUNCTION;
166 void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
167
168 /*
169 * Starts the scheduler by restoring the context of the first task to run.
170 */
171 static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
172
173 /*
174 * C portion of the SVC handler. The SVC handler is split between an asm entry
175 * and a C wrapper for simplicity of coding and maintenance.
176 */
177 void vSVCHandler_C( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
178
179 /**
180 * @brief Checks whether or not the processor is privileged.
181 *
182 * @return 1 if the processor is already privileged, 0 otherwise.
183 */
184 BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
185
186 /**
187 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
188 * register.
189 *
190 * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
191 * Bit[0] = 0 --> The processor is running privileged
192 * Bit[0] = 1 --> The processor is running unprivileged.
193 */
194 void vResetPrivilege( void ) __attribute__( ( naked ) );
195
196 /**
197 * @brief Make a task unprivileged.
198 */
199 void vPortSwitchToUserMode( void );
200
201 /**
202 * @brief Enter critical section.
203 */
204 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
205 void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
206 #else
207 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
208 #endif
209
210 /**
211 * @brief Exit from critical section.
212 */
213 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
214 void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
215 #else
216 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
217 #endif
218
219 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
220
221 /**
222 * @brief Sets up the system call stack so that upon returning from
223 * SVC, the system call stack is used.
224 *
225 * @param pulTaskStack The current SP when the SVC was raised.
226 * @param ucSystemCallNumber The system call number of the system call.
227 */
228 void vSystemCallEnter( uint32_t * pulTaskStack,
229 uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
230
231 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
232
233 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
234
235 /**
236 * @brief Raise SVC for exiting from a system call.
237 */
238 void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
239
240 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
241
242 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
243
244 /**
245 * @brief Sets up the task stack so that upon returning from
246 * SVC, the task stack is used again.
247 *
248 * @param pulSystemCallStack The current SP when the SVC was raised.
249 */
250 void vSystemCallExit( uint32_t * pulSystemCallStack ) PRIVILEGED_FUNCTION;
251
252 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
253
254 /**
255 * @brief Checks whether or not the calling task is privileged.
256 *
257 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
258 */
259 BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
260 /*-----------------------------------------------------------*/
261
262 /* Each task maintains its own interrupt status in the critical nesting
263 * variable. Note this is not saved as part of the task context as context
264 * switches can only occur when uxCriticalNesting is zero. */
265 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
266
267 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
268
269 /*
270 * This variable is set to pdTRUE when the scheduler is started.
271 */
272 PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
273
274 #endif
275
276 /*
277 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
278 * FreeRTOS API functions are not called from interrupts that have been assigned
279 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
280 */
281 #if ( configASSERT_DEFINED == 1 )
282 static uint8_t ucMaxSysCallPriority = 0;
283 static uint32_t ulMaxPRIGROUPValue = 0;
284 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
285 #endif /* configASSERT_DEFINED */
286 /*-----------------------------------------------------------*/
287
288 /*
289 * See header file for description.
290 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters,BaseType_t xRunPrivileged,xMPU_SETTINGS * xMPUSettings)291 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
292 TaskFunction_t pxCode,
293 void * pvParameters,
294 BaseType_t xRunPrivileged,
295 xMPU_SETTINGS * xMPUSettings )
296 {
297 if( xRunPrivileged == pdTRUE )
298 {
299 xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
300 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED;
301 }
302 else
303 {
304 xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
305 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
306 }
307
308 xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
309 xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
310 xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
311 xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
312 xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
313 xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
314 xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
315 xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
316 xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
317
318 xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
319 xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
320 xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
321 xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
322 xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
323 xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
324 xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
325 xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
326 xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
327
328 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
329 {
330 /* Ensure that the system call stack is double word aligned. */
331 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
332 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
333 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
334
335 /* This is not NULL only for the duration of a system call. */
336 xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
337 }
338 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
339
340 return &( xMPUSettings->ulContext[ 19 ] );
341 }
342 /*-----------------------------------------------------------*/
343
344 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
345
vPortSVCHandler(void)346 void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
347 {
348 __asm volatile
349 (
350 ".syntax unified \n"
351 ".extern vSVCHandler_C \n"
352 ".extern vSystemCallEnter \n"
353 ".extern vSystemCallExit \n"
354 " \n"
355 "tst lr, #4 \n"
356 "ite eq \n"
357 "mrseq r0, msp \n"
358 "mrsne r0, psp \n"
359 " \n"
360 "ldr r2, [r0, #24] \n"
361 "ldrb r1, [r2, #-2] \n"
362 "cmp r1, %0 \n"
363 "blt vSystemCallEnter \n"
364 "cmp r1, %1 \n"
365 "beq vSystemCallExit \n"
366 "b vSVCHandler_C \n"
367 " \n"
368 : /* No outputs. */
369 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
370 : "r0", "r1", "r2", "memory"
371 );
372 }
373
374 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
375
vPortSVCHandler(void)376 void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
377 {
378 /* Assumes psp was in use. */
379 __asm volatile
380 (
381 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
382 " tst lr, #4 \n"
383 " ite eq \n"
384 " mrseq r0, msp \n"
385 " mrsne r0, psp \n"
386 #else
387 " mrs r0, psp \n"
388 #endif
389 " b %0 \n"
390 ::"i" ( vSVCHandler_C ) : "r0", "memory"
391 );
392 }
393
394 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
395 /*-----------------------------------------------------------*/
396
vSVCHandler_C(uint32_t * pulParam)397 void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
398 {
399 uint8_t ucSVCNumber;
400 uint32_t ulPC;
401
402 #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
403 #if defined( __ARMCC_VERSION )
404
405 /* Declaration when these variable are defined in code instead of being
406 * exported from linker scripts. */
407 extern uint32_t * __syscalls_flash_start__;
408 extern uint32_t * __syscalls_flash_end__;
409 #else
410 /* Declaration when these variable are exported from linker scripts. */
411 extern uint32_t __syscalls_flash_start__[];
412 extern uint32_t __syscalls_flash_end__[];
413 #endif /* #if defined( __ARMCC_VERSION ) */
414 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */
415
416 /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
417 * argument (r0) is pulParam[ 0 ]. */
418 ulPC = pulParam[ portOFFSET_TO_PC ];
419 ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
420
421 switch( ucSVCNumber )
422 {
423 case portSVC_START_SCHEDULER:
424 prvRestoreContextOfFirstTask();
425 break;
426
427 case portSVC_YIELD:
428 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
429
430 /* Barriers are normally not required
431 * but do ensure the code is completely
432 * within the specified behaviour for the
433 * architecture. */
434 __asm volatile ( "dsb" ::: "memory" );
435 __asm volatile ( "isb" );
436
437 break;
438
439 #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
440 #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
441 case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
442 * svc was raised from any of the
443 * system calls. */
444
445 if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
446 ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
447 {
448 __asm volatile
449 (
450 " mrs r1, control \n" /* Obtain current control value. */
451 " bic r1, #1 \n" /* Set privilege bit. */
452 " msr control, r1 \n" /* Write back new control value. */
453 ::: "r1", "memory"
454 );
455 }
456
457 break;
458 #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
459 case portSVC_RAISE_PRIVILEGE:
460 __asm volatile
461 (
462 " mrs r1, control \n" /* Obtain current control value. */
463 " bic r1, #1 \n" /* Set privilege bit. */
464 " msr control, r1 \n" /* Write back new control value. */
465 ::: "r1", "memory"
466 );
467 break;
468 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
469 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
470
471 default: /* Unknown SVC call. */
472 break;
473 }
474 }
475 /*-----------------------------------------------------------*/
476
477 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
478
vSystemCallEnter(uint32_t * pulTaskStack,uint8_t ucSystemCallNumber)479 void vSystemCallEnter( uint32_t * pulTaskStack,
480 uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
481 {
482 extern TaskHandle_t pxCurrentTCB;
483 extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
484 xMPU_SETTINGS * pxMpuSettings;
485 uint32_t * pulSystemCallStack;
486 uint32_t ulSystemCallLocation, i;
487 const uint32_t ulStackFrameSize = 8;
488
489 #if defined( __ARMCC_VERSION )
490 /* Declaration when these variable are defined in code instead of being
491 * exported from linker scripts. */
492 extern uint32_t * __syscalls_flash_start__;
493 extern uint32_t * __syscalls_flash_end__;
494 #else
495 /* Declaration when these variable are exported from linker scripts. */
496 extern uint32_t __syscalls_flash_start__[];
497 extern uint32_t __syscalls_flash_end__[];
498 #endif /* #if defined( __ARMCC_VERSION ) */
499
500 ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
501 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
502
503 /* Checks:
504 * 1. SVC is raised from the system call section (i.e. application is
505 * not raising SVC directly).
506 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
507 * it is non-NULL only during the execution of a system call (i.e.
508 * between system call enter and exit).
509 * 3. System call is not for a kernel API disabled by the configuration
510 * in FreeRTOSConfig.h.
511 * 4. We do not need to check that ucSystemCallNumber is within range
512 * because the assembly SVC handler checks that before calling
513 * this function.
514 */
515 if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
516 ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
517 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
518 ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
519 {
520 pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
521
522 /* Make space on the system call stack for the stack frame. */
523 pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
524
525 /* Copy the stack frame. */
526 for( i = 0; i < ulStackFrameSize; i++ )
527 {
528 pulSystemCallStack[ i ] = pulTaskStack[ i ];
529 }
530
531 /* Use the pulSystemCallStack in thread mode. */
532 __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
533
534 /* Raise the privilege for the duration of the system call. */
535 __asm volatile (
536 " mrs r1, control \n" /* Obtain current control value. */
537 " bic r1, #1 \n" /* Clear nPRIV bit. */
538 " msr control, r1 \n" /* Write back new control value. */
539 ::: "r1", "memory"
540 );
541
542 /* Remember the location where we should copy the stack frame when we exit from
543 * the system call. */
544 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
545
546 /* Store the value of the Link Register before the SVC was raised.
547 * It contains the address of the caller of the System Call entry
548 * point (i.e. the caller of the MPU_<API>). We need to restore it
549 * when we exit from the system call. */
550 pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
551
552 /* Start executing the system call upon returning from this handler. */
553 pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
554 /* Raise a request to exit from the system call upon finishing the
555 * system call. */
556 pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
557
558 /* Record if the hardware used padding to force the stack pointer
559 * to be double word aligned. */
560 if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
561 {
562 pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
563 }
564 else
565 {
566 pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
567 }
568
569 /* We ensure in pxPortInitialiseStack that the system call stack is
570 * double word aligned and therefore, there is no need of padding.
571 * Clear the bit[9] of stacked xPSR. */
572 pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
573 }
574 }
575
576 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
577 /*-----------------------------------------------------------*/
578
579 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
580
vRequestSystemCallExit(void)581 void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
582 {
583 __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
584 }
585
586 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
587 /*-----------------------------------------------------------*/
588
589 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
590
vSystemCallExit(uint32_t * pulSystemCallStack)591 void vSystemCallExit( uint32_t * pulSystemCallStack ) /* PRIVILEGED_FUNCTION */
592 {
593 extern TaskHandle_t pxCurrentTCB;
594 xMPU_SETTINGS * pxMpuSettings;
595 uint32_t * pulTaskStack;
596 uint32_t ulSystemCallLocation, i;
597 const uint32_t ulStackFrameSize = 8;
598
599 #if defined( __ARMCC_VERSION )
600 /* Declaration when these variable are defined in code instead of being
601 * exported from linker scripts. */
602 extern uint32_t * __privileged_functions_start__;
603 extern uint32_t * __privileged_functions_end__;
604 #else
605 /* Declaration when these variable are exported from linker scripts. */
606 extern uint32_t __privileged_functions_start__[];
607 extern uint32_t __privileged_functions_end__[];
608 #endif /* #if defined( __ARMCC_VERSION ) */
609
610 ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
611 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
612
613 /* Checks:
614 * 1. SVC is raised from the privileged code (i.e. application is not
615 * raising SVC directly). This SVC is only raised from
616 * vRequestSystemCallExit which is in the privileged code section.
617 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
618 * this means that we previously entered a system call and the
619 * application is not attempting to exit without entering a system
620 * call.
621 */
622 if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
623 ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
624 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
625 {
626 pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
627
628 /* Make space on the task stack for the stack frame. */
629 pulTaskStack = pulTaskStack - ulStackFrameSize;
630
631 /* Copy the stack frame. */
632 for( i = 0; i < ulStackFrameSize; i++ )
633 {
634 pulTaskStack[ i ] = pulSystemCallStack[ i ];
635 }
636
637 /* Use the pulTaskStack in thread mode. */
638 __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
639
640 /* Drop the privilege before returning to the thread mode. */
641 __asm volatile (
642 " mrs r1, control \n" /* Obtain current control value. */
643 " orr r1, #1 \n" /* Set nPRIV bit. */
644 " msr control, r1 \n" /* Write back new control value. */
645 ::: "r1", "memory"
646 );
647
648 /* Return to the caller of the System Call entry point (i.e. the
649 * caller of the MPU_<API>). */
650 pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
651 /* Ensure that LR has a valid value.*/
652 pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
653
654 /* If the hardware used padding to force the stack pointer
655 * to be double word aligned, set the stacked xPSR bit[9],
656 * otherwise clear it. */
657 if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
658 {
659 pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
660 }
661 else
662 {
663 pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
664 }
665
666 /* This is not NULL only for the duration of the system call. */
667 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
668 }
669 }
670
671 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
672 /*-----------------------------------------------------------*/
673
xPortIsTaskPrivileged(void)674 BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
675 {
676 BaseType_t xTaskIsPrivileged = pdFALSE;
677 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
678
679 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
680 {
681 xTaskIsPrivileged = pdTRUE;
682 }
683
684 return xTaskIsPrivileged;
685 }
686 /*-----------------------------------------------------------*/
687
prvRestoreContextOfFirstTask(void)688 static void prvRestoreContextOfFirstTask( void )
689 {
690 __asm volatile
691 (
692 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
693 " ldr r0, [r0] \n"
694 " ldr r0, [r0] \n"
695 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
696 " \n"
697 /*------------ Program MPU. ------------ */
698 " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
699 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
700 " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
701 " \n"
702 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
703 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
704 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
705 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
706 " str r3, [r0] \n" /* Disable MPU. */
707 " \n"
708 " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
709 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
710 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
711 " \n"
712 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
713 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
714 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
715 " str r3, [r0] \n" /* Enable MPU. */
716 " dsb \n" /* Force memory writes before continuing. */
717 " \n"
718 /*---------- Restore Context. ---------- */
719 " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
720 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
721 " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
722 " \n"
723 " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
724 " msr psp, r0 \n"
725 " stmia r0, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
726 " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */
727 " msr control, r3 \n"
728 " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */
729 " \n"
730 " mov r0, #0 \n"
731 " msr basepri, r0 \n"
732 " bx lr \n"
733 " \n"
734 " .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
735 " .align 4 \n"
736 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
737 );
738 }
739 /*-----------------------------------------------------------*/
740
741 /*
742 * See header file for description.
743 */
xPortStartScheduler(void)744 BaseType_t xPortStartScheduler( void )
745 {
746 /* An application can install FreeRTOS interrupt handlers in one of the
747 * folllowing ways:
748 * 1. Direct Routing - Install the functions vPortSVCHandler and
749 * xPortPendSVHandler for SVCall and PendSV interrupts respectively.
750 * 2. Indirect Routing - Install separate handlers for SVCall and PendSV
751 * interrupts and route program control from those handlers to
752 * vPortSVCHandler and xPortPendSVHandler functions.
753 *
754 * Applications that use Indirect Routing must set
755 * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct
756 * routing, which is validated here when configCHECK_HANDLER_INSTALLATION
757 * is 1, should be preferred when possible. */
758 #if ( configCHECK_HANDLER_INSTALLATION == 1 )
759 {
760 const portISR_t * const pxVectorTable = portSCB_VTOR_REG;
761
762 /* Validate that the application has correctly installed the FreeRTOS
763 * handlers for SVCall and PendSV interrupts. We do not check the
764 * installation of the SysTick handler because the application may
765 * choose to drive the RTOS tick using a timer other than the SysTick
766 * timer by overriding the weak function vPortSetupTimerInterrupt().
767 *
768 * Assertion failures here indicate incorrect installation of the
769 * FreeRTOS handlers. For help installing the FreeRTOS handlers, see
770 * https://www.FreeRTOS.org/FAQHelp.html.
771 *
772 * Systems with a configurable address for the interrupt vector table
773 * can also encounter assertion failures or even system faults here if
774 * VTOR is not set correctly to point to the application's vector table. */
775 configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler );
776 configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler );
777 }
778 #endif /* configCHECK_HANDLER_INSTALLATION */
779
780 #if ( configASSERT_DEFINED == 1 )
781 {
782 volatile uint8_t ucOriginalPriority;
783 volatile uint32_t ulImplementedPrioBits = 0;
784 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
785 volatile uint8_t ucMaxPriorityValue;
786
787 /* Determine the maximum priority from which ISR safe FreeRTOS API
788 * functions can be called. ISR safe functions are those that end in
789 * "FromISR". FreeRTOS maintains separate thread and ISR API functions
790 * to ensure interrupt entry is as fast and simple as possible.
791 *
792 * Save the interrupt priority value that is about to be clobbered. */
793 ucOriginalPriority = *pucFirstUserPriorityRegister;
794
795 /* Determine the number of priority bits available. First write to all
796 * possible bits. */
797 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
798
799 /* Read the value back to see how many bits stuck. */
800 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
801
802 /* Use the same mask on the maximum system call priority. */
803 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
804
805 /* Check that the maximum system call priority is nonzero after
806 * accounting for the number of priority bits supported by the
807 * hardware. A priority of 0 is invalid because setting the BASEPRI
808 * register to 0 unmasks all interrupts, and interrupts with priority 0
809 * cannot be masked using BASEPRI.
810 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
811 configASSERT( ucMaxSysCallPriority );
812
813 /* Check that the bits not implemented in hardware are zero in
814 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
815 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
816
817 /* Calculate the maximum acceptable priority group value for the number
818 * of bits read back. */
819
820 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
821 {
822 ulImplementedPrioBits++;
823 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
824 }
825
826 if( ulImplementedPrioBits == 8 )
827 {
828 /* When the hardware implements 8 priority bits, there is no way for
829 * the software to configure PRIGROUP to not have sub-priorities. As
830 * a result, the least significant bit is always used for sub-priority
831 * and there are 128 preemption priorities and 2 sub-priorities.
832 *
833 * This may cause some confusion in some cases - for example, if
834 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
835 * priority interrupts will be masked in Critical Sections as those
836 * are at the same preemption priority. This may appear confusing as
837 * 4 is higher (numerically lower) priority than
838 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
839 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
840 * to 4, this confusion does not happen and the behaviour remains the same.
841 *
842 * The following assert ensures that the sub-priority bit in the
843 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
844 * confusion. */
845 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
846 ulMaxPRIGROUPValue = 0;
847 }
848 else
849 {
850 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
851 }
852
853 /* Shift the priority group value back to its position within the AIRCR
854 * register. */
855 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
856 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
857
858 /* Restore the clobbered interrupt priority register to its original
859 * value. */
860 *pucFirstUserPriorityRegister = ucOriginalPriority;
861 }
862 #endif /* configASSERT_DEFINED */
863
864 /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall
865 * the highest priority. */
866 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
867 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
868 portNVIC_SHPR2_REG = 0;
869
870
871 /* Configure the regions in the MPU that are common to all tasks. */
872 prvSetupMPU();
873
874 /* Start the timer that generates the tick ISR. Interrupts are disabled
875 * here already. */
876 vPortSetupTimerInterrupt();
877
878 /* Initialise the critical nesting count ready for the first task. */
879 uxCriticalNesting = 0;
880
881 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
882 {
883 xSchedulerRunning = pdTRUE;
884 }
885 #endif
886
887 /* Start the first task. */
888 __asm volatile (
889 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
890 " ldr r0, [r0] \n"
891 " ldr r0, [r0] \n"
892 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
893 " cpsie i \n" /* Globally enable interrupts. */
894 " cpsie f \n"
895 " dsb \n"
896 " isb \n"
897 " svc %0 \n" /* System call to start first task. */
898 " nop \n"
899 " .ltorg \n"
900 ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
901
902 /* Should not get here! */
903 return 0;
904 }
905 /*-----------------------------------------------------------*/
906
vPortEndScheduler(void)907 void vPortEndScheduler( void )
908 {
909 /* Not implemented in ports where there is nothing to return to.
910 * Artificially force an assert. */
911 configASSERT( uxCriticalNesting == 1000UL );
912 }
913 /*-----------------------------------------------------------*/
914
vPortEnterCritical(void)915 void vPortEnterCritical( void )
916 {
917 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
918 if( portIS_PRIVILEGED() == pdFALSE )
919 {
920 portRAISE_PRIVILEGE();
921 portMEMORY_BARRIER();
922
923 portDISABLE_INTERRUPTS();
924 uxCriticalNesting++;
925 portMEMORY_BARRIER();
926
927 portRESET_PRIVILEGE();
928 portMEMORY_BARRIER();
929 }
930 else
931 {
932 portDISABLE_INTERRUPTS();
933 uxCriticalNesting++;
934 }
935 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
936 portDISABLE_INTERRUPTS();
937 uxCriticalNesting++;
938 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
939 }
940 /*-----------------------------------------------------------*/
941
vPortExitCritical(void)942 void vPortExitCritical( void )
943 {
944 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
945 if( portIS_PRIVILEGED() == pdFALSE )
946 {
947 portRAISE_PRIVILEGE();
948 portMEMORY_BARRIER();
949
950 configASSERT( uxCriticalNesting );
951 uxCriticalNesting--;
952
953 if( uxCriticalNesting == 0 )
954 {
955 portENABLE_INTERRUPTS();
956 }
957
958 portMEMORY_BARRIER();
959
960 portRESET_PRIVILEGE();
961 portMEMORY_BARRIER();
962 }
963 else
964 {
965 configASSERT( uxCriticalNesting );
966 uxCriticalNesting--;
967
968 if( uxCriticalNesting == 0 )
969 {
970 portENABLE_INTERRUPTS();
971 }
972 }
973 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
974 configASSERT( uxCriticalNesting );
975 uxCriticalNesting--;
976
977 if( uxCriticalNesting == 0 )
978 {
979 portENABLE_INTERRUPTS();
980 }
981 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
982 }
983 /*-----------------------------------------------------------*/
984
xPortPendSVHandler(void)985 void xPortPendSVHandler( void )
986 {
987 /* This is a naked function. */
988
989 __asm volatile
990 (
991 " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
992 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
993 " ldr r1, [r2] \n" /* r1 = Location where the context should be saved. */
994 " \n"
995 /*------------ Save Context. ----------- */
996 " mrs r3, control \n"
997 " mrs r0, psp \n"
998 " isb \n"
999 " \n"
1000 " stmia r1!, {r3-r11, lr} \n" /* Store CONTROL register, r4-r11 and LR. */
1001 " ldmia r0, {r4-r11} \n" /* Copy hardware saved context into r4-r11. */
1002 " stmia r1!, {r0, r4-r11} \n" /* Store original PSP (after hardware has saved context) and the hardware saved context. */
1003 " str r1, [r2] \n" /* Save the location from where the context should be restored as the first member of TCB. */
1004 " \n"
1005 /*---------- Select next task. --------- */
1006 " mov r0, %0 \n"
1007 " msr basepri, r0 \n"
1008 " dsb \n"
1009 " isb \n"
1010 " bl vTaskSwitchContext \n"
1011 " mov r0, #0 \n"
1012 " msr basepri, r0 \n"
1013 " \n"
1014 /*------------ Program MPU. ------------ */
1015 " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
1016 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
1017 " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
1018 " \n"
1019 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
1020 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
1021 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
1022 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
1023 " str r3, [r0] \n" /* Disable MPU. */
1024 " \n"
1025 " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
1026 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
1027 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
1028 " \n"
1029 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
1030 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
1031 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
1032 " str r3, [r0] \n" /* Enable MPU. */
1033 " dsb \n" /* Force memory writes before continuing. */
1034 " \n"
1035 /*---------- Restore Context. ---------- */
1036 " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
1037 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
1038 " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
1039 " \n"
1040 " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
1041 " msr psp, r0 \n"
1042 " stmia r0, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
1043 " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */
1044 " msr control, r3 \n"
1045 " \n"
1046 " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */
1047 " bx lr \n"
1048 " \n"
1049 " .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
1050 " .align 4 \n"
1051 "pxCurrentTCBConst: .word pxCurrentTCB \n"
1052 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
1053 );
1054 }
1055 /*-----------------------------------------------------------*/
1056
xPortSysTickHandler(void)1057 void xPortSysTickHandler( void )
1058 {
1059 uint32_t ulDummy;
1060
1061 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
1062 traceISR_ENTER();
1063 {
1064 /* Increment the RTOS tick. */
1065 if( xTaskIncrementTick() != pdFALSE )
1066 {
1067 traceISR_EXIT_TO_SCHEDULER();
1068 /* Pend a context switch. */
1069 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
1070 }
1071 else
1072 {
1073 traceISR_EXIT();
1074 }
1075 }
1076 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
1077 }
1078 /*-----------------------------------------------------------*/
1079
1080 /*
1081 * Setup the systick timer to generate the tick interrupts at the required
1082 * frequency.
1083 */
vPortSetupTimerInterrupt(void)1084 __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
1085 {
1086 /* Stop and clear the SysTick. */
1087 portNVIC_SYSTICK_CTRL_REG = 0UL;
1088 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
1089
1090 /* Configure SysTick to interrupt at the requested rate. */
1091 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
1092 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
1093 }
1094 /*-----------------------------------------------------------*/
1095
prvSetupMPU(void)1096 static void prvSetupMPU( void )
1097 {
1098 extern uint32_t __privileged_functions_start__[];
1099 extern uint32_t __privileged_functions_end__[];
1100 extern uint32_t __FLASH_segment_start__[];
1101 extern uint32_t __FLASH_segment_end__[];
1102 extern uint32_t __privileged_data_start__[];
1103 extern uint32_t __privileged_data_end__[];
1104
1105 /* Check the expected MPU is present. */
1106 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
1107 {
1108 /* First setup the unprivileged flash for unprivileged read only access. */
1109 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
1110 ( portMPU_REGION_VALID ) |
1111 ( portUNPRIVILEGED_FLASH_REGION );
1112
1113 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
1114 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
1115 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
1116 ( portMPU_REGION_ENABLE );
1117
1118 /* Setup the privileged flash for privileged only access. This is where
1119 * the kernel code is * placed. */
1120 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
1121 ( portMPU_REGION_VALID ) |
1122 ( portPRIVILEGED_FLASH_REGION );
1123
1124 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
1125 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
1126 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
1127 ( portMPU_REGION_ENABLE );
1128
1129 /* Setup the privileged data RAM region. This is where the kernel data
1130 * is placed. */
1131 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
1132 ( portMPU_REGION_VALID ) |
1133 ( portPRIVILEGED_RAM_REGION );
1134
1135 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
1136 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
1137 ( portMPU_REGION_EXECUTE_NEVER ) |
1138 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
1139 ( portMPU_REGION_ENABLE );
1140
1141 /* By default allow everything to access the general peripherals. The
1142 * system peripherals and registers are protected. */
1143 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
1144 ( portMPU_REGION_VALID ) |
1145 ( portGENERAL_PERIPHERALS_REGION );
1146
1147 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
1148 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
1149 ( portMPU_REGION_ENABLE );
1150
1151 /* Enable the memory fault exception. */
1152 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
1153
1154 /* Enable the MPU with the background region configured. */
1155 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
1156 }
1157 }
1158 /*-----------------------------------------------------------*/
1159
prvGetMPURegionSizeSetting(uint32_t ulActualSizeInBytes)1160 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
1161 {
1162 uint32_t ulRegionSize, ulReturnValue = 4;
1163
1164 /* 32 is the smallest region size, 31 is the largest valid value for
1165 * ulReturnValue. */
1166 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
1167 {
1168 if( ulActualSizeInBytes <= ulRegionSize )
1169 {
1170 break;
1171 }
1172 else
1173 {
1174 ulReturnValue++;
1175 }
1176 }
1177
1178 /* Shift the code by one before returning so it can be written directly
1179 * into the the correct bit position of the attribute register. */
1180 return( ulReturnValue << 1UL );
1181 }
1182 /*-----------------------------------------------------------*/
1183
xIsPrivileged(void)1184 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
1185 {
1186 __asm volatile
1187 (
1188 " mrs r0, control \n" /* r0 = CONTROL. */
1189 " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
1190 " ite ne \n"
1191 " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
1192 " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
1193 " bx lr \n" /* Return. */
1194 " \n"
1195 " .align 4 \n"
1196 ::: "r0", "memory"
1197 );
1198 }
1199 /*-----------------------------------------------------------*/
1200
vResetPrivilege(void)1201 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
1202 {
1203 __asm volatile
1204 (
1205 " mrs r0, control \n" /* r0 = CONTROL. */
1206 " orr r0, #1 \n" /* r0 = r0 | 1. */
1207 " msr control, r0 \n" /* CONTROL = r0. */
1208 " bx lr \n" /* Return to the caller. */
1209 ::: "r0", "memory"
1210 );
1211 }
1212 /*-----------------------------------------------------------*/
1213
vPortSwitchToUserMode(void)1214 void vPortSwitchToUserMode( void )
1215 {
1216 /* Load the current task's MPU settings from its TCB. */
1217 xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL );
1218
1219 /* Mark the task as unprivileged. */
1220 xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) );
1221
1222 /* Lower the processor's privilege level. */
1223 vResetPrivilege();
1224 }
1225 /*-----------------------------------------------------------*/
1226
vPortStoreTaskMPUSettings(xMPU_SETTINGS * xMPUSettings,const struct xMEMORY_REGION * const xRegions,StackType_t * pxBottomOfStack,uint32_t ulStackDepth)1227 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
1228 const struct xMEMORY_REGION * const xRegions,
1229 StackType_t * pxBottomOfStack,
1230 uint32_t ulStackDepth )
1231 {
1232 extern uint32_t __SRAM_segment_start__[];
1233 extern uint32_t __SRAM_segment_end__[];
1234 extern uint32_t __privileged_data_start__[];
1235 extern uint32_t __privileged_data_end__[];
1236 int32_t lIndex;
1237 uint32_t ul;
1238
1239 if( xRegions == NULL )
1240 {
1241 /* No MPU regions are specified so allow access to all RAM. */
1242 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1243 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
1244 ( portMPU_REGION_VALID ) |
1245 ( portSTACK_REGION ); /* Region number. */
1246
1247 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1248 ( portMPU_REGION_READ_WRITE ) |
1249 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
1250 ( portMPU_REGION_EXECUTE_NEVER ) |
1251 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
1252 ( portMPU_REGION_ENABLE );
1253
1254 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__;
1255 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__;
1256 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1257 tskMPU_WRITE_PERMISSION );
1258
1259 /* Invalidate user configurable regions. */
1260 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1261 {
1262 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1263 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1264 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1265 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1266 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1267 }
1268 }
1269 else
1270 {
1271 /* This function is called automatically when the task is created - in
1272 * which case the stack region parameters will be valid. At all other
1273 * times the stack parameters will not be valid and it is assumed that the
1274 * stack region has already been configured. */
1275 if( ulStackDepth > 0 )
1276 {
1277 /* Define the region that allows access to the stack. */
1278 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1279 ( ( uint32_t ) pxBottomOfStack ) |
1280 ( portMPU_REGION_VALID ) |
1281 ( portSTACK_REGION ); /* Region number. */
1282
1283 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1284 ( portMPU_REGION_READ_WRITE ) |
1285 ( portMPU_REGION_EXECUTE_NEVER ) |
1286 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
1287 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
1288 ( portMPU_REGION_ENABLE );
1289 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
1290 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
1291 ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
1292 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1293 tskMPU_WRITE_PERMISSION );
1294 }
1295
1296 lIndex = 0;
1297
1298 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1299 {
1300 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
1301 {
1302 /* Translate the generic region definition contained in
1303 * xRegions into the CM3 specific MPU settings that are then
1304 * stored in xMPUSettings. */
1305 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
1306 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
1307 ( portMPU_REGION_VALID ) |
1308 ( ul - 1UL ); /* Region number. */
1309
1310 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
1311 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
1312 ( xRegions[ lIndex ].ulParameters ) |
1313 ( portMPU_REGION_ENABLE );
1314
1315 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
1316 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
1317 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1318
1319 if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
1320 ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
1321 {
1322 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
1323 }
1324
1325 if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
1326 {
1327 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
1328 }
1329 }
1330 else
1331 {
1332 /* Invalidate the region. */
1333 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1334 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1335 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1336 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1337 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1338 }
1339
1340 lIndex++;
1341 }
1342 }
1343 }
1344 /*-----------------------------------------------------------*/
1345
xPortIsAuthorizedToAccessBuffer(const void * pvBuffer,uint32_t ulBufferLength,uint32_t ulAccessRequested)1346 BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
1347 uint32_t ulBufferLength,
1348 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
1349
1350 {
1351 uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
1352 BaseType_t xAccessGranted = pdFALSE;
1353 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1354
1355 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1356 {
1357 xAccessGranted = pdTRUE;
1358 }
1359 else
1360 {
1361 if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
1362 {
1363 ulBufferStartAddress = ( uint32_t ) pvBuffer;
1364 ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
1365
1366 for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
1367 {
1368 if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
1369 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1370 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1371 portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
1372 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1373 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1374 portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
1375 {
1376 xAccessGranted = pdTRUE;
1377 break;
1378 }
1379 }
1380 }
1381 }
1382
1383 return xAccessGranted;
1384 }
1385 /*-----------------------------------------------------------*/
1386
1387 #if ( configASSERT_DEFINED == 1 )
1388
vPortValidateInterruptPriority(void)1389 void vPortValidateInterruptPriority( void )
1390 {
1391 uint32_t ulCurrentInterrupt;
1392 uint8_t ucCurrentPriority;
1393
1394 /* Obtain the number of the currently executing interrupt. */
1395 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
1396
1397 /* Is the interrupt number a user defined interrupt? */
1398 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
1399 {
1400 /* Look up the interrupt's priority. */
1401 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
1402
1403 /* The following assertion will fail if a service routine (ISR) for
1404 * an interrupt that has been assigned a priority above
1405 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
1406 * function. ISR safe FreeRTOS API functions must *only* be called
1407 * from interrupts that have been assigned a priority at or below
1408 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1409 *
1410 * Numerically low interrupt priority numbers represent logically high
1411 * interrupt priorities, therefore the priority of the interrupt must
1412 * be set to a value equal to or numerically *higher* than
1413 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1414 *
1415 * Interrupts that use the FreeRTOS API must not be left at their
1416 * default priority of zero as that is the highest possible priority,
1417 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
1418 * and therefore also guaranteed to be invalid.
1419 *
1420 * FreeRTOS maintains separate thread and ISR API functions to ensure
1421 * interrupt entry is as fast and simple as possible.
1422 *
1423 * The following links provide detailed information:
1424 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
1425 * https://www.FreeRTOS.org/FAQHelp.html */
1426 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
1427 }
1428
1429 /* Priority grouping: The interrupt controller (NVIC) allows the bits
1430 * that define each interrupt's priority to be split between bits that
1431 * define the interrupt's pre-emption priority bits and bits that define
1432 * the interrupt's sub-priority. For simplicity all bits must be defined
1433 * to be pre-emption priority bits. The following assertion will fail if
1434 * this is not the case (if some bits represent a sub-priority).
1435 *
1436 * If the application only uses CMSIS libraries for interrupt
1437 * configuration then the correct setting can be achieved on all Cortex-M
1438 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
1439 * scheduler. Note however that some vendor specific peripheral libraries
1440 * assume a non-zero priority group setting, in which cases using a value
1441 * of zero will result in unpredictable behaviour. */
1442 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
1443 }
1444
1445 #endif /* configASSERT_DEFINED */
1446 /*-----------------------------------------------------------*/
1447
1448 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1449
vPortGrantAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1450 void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1451 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1452 {
1453 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1454 xMPU_SETTINGS * xTaskMpuSettings;
1455
1456 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1457 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1458
1459 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1460
1461 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
1462 }
1463
1464 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1465 /*-----------------------------------------------------------*/
1466
1467 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1468
vPortRevokeAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1469 void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1470 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1471 {
1472 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1473 xMPU_SETTINGS * xTaskMpuSettings;
1474
1475 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1476 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1477
1478 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1479
1480 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
1481 }
1482
1483 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1484 /*-----------------------------------------------------------*/
1485
1486 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
1487
1488 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
1489
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1490 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1491 {
1492 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1493 BaseType_t xAccessGranted = pdFALSE;
1494 const xMPU_SETTINGS * xTaskMpuSettings;
1495
1496 if( xSchedulerRunning == pdFALSE )
1497 {
1498 /* Grant access to all the kernel objects before the scheduler
1499 * is started. It is necessary because there is no task running
1500 * yet and therefore, we cannot use the permissions of any
1501 * task. */
1502 xAccessGranted = pdTRUE;
1503 }
1504 else
1505 {
1506 xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1507
1508 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1509 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1510
1511 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1512 {
1513 xAccessGranted = pdTRUE;
1514 }
1515 else
1516 {
1517 if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
1518 {
1519 xAccessGranted = pdTRUE;
1520 }
1521 }
1522 }
1523
1524 return xAccessGranted;
1525 }
1526
1527 #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1528
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1529 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1530 {
1531 ( void ) lInternalIndexOfKernelObject;
1532
1533 /* If Access Control List feature is not used, all the tasks have
1534 * access to all the kernel objects. */
1535 return pdTRUE;
1536 }
1537
1538 #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1539
1540 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
1541 /*-----------------------------------------------------------*/
1542
