1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Secure context includes. */
30 #include "secure_context.h"
31
32 /* Secure port macros. */
33 #include "secure_port_macros.h"
34
35 #if ( configENABLE_FPU == 1 )
36 #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
37 #endif
38
39 void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
40 void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
41
SecureContext_LoadContextAsm(SecureContext_t * pxSecureContext)42 void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
43 {
44 /* pxSecureContext value is in r0. */
45 __asm volatile
46 (
47 " .syntax unified \n"
48 " \n"
49 " mrs r1, ipsr \n" /* r1 = IPSR. */
50 " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
51 " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
52 " \n"
53 #if ( configENABLE_MPU == 1 )
54 " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
55 " msr control, r3 \n" /* CONTROL = r3. */
56 #endif /* configENABLE_MPU */
57 " \n"
58 " msr psplim, r2 \n" /* PSPLIM = r2. */
59 " msr psp, r1 \n" /* PSP = r1. */
60 " \n"
61 " load_ctx_therad_mode: \n"
62 " bx lr \n"
63 " \n"
64 ::: "r0", "r1", "r2"
65 );
66 }
67 /*-----------------------------------------------------------*/
68
SecureContext_SaveContextAsm(SecureContext_t * pxSecureContext)69 void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
70 {
71 /* pxSecureContext value is in r0. */
72 __asm volatile
73 (
74 " .syntax unified \n"
75 " \n"
76 " mrs r1, ipsr \n" /* r1 = IPSR. */
77 " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
78 " mrs r1, psp \n" /* r1 = PSP. */
79 " \n"
80 #if ( configENABLE_MPU == 1 )
81 " mrs r2, control \n" /* r2 = CONTROL. */
82 " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */
83 " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
84 " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */
85 #else /* configENABLE_MPU */
86 " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
87 #endif /* configENABLE_MPU */
88 " \n"
89 " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
90 " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
91 " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
92 " \n"
93 " save_ctx_therad_mode: \n"
94 " bx lr \n"
95 " \n"
96 ::"i" ( securecontextNO_STACK ) : "r1", "memory"
97 );
98 }
99 /*-----------------------------------------------------------*/
100
