1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdint.h>
31
32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
33 * is defined correctly and privileged functions are placed in correct sections. */
34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
35
36 /* Portasm includes. */
37 #include "portasm.h"
38
39 /* System call numbers includes. */
40 #include "mpu_syscall_numbers.h"
41
42 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
43 * header files. */
44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
45
46 #if ( configENABLE_FPU == 1 )
47 #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
48 #endif
49
50 #if ( configENABLE_MPU == 1 )
51
vRestoreContextOfFirstTask(void)52 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
53 {
54 __asm volatile
55 (
56 " .syntax unified \n"
57 " \n"
58 " program_mpu_first_task: \n"
59 " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
60 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
61 " \n"
62 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
63 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
64 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
65 " movs r3, #1 \n" /* r3 = 1. */
66 " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
67 " str r2, [r1] \n" /* Disable MPU. */
68 " \n"
69 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
70 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
71 " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
72 " str r1, [r2] \n" /* Program MAIR0. */
73 " \n"
74 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
75 " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
76 " \n"
77 " movs r3, #4 \n" /* r3 = 4. */
78 " str r3, [r1] \n" /* Program RNR = 4. */
79 " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
80 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
81 " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
82 " movs r3, #5 \n" /* r3 = 5. */
83 " str r3, [r1] \n" /* Program RNR = 5. */
84 " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
85 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
86 " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
87 " movs r3, #6 \n" /* r3 = 6. */
88 " str r3, [r1] \n" /* Program RNR = 6. */
89 " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
90 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
91 " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
92 " movs r3, #7 \n" /* r3 = 6. */
93 " str r3, [r1] \n" /* Program RNR = 7. */
94 " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
95 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
96 " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
97 " \n"
98 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
99 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
100 " movs r3, #1 \n" /* r3 = 1. */
101 " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
102 " str r2, [r1] \n" /* Enable MPU. */
103 " dsb \n" /* Force memory writes before continuing. */
104 " \n"
105 " restore_context_first_task: \n"
106 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
107 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
108 " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
109 " \n"
110 " restore_special_regs_first_task: \n"
111 " subs r1, #16 \n"
112 " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
113 " subs r1, #16 \n"
114 " msr psp, r2 \n"
115 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
116 " msr psplim, r3 \n"
117 #endif
118 " msr control, r4 \n"
119 " mov lr, r5 \n"
120 " \n"
121 " restore_general_regs_first_task: \n"
122 " subs r1, #32 \n"
123 " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
124 " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
125 " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
126 " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
127 " subs r1, #48 \n"
128 " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
129 " mov r8, r4 \n" /* r8 = r4. */
130 " mov r9, r5 \n" /* r9 = r5. */
131 " mov r10, r6 \n" /* r10 = r6. */
132 " mov r11, r7 \n" /* r11 = r7. */
133 " subs r1, #32 \n"
134 " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
135 " subs r1, #16 \n"
136 " \n"
137 " restore_context_done_first_task: \n"
138 " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
139 " bx lr \n"
140 );
141 }
142
143 #else /* configENABLE_MPU */
144
vRestoreContextOfFirstTask(void)145 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
146 {
147 __asm volatile
148 (
149 " .syntax unified \n"
150 " \n"
151 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
152 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
153 " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
154 " \n"
155 " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
156 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
157 " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
158 #endif
159 " movs r1, #2 \n" /* r1 = 2. */
160 " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
161 " adds r0, #32 \n" /* Discard everything up to r0. */
162 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
163 " isb \n"
164 " bx r2 \n" /* Finally, branch to EXC_RETURN. */
165 );
166 }
167
168 #endif /* configENABLE_MPU */
169 /*-----------------------------------------------------------*/
170
xIsPrivileged(void)171 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
172 {
173 __asm volatile
174 (
175 " .syntax unified \n"
176 " \n"
177 " mrs r0, control \n" /* r0 = CONTROL. */
178 " movs r1, #1 \n" /* r1 = 1. */
179 " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
180 " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */
181 " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
182 " bx lr \n" /* Return. */
183 " running_privileged: \n"
184 " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
185 " bx lr \n" /* Return. */
186 ::: "r0", "r1", "memory"
187 );
188 }
189 /*-----------------------------------------------------------*/
190
vRaisePrivilege(void)191 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
192 {
193 __asm volatile
194 (
195 " .syntax unified \n"
196 " \n"
197 " mrs r0, control \n" /* Read the CONTROL register. */
198 " movs r1, #1 \n" /* r1 = 1. */
199 " bics r0, r1 \n" /* Clear the bit 0. */
200 " msr control, r0 \n" /* Write back the new CONTROL value. */
201 " bx lr \n" /* Return to the caller. */
202 ::: "r0", "r1", "memory"
203 );
204 }
205 /*-----------------------------------------------------------*/
206
vResetPrivilege(void)207 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
208 {
209 __asm volatile
210 (
211 " .syntax unified \n"
212 " \n"
213 " mrs r0, control \n" /* r0 = CONTROL. */
214 " movs r1, #1 \n" /* r1 = 1. */
215 " orrs r0, r1 \n" /* r0 = r0 | r1. */
216 " msr control, r0 \n" /* CONTROL = r0. */
217 " bx lr \n" /* Return to the caller. */
218 ::: "r0", "r1", "memory"
219 );
220 }
221 /*-----------------------------------------------------------*/
222
vStartFirstTask(void)223 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
224 {
225 __asm volatile
226 (
227 " .syntax unified \n"
228 " \n"
229 " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
230 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
231 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
232 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
233 " cpsie i \n" /* Globally enable interrupts. */
234 " dsb \n"
235 " isb \n"
236 " svc %0 \n" /* System call to start the first task. */
237 " nop \n"
238 ::"i" ( portSVC_START_SCHEDULER ) : "memory"
239 );
240 }
241 /*-----------------------------------------------------------*/
242
ulSetInterruptMask(void)243 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
244 {
245 __asm volatile
246 (
247 " .syntax unified \n"
248 " \n"
249 " mrs r0, PRIMASK \n"
250 " cpsid i \n"
251 " bx lr \n"
252 ::: "memory"
253 );
254 }
255 /*-----------------------------------------------------------*/
256
vClearInterruptMask(uint32_t ulMask)257 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
258 {
259 __asm volatile
260 (
261 " .syntax unified \n"
262 " \n"
263 " msr PRIMASK, r0 \n"
264 " bx lr \n"
265 ::: "memory"
266 );
267 }
268 /*-----------------------------------------------------------*/
269
270 #if ( configENABLE_MPU == 1 )
271
PendSV_Handler(void)272 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
273 {
274 __asm volatile
275 (
276 " .syntax unified \n"
277 " \n"
278 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
279 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
280 " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
281 " mrs r2, psp \n" /* r2 = PSP. */
282 " \n"
283 " save_general_regs: \n"
284 " stmia r1!, {r4-r7} \n" /* Store r4-r7. */
285 " mov r4, r8 \n" /* r4 = r8. */
286 " mov r5, r9 \n" /* r5 = r9. */
287 " mov r6, r10 \n" /* r6 = r10. */
288 " mov r7, r11 \n" /* r7 = r11. */
289 " stmia r1!, {r4-r7} \n" /* Store r8-r11. */
290 " ldmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */
291 " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
292 " ldmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */
293 " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
294 " \n"
295 " save_special_regs: \n"
296 " mrs r2, psp \n" /* r2 = PSP. */
297 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
298 " mrs r3, psplim \n" /* r3 = PSPLIM. */
299 #else
300 " movs r3, #0 \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */
301 #endif
302 " mrs r4, control \n" /* r4 = CONTROL. */
303 " mov r5, lr \n" /* r5 = LR. */
304 " stmia r1!, {r2-r5} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
305 " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
306 " \n"
307 " select_next_task: \n"
308 " cpsid i \n"
309 " bl vTaskSwitchContext \n"
310 " cpsie i \n"
311 " \n"
312 " program_mpu: \n"
313 " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
314 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
315 " \n"
316 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
317 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
318 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
319 " movs r3, #1 \n" /* r3 = 1. */
320 " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
321 " str r2, [r1] \n" /* Disable MPU. */
322 " \n"
323 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
324 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
325 " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
326 " str r1, [r2] \n" /* Program MAIR0. */
327 " \n"
328 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
329 " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
330 " \n"
331 " movs r3, #4 \n" /* r3 = 4. */
332 " str r3, [r1] \n" /* Program RNR = 4. */
333 " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
334 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
335 " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
336 " movs r3, #5 \n" /* r3 = 5. */
337 " str r3, [r1] \n" /* Program RNR = 5. */
338 " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
339 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
340 " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
341 " movs r3, #6 \n" /* r3 = 6. */
342 " str r3, [r1] \n" /* Program RNR = 6. */
343 " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
344 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
345 " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
346 " movs r3, #7 \n" /* r3 = 6. */
347 " str r3, [r1] \n" /* Program RNR = 7. */
348 " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
349 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
350 " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
351 " \n"
352 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
353 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
354 " movs r3, #1 \n" /* r3 = 1. */
355 " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
356 " str r2, [r1] \n" /* Enable MPU. */
357 " dsb \n" /* Force memory writes before continuing. */
358 " \n"
359 " restore_context: \n"
360 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
361 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
362 " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
363 " \n"
364 " restore_special_regs: \n"
365 " subs r1, #16 \n"
366 " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
367 " subs r1, #16 \n"
368 " msr psp, r2 \n"
369 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
370 " msr psplim, r3 \n"
371 #endif
372 " msr control, r4 \n"
373 " mov lr, r5 \n"
374 " \n"
375 " restore_general_regs: \n"
376 " subs r1, #32 \n"
377 " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
378 " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
379 " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
380 " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
381 " subs r1, #48 \n"
382 " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
383 " mov r8, r4 \n" /* r8 = r4. */
384 " mov r9, r5 \n" /* r9 = r5. */
385 " mov r10, r6 \n" /* r10 = r6. */
386 " mov r11, r7 \n" /* r11 = r7. */
387 " subs r1, #32 \n"
388 " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
389 " subs r1, #16 \n"
390 " \n"
391 " restore_context_done: \n"
392 " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
393 " bx lr \n"
394 );
395 }
396
397 #else /* configENABLE_MPU */
398
PendSV_Handler(void)399 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
400 {
401 __asm volatile
402 (
403 " .syntax unified \n"
404 " \n"
405 " mrs r0, psp \n" /* Read PSP in r0. */
406 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
407 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
408 " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
409 " str r0, [r1] \n" /* Save the new top of stack in TCB. */
410 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
411 " mrs r2, psplim \n" /* r2 = PSPLIM. */
412 #else
413 " movs r2, #0 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */
414 #endif
415 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
416 " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
417 " mov r4, r8 \n" /* r4 = r8. */
418 " mov r5, r9 \n" /* r5 = r9. */
419 " mov r6, r10 \n" /* r6 = r10. */
420 " mov r7, r11 \n" /* r7 = r11. */
421 " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
422 " \n"
423 " cpsid i \n"
424 " bl vTaskSwitchContext \n"
425 " cpsie i \n"
426 " \n"
427 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
428 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
429 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
430 " \n"
431 " adds r0, r0, #24 \n" /* Move to the high registers. */
432 " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
433 " mov r8, r4 \n" /* r8 = r4. */
434 " mov r9, r5 \n" /* r9 = r5. */
435 " mov r10, r6 \n" /* r10 = r6. */
436 " mov r11, r7 \n" /* r11 = r7. */
437 " msr psp, r0 \n" /* Remember the new top of stack for the task. */
438 " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */
439 " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
440 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
441 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
442 #endif
443 " bx r3 \n"
444 );
445 }
446
447 #endif /* configENABLE_MPU */
448 /*-----------------------------------------------------------*/
449
450 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
451
SVC_Handler(void)452 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
453 {
454 __asm volatile
455 (
456 ".syntax unified \n"
457 ".extern vPortSVCHandler_C \n"
458 ".extern vSystemCallEnter \n"
459 ".extern vSystemCallExit \n"
460 " \n"
461 "movs r0, #4 \n"
462 "mov r1, lr \n"
463 "tst r0, r1 \n"
464 "beq stack_on_msp \n"
465 "stack_on_psp: \n"
466 " mrs r0, psp \n"
467 " b route_svc \n"
468 "stack_on_msp: \n"
469 " mrs r0, msp \n"
470 " b route_svc \n"
471 " \n"
472 "route_svc: \n"
473 " ldr r3, [r0, #24] \n"
474 " subs r3, #2 \n"
475 " ldrb r2, [r3, #0] \n"
476 " cmp r2, %0 \n"
477 " blt system_call_enter \n"
478 " cmp r2, %1 \n"
479 " beq system_call_exit \n"
480 " b vPortSVCHandler_C \n"
481 " \n"
482 "system_call_enter: \n"
483 " b vSystemCallEnter \n"
484 "system_call_exit: \n"
485 " b vSystemCallExit \n"
486 " \n"
487 : /* No outputs. */
488 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
489 : "r0", "r1", "r2", "r3", "memory"
490 );
491 }
492
493 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
494
SVC_Handler(void)495 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
496 {
497 __asm volatile
498 (
499 " .syntax unified \n"
500 " \n"
501 " movs r0, #4 \n"
502 " mov r1, lr \n"
503 " tst r0, r1 \n"
504 " beq stacking_used_msp \n"
505 " mrs r0, psp \n"
506 " ldr r2, =vPortSVCHandler_C \n"
507 " bx r2 \n"
508 " stacking_used_msp: \n"
509 " mrs r0, msp \n"
510 " ldr r2, =vPortSVCHandler_C \n"
511 " bx r2 \n"
512 );
513 }
514
515 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
516 /*-----------------------------------------------------------*/
517
