1 /*
2 * FreeRTOS Kernel V11.0.1
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdint.h>
31
32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
33 * is defined correctly and privileged functions are placed in correct sections. */
34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
35
36 /* Portasm includes. */
37 #include "portasm.h"
38
39 /* System call numbers includes. */
40 #include "mpu_syscall_numbers.h"
41
42 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
43 * header files. */
44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
45
46 #if ( configENABLE_FPU == 1 )
47 #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
48 #endif
49
50 #if ( configENABLE_MPU == 1 )
51
vRestoreContextOfFirstTask(void)52 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
53 {
54 __asm volatile
55 (
56 " .syntax unified \n"
57 " \n"
58 " program_mpu_first_task: \n"
59 " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
60 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
61 " \n"
62 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
63 " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
64 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
65 " movs r3, #1 \n" /* r3 = 1. */
66 " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
67 " str r2, [r1] \n" /* Disable MPU. */
68 " \n"
69 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
70 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
71 " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
72 " str r1, [r2] \n" /* Program MAIR0. */
73 " \n"
74 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
75 " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
76 " \n"
77 " movs r3, #4 \n" /* r3 = 4. */
78 " str r3, [r1] \n" /* Program RNR = 4. */
79 " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
80 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
81 " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
82 " movs r3, #5 \n" /* r3 = 5. */
83 " str r3, [r1] \n" /* Program RNR = 5. */
84 " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
85 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
86 " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
87 " movs r3, #6 \n" /* r3 = 6. */
88 " str r3, [r1] \n" /* Program RNR = 6. */
89 " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
90 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
91 " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
92 " movs r3, #7 \n" /* r3 = 6. */
93 " str r3, [r1] \n" /* Program RNR = 7. */
94 " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
95 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
96 " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
97 " \n"
98 " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
99 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
100 " movs r3, #1 \n" /* r3 = 1. */
101 " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
102 " str r2, [r1] \n" /* Enable MPU. */
103 " dsb \n" /* Force memory writes before continuing. */
104 " \n"
105 " restore_context_first_task: \n"
106 " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
107 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
108 " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
109 " \n"
110 " restore_special_regs_first_task: \n"
111 " subs r1, #16 \n"
112 " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
113 " subs r1, #16 \n"
114 " msr psp, r2 \n"
115 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
116 " msr psplim, r3 \n"
117 #endif
118 " msr control, r4 \n"
119 " mov lr, r5 \n"
120 " \n"
121 " restore_general_regs_first_task: \n"
122 " subs r1, #32 \n"
123 " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
124 " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
125 " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
126 " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
127 " subs r1, #48 \n"
128 " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
129 " mov r8, r4 \n" /* r8 = r4. */
130 " mov r9, r5 \n" /* r9 = r5. */
131 " mov r10, r6 \n" /* r10 = r6. */
132 " mov r11, r7 \n" /* r11 = r7. */
133 " subs r1, #32 \n"
134 " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
135 " subs r1, #16 \n"
136 " \n"
137 " restore_context_done_first_task: \n"
138 " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
139 " bx lr \n"
140 " \n"
141 " .align 4 \n"
142 " pxCurrentTCBConst2: .word pxCurrentTCB \n"
143 " xMPUCTRLConst2: .word 0xe000ed94 \n"
144 " xMAIR0Const2: .word 0xe000edc0 \n"
145 " xRNRConst2: .word 0xe000ed98 \n"
146 " xRBARConst2: .word 0xe000ed9c \n"
147 );
148 }
149
150 #else /* configENABLE_MPU */
151
vRestoreContextOfFirstTask(void)152 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
153 {
154 __asm volatile
155 (
156 " .syntax unified \n"
157 " \n"
158 " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
159 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
160 " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
161 " \n"
162 " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
163 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
164 " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
165 #endif
166 " movs r1, #2 \n" /* r1 = 2. */
167 " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
168 " adds r0, #32 \n" /* Discard everything up to r0. */
169 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
170 " isb \n"
171 " bx r2 \n" /* Finally, branch to EXC_RETURN. */
172 " \n"
173 " .align 4 \n"
174 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
175 );
176 }
177
178 #endif /* configENABLE_MPU */
179 /*-----------------------------------------------------------*/
180
xIsPrivileged(void)181 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
182 {
183 __asm volatile
184 (
185 " .syntax unified \n"
186 " \n"
187 " mrs r0, control \n" /* r0 = CONTROL. */
188 " movs r1, #1 \n" /* r1 = 1. */
189 " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
190 " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */
191 " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
192 " bx lr \n" /* Return. */
193 " running_privileged: \n"
194 " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
195 " bx lr \n" /* Return. */
196 " \n"
197 " .align 4 \n"
198 ::: "r0", "r1", "memory"
199 );
200 }
201 /*-----------------------------------------------------------*/
202
vRaisePrivilege(void)203 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
204 {
205 __asm volatile
206 (
207 " .syntax unified \n"
208 " \n"
209 " mrs r0, control \n" /* Read the CONTROL register. */
210 " movs r1, #1 \n" /* r1 = 1. */
211 " bics r0, r1 \n" /* Clear the bit 0. */
212 " msr control, r0 \n" /* Write back the new CONTROL value. */
213 " bx lr \n" /* Return to the caller. */
214 ::: "r0", "r1", "memory"
215 );
216 }
217 /*-----------------------------------------------------------*/
218
vResetPrivilege(void)219 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
220 {
221 __asm volatile
222 (
223 " .syntax unified \n"
224 " \n"
225 " mrs r0, control \n" /* r0 = CONTROL. */
226 " movs r1, #1 \n" /* r1 = 1. */
227 " orrs r0, r1 \n" /* r0 = r0 | r1. */
228 " msr control, r0 \n" /* CONTROL = r0. */
229 " bx lr \n" /* Return to the caller. */
230 ::: "r0", "r1", "memory"
231 );
232 }
233 /*-----------------------------------------------------------*/
234
vStartFirstTask(void)235 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
236 {
237 __asm volatile
238 (
239 " .syntax unified \n"
240 " \n"
241 " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
242 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
243 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
244 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
245 " cpsie i \n" /* Globally enable interrupts. */
246 " dsb \n"
247 " isb \n"
248 " svc %0 \n" /* System call to start the first task. */
249 " nop \n"
250 " \n"
251 " .align 4 \n"
252 "xVTORConst: .word 0xe000ed08 \n"
253 ::"i" ( portSVC_START_SCHEDULER ) : "memory"
254 );
255 }
256 /*-----------------------------------------------------------*/
257
ulSetInterruptMask(void)258 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
259 {
260 __asm volatile
261 (
262 " .syntax unified \n"
263 " \n"
264 " mrs r0, PRIMASK \n"
265 " cpsid i \n"
266 " bx lr \n"
267 ::: "memory"
268 );
269 }
270 /*-----------------------------------------------------------*/
271
vClearInterruptMask(uint32_t ulMask)272 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
273 {
274 __asm volatile
275 (
276 " .syntax unified \n"
277 " \n"
278 " msr PRIMASK, r0 \n"
279 " bx lr \n"
280 ::: "memory"
281 );
282 }
283 /*-----------------------------------------------------------*/
284
285 #if ( configENABLE_MPU == 1 )
286
PendSV_Handler(void)287 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
288 {
289 __asm volatile
290 (
291 " .syntax unified \n"
292 " \n"
293 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
294 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
295 " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
296 " mrs r2, psp \n" /* r2 = PSP. */
297 " \n"
298 " save_general_regs: \n"
299 " stmia r1!, {r4-r7} \n" /* Store r4-r7. */
300 " mov r4, r8 \n" /* r4 = r8. */
301 " mov r5, r9 \n" /* r5 = r9. */
302 " mov r6, r10 \n" /* r6 = r10. */
303 " mov r7, r11 \n" /* r7 = r11. */
304 " stmia r1!, {r4-r7} \n" /* Store r8-r11. */
305 " ldmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */
306 " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
307 " ldmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */
308 " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */
309 " \n"
310 " save_special_regs: \n"
311 " mrs r2, psp \n" /* r2 = PSP. */
312 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
313 " mrs r3, psplim \n" /* r3 = PSPLIM. */
314 #else
315 " movs r3, #0 \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */
316 #endif
317 " mrs r4, control \n" /* r4 = CONTROL. */
318 " mov r5, lr \n" /* r5 = LR. */
319 " stmia r1!, {r2-r5} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
320 " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
321 " \n"
322 " select_next_task: \n"
323 " cpsid i \n"
324 " bl vTaskSwitchContext \n"
325 " cpsie i \n"
326 " \n"
327 " program_mpu: \n"
328 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
329 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
330 " \n"
331 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
332 " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
333 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
334 " movs r3, #1 \n" /* r3 = 1. */
335 " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
336 " str r2, [r1] \n" /* Disable MPU. */
337 " \n"
338 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
339 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
340 " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
341 " str r1, [r2] \n" /* Program MAIR0. */
342 " \n"
343 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
344 " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
345 " \n"
346 " movs r3, #4 \n" /* r3 = 4. */
347 " str r3, [r1] \n" /* Program RNR = 4. */
348 " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
349 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
350 " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
351 " movs r3, #5 \n" /* r3 = 5. */
352 " str r3, [r1] \n" /* Program RNR = 5. */
353 " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
354 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
355 " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
356 " movs r3, #6 \n" /* r3 = 6. */
357 " str r3, [r1] \n" /* Program RNR = 6. */
358 " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
359 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
360 " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
361 " movs r3, #7 \n" /* r3 = 6. */
362 " str r3, [r1] \n" /* Program RNR = 7. */
363 " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
364 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
365 " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
366 " \n"
367 " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
368 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
369 " movs r3, #1 \n" /* r3 = 1. */
370 " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
371 " str r2, [r1] \n" /* Enable MPU. */
372 " dsb \n" /* Force memory writes before continuing. */
373 " \n"
374 " restore_context: \n"
375 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
376 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
377 " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
378 " \n"
379 " restore_special_regs: \n"
380 " subs r1, #16 \n"
381 " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
382 " subs r1, #16 \n"
383 " msr psp, r2 \n"
384 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
385 " msr psplim, r3 \n"
386 #endif
387 " msr control, r4 \n"
388 " mov lr, r5 \n"
389 " \n"
390 " restore_general_regs: \n"
391 " subs r1, #32 \n"
392 " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
393 " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
394 " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
395 " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
396 " subs r1, #48 \n"
397 " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
398 " mov r8, r4 \n" /* r8 = r4. */
399 " mov r9, r5 \n" /* r9 = r5. */
400 " mov r10, r6 \n" /* r10 = r6. */
401 " mov r11, r7 \n" /* r11 = r7. */
402 " subs r1, #32 \n"
403 " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */
404 " subs r1, #16 \n"
405 " \n"
406 " restore_context_done: \n"
407 " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
408 " bx lr \n"
409 " \n"
410 " .align 4 \n"
411 " pxCurrentTCBConst: .word pxCurrentTCB \n"
412 " xMPUCTRLConst: .word 0xe000ed94 \n"
413 " xMAIR0Const: .word 0xe000edc0 \n"
414 " xRNRConst: .word 0xe000ed98 \n"
415 " xRBARConst: .word 0xe000ed9c \n"
416 );
417 }
418
419 #else /* configENABLE_MPU */
420
PendSV_Handler(void)421 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
422 {
423 __asm volatile
424 (
425 " .syntax unified \n"
426 " \n"
427 " mrs r0, psp \n" /* Read PSP in r0. */
428 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
429 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
430 " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
431 " str r0, [r1] \n" /* Save the new top of stack in TCB. */
432 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
433 " mrs r2, psplim \n" /* r2 = PSPLIM. */
434 #else
435 " movs r2, #0 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */
436 #endif
437 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
438 " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
439 " mov r4, r8 \n" /* r4 = r8. */
440 " mov r5, r9 \n" /* r5 = r9. */
441 " mov r6, r10 \n" /* r6 = r10. */
442 " mov r7, r11 \n" /* r7 = r11. */
443 " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
444 " \n"
445 " cpsid i \n"
446 " bl vTaskSwitchContext \n"
447 " cpsie i \n"
448 " \n"
449 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
450 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
451 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
452 " \n"
453 " adds r0, r0, #24 \n" /* Move to the high registers. */
454 " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
455 " mov r8, r4 \n" /* r8 = r4. */
456 " mov r9, r5 \n" /* r9 = r5. */
457 " mov r10, r6 \n" /* r10 = r6. */
458 " mov r11, r7 \n" /* r11 = r7. */
459 " msr psp, r0 \n" /* Remember the new top of stack for the task. */
460 " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */
461 " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
462 #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
463 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
464 #endif
465 " bx r3 \n"
466 " \n"
467 " .align 4 \n"
468 "pxCurrentTCBConst: .word pxCurrentTCB \n"
469 );
470 }
471
472 #endif /* configENABLE_MPU */
473 /*-----------------------------------------------------------*/
474
475 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
476
SVC_Handler(void)477 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
478 {
479 __asm volatile
480 (
481 ".syntax unified \n"
482 ".extern vPortSVCHandler_C \n"
483 ".extern vSystemCallEnter \n"
484 ".extern vSystemCallExit \n"
485 " \n"
486 "movs r0, #4 \n"
487 "mov r1, lr \n"
488 "tst r0, r1 \n"
489 "beq stack_on_msp \n"
490 "stack_on_psp: \n"
491 " mrs r0, psp \n"
492 " b route_svc \n"
493 "stack_on_msp: \n"
494 " mrs r0, msp \n"
495 " b route_svc \n"
496 " \n"
497 "route_svc: \n"
498 " ldr r3, [r0, #24] \n"
499 " subs r3, #2 \n"
500 " ldrb r2, [r3, #0] \n"
501 " cmp r2, %0 \n"
502 " blt system_call_enter \n"
503 " cmp r2, %1 \n"
504 " beq system_call_exit \n"
505 " b vPortSVCHandler_C \n"
506 " \n"
507 "system_call_enter: \n"
508 " b vSystemCallEnter \n"
509 "system_call_exit: \n"
510 " b vSystemCallExit \n"
511 " \n"
512 : /* No outputs. */
513 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
514 : "r0", "r1", "r2", "r3", "memory"
515 );
516 }
517
518 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
519
SVC_Handler(void)520 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
521 {
522 __asm volatile
523 (
524 " .syntax unified \n"
525 " \n"
526 " movs r0, #4 \n"
527 " mov r1, lr \n"
528 " tst r0, r1 \n"
529 " beq stacking_used_msp \n"
530 " mrs r0, psp \n"
531 " ldr r2, svchandler_address_const \n"
532 " bx r2 \n"
533 " stacking_used_msp: \n"
534 " mrs r0, msp \n"
535 " ldr r2, svchandler_address_const \n"
536 " bx r2 \n"
537 " \n"
538 " .align 4 \n"
539 "svchandler_address_const: .word vPortSVCHandler_C \n"
540 );
541 }
542
543 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
544 /*-----------------------------------------------------------*/
545
