1 /*
2 * FreeRTOS Kernel V11.0.1
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdint.h>
31
32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
33 * is defined correctly and privileged functions are placed in correct sections. */
34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
35
36 /* Portasm includes. */
37 #include "portasm.h"
38
39 /* System call numbers includes. */
40 #include "mpu_syscall_numbers.h"
41
42 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
43 * header files. */
44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
45
46 #if ( configENABLE_FPU == 1 )
47 #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
48 #endif
49
50 #if ( configENABLE_MPU == 1 )
51
vRestoreContextOfFirstTask(void)52 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
53 {
54 __asm volatile
55 (
56 " .syntax unified \n"
57 " \n"
58 " program_mpu_first_task: \n"
59 " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
60 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
61 " \n"
62 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
63 " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
64 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
65 " movs r3, #1 \n" /* r3 = 1. */
66 " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
67 " str r2, [r1] \n" /* Disable MPU. */
68 " \n"
69 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
70 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
71 " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
72 " str r1, [r2] \n" /* Program MAIR0. */
73 " \n"
74 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
75 " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
76 " \n"
77 " movs r3, #4 \n" /* r3 = 4. */
78 " str r3, [r1] \n" /* Program RNR = 4. */
79 " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
80 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
81 " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
82 " movs r3, #5 \n" /* r3 = 5. */
83 " str r3, [r1] \n" /* Program RNR = 5. */
84 " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
85 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
86 " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
87 " movs r3, #6 \n" /* r3 = 6. */
88 " str r3, [r1] \n" /* Program RNR = 6. */
89 " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
90 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
91 " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
92 " movs r3, #7 \n" /* r3 = 6. */
93 " str r3, [r1] \n" /* Program RNR = 7. */
94 " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
95 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
96 " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
97 " \n"
98 " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
99 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
100 " movs r3, #1 \n" /* r3 = 1. */
101 " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
102 " str r2, [r1] \n" /* Enable MPU. */
103 " dsb \n" /* Force memory writes before continuing. */
104 " \n"
105 " restore_context_first_task: \n"
106 " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
107 " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
108 " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
109 " \n"
110 " restore_special_regs_first_task: \n"
111 " subs r2, #20 \n"
112 " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
113 " subs r2, #20 \n"
114 " msr psp, r3 \n"
115 " msr control, r5 \n"
116 " mov lr, r6 \n"
117 " ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
118 " str r0, [r4] \n" /* Restore xSecureContext. */
119 " \n"
120 " restore_general_regs_first_task: \n"
121 " subs r2, #32 \n"
122 " ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
123 " stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
124 " ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
125 " stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
126 " subs r2, #48 \n"
127 " ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */
128 " mov r8, r4 \n" /* r8 = r4. */
129 " mov r9, r5 \n" /* r9 = r5. */
130 " mov r10, r6 \n" /* r10 = r6. */
131 " mov r11, r7 \n" /* r11 = r7. */
132 " subs r2, #32 \n"
133 " ldmia r2!, {r4-r7} \n" /* Restore r4-r7. */
134 " subs r2, #16 \n"
135 " \n"
136 " restore_context_done_first_task: \n"
137 " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
138 " bx lr \n"
139 " \n"
140 " .align 4 \n"
141 " pxCurrentTCBConst2: .word pxCurrentTCB \n"
142 " xSecureContextConst2: .word xSecureContext \n"
143 " xMPUCTRLConst2: .word 0xe000ed94 \n"
144 " xMAIR0Const2: .word 0xe000edc0 \n"
145 " xRNRConst2: .word 0xe000ed98 \n"
146 " xRBARConst2: .word 0xe000ed9c \n"
147 );
148 }
149
150 #else /* configENABLE_MPU */
151
vRestoreContextOfFirstTask(void)152 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
153 {
154 __asm volatile
155 (
156 " .syntax unified \n"
157 " \n"
158 " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
159 " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
160 " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
161 " \n"
162 " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
163 " ldr r4, xSecureContextConst2 \n"
164 " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
165 " movs r1, #2 \n" /* r1 = 2. */
166 " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
167 " adds r0, #32 \n" /* Discard everything up to r0. */
168 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
169 " isb \n"
170 " bx r3 \n" /* Finally, branch to EXC_RETURN. */
171 " \n"
172 " .align 4 \n"
173 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
174 "xSecureContextConst2: .word xSecureContext \n"
175 );
176 }
177
178 #endif /* configENABLE_MPU */
179 /*-----------------------------------------------------------*/
180
xIsPrivileged(void)181 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
182 {
183 __asm volatile
184 (
185 " .syntax unified \n"
186 " \n"
187 " mrs r0, control \n" /* r0 = CONTROL. */
188 " movs r1, #1 \n" /* r1 = 1. */
189 " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
190 " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */
191 " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
192 " bx lr \n" /* Return. */
193 " running_privileged: \n"
194 " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
195 " bx lr \n" /* Return. */
196 " \n"
197 " .align 4 \n"
198 ::: "r0", "r1", "memory"
199 );
200 }
201 /*-----------------------------------------------------------*/
202
vRaisePrivilege(void)203 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
204 {
205 __asm volatile
206 (
207 " .syntax unified \n"
208 " \n"
209 " mrs r0, control \n" /* Read the CONTROL register. */
210 " movs r1, #1 \n" /* r1 = 1. */
211 " bics r0, r1 \n" /* Clear the bit 0. */
212 " msr control, r0 \n" /* Write back the new CONTROL value. */
213 " bx lr \n" /* Return to the caller. */
214 ::: "r0", "r1", "memory"
215 );
216 }
217 /*-----------------------------------------------------------*/
218
vResetPrivilege(void)219 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
220 {
221 __asm volatile
222 (
223 " .syntax unified \n"
224 " \n"
225 " mrs r0, control \n" /* r0 = CONTROL. */
226 " movs r1, #1 \n" /* r1 = 1. */
227 " orrs r0, r1 \n" /* r0 = r0 | r1. */
228 " msr control, r0 \n" /* CONTROL = r0. */
229 " bx lr \n" /* Return to the caller. */
230 ::: "r0", "r1", "memory"
231 );
232 }
233 /*-----------------------------------------------------------*/
234
vStartFirstTask(void)235 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
236 {
237 __asm volatile
238 (
239 " .syntax unified \n"
240 " \n"
241 " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
242 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
243 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
244 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
245 " cpsie i \n" /* Globally enable interrupts. */
246 " dsb \n"
247 " isb \n"
248 " svc %0 \n" /* System call to start the first task. */
249 " nop \n"
250 " \n"
251 " .align 4 \n"
252 "xVTORConst: .word 0xe000ed08 \n"
253 ::"i" ( portSVC_START_SCHEDULER ) : "memory"
254 );
255 }
256 /*-----------------------------------------------------------*/
257
ulSetInterruptMask(void)258 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
259 {
260 __asm volatile
261 (
262 " .syntax unified \n"
263 " \n"
264 " mrs r0, PRIMASK \n"
265 " cpsid i \n"
266 " bx lr \n"
267 ::: "memory"
268 );
269 }
270 /*-----------------------------------------------------------*/
271
vClearInterruptMask(uint32_t ulMask)272 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
273 {
274 __asm volatile
275 (
276 " .syntax unified \n"
277 " \n"
278 " msr PRIMASK, r0 \n"
279 " bx lr \n"
280 ::: "memory"
281 );
282 }
283 /*-----------------------------------------------------------*/
284
285 #if ( configENABLE_MPU == 1 )
286
PendSV_Handler(void)287 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
288 {
289 __asm volatile
290 (
291 " .syntax unified \n"
292 " .extern SecureContext_SaveContext \n"
293 " .extern SecureContext_LoadContext \n"
294 " \n"
295 " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
296 " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
297 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
298 " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
299 " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */
300 " \n"
301 " cbz r0, save_ns_context \n" /* No secure context to save. */
302 " save_s_context: \n"
303 " push {r0-r2, lr} \n"
304 " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
305 " pop {r0-r3} \n" /* LR is now in r3. */
306 " mov lr, r3 \n" /* Restore LR. */
307 " \n"
308 " save_ns_context: \n"
309 " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */
310 " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
311 " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
312 " \n"
313 " save_general_regs: \n"
314 " mrs r3, psp \n"
315 " stmia r2!, {r4-r7} \n" /* Store r4-r7. */
316 " mov r4, r8 \n" /* r4 = r8. */
317 " mov r5, r9 \n" /* r5 = r9. */
318 " mov r6, r10 \n" /* r6 = r10. */
319 " mov r7, r11 \n" /* r7 = r11. */
320 " stmia r2!, {r4-r7} \n" /* Store r8-r11. */
321 " ldmia r3!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */
322 " stmia r2!, {r4-r7} \n" /* Store the hardware saved context. */
323 " ldmia r3!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */
324 " stmia r2!, {r4-r7} \n" /* Store the hardware saved context. */
325 " \n"
326 " save_special_regs: \n"
327 " mrs r3, psp \n" /* r3 = PSP. */
328 " movs r4, #0 \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */
329 " mrs r5, control \n" /* r5 = CONTROL. */
330 " mov r6, lr \n" /* r6 = LR. */
331 " stmia r2!, {r0, r3-r6} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
332 " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
333 " \n"
334 " select_next_task: \n"
335 " cpsid i \n"
336 " bl vTaskSwitchContext \n"
337 " cpsie i \n"
338 " \n"
339 " program_mpu: \n"
340 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
341 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
342 " \n"
343 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
344 " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
345 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
346 " movs r3, #1 \n" /* r3 = 1. */
347 " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
348 " str r2, [r1] \n" /* Disable MPU. */
349 " \n"
350 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
351 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
352 " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
353 " str r1, [r2] \n" /* Program MAIR0. */
354 " \n"
355 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
356 " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */
357 " \n"
358 " movs r3, #4 \n" /* r3 = 4. */
359 " str r3, [r1] \n" /* Program RNR = 4. */
360 " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */
361 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
362 " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */
363 " movs r3, #5 \n" /* r3 = 5. */
364 " str r3, [r1] \n" /* Program RNR = 5. */
365 " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */
366 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
367 " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */
368 " movs r3, #6 \n" /* r3 = 6. */
369 " str r3, [r1] \n" /* Program RNR = 6. */
370 " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */
371 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
372 " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */
373 " movs r3, #7 \n" /* r3 = 6. */
374 " str r3, [r1] \n" /* Program RNR = 7. */
375 " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
376 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
377 " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */
378 " \n"
379 " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
380 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
381 " movs r3, #1 \n" /* r3 = 1. */
382 " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
383 " str r2, [r1] \n" /* Enable MPU. */
384 " dsb \n" /* Force memory writes before continuing. */
385 " \n"
386 " restore_context: \n"
387 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
388 " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
389 " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
390 " \n"
391 " restore_special_regs: \n"
392 " subs r2, #20 \n"
393 " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
394 " subs r2, #20 \n"
395 " msr psp, r3 \n"
396 " msr control, r5 \n"
397 " mov lr, r6 \n"
398 " ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
399 " str r0, [r4] \n" /* Restore xSecureContext. */
400 " cbz r0, restore_ns_context \n" /* No secure context to restore. */
401 " \n"
402 " restore_s_context: \n"
403 " push {r1-r3, lr} \n"
404 " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
405 " pop {r1-r4} \n" /* LR is now in r4. */
406 " mov lr, r4 \n"
407 " \n"
408 " restore_ns_context: \n"
409 " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */
410 " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
411 " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
412 " \n"
413 " restore_general_regs: \n"
414 " subs r2, #32 \n"
415 " ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
416 " stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
417 " ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
418 " stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
419 " subs r2, #48 \n"
420 " ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */
421 " mov r8, r4 \n" /* r8 = r4. */
422 " mov r9, r5 \n" /* r9 = r5. */
423 " mov r10, r6 \n" /* r10 = r6. */
424 " mov r11, r7 \n" /* r11 = r7. */
425 " subs r2, #32 \n"
426 " ldmia r2!, {r4-r7} \n" /* Restore r4-r7. */
427 " subs r2, #16 \n"
428 " \n"
429 " restore_context_done: \n"
430 " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
431 " bx lr \n"
432 " \n"
433 " .align 4 \n"
434 " pxCurrentTCBConst: .word pxCurrentTCB \n"
435 " xSecureContextConst: .word xSecureContext \n"
436 " xMPUCTRLConst: .word 0xe000ed94 \n"
437 " xMAIR0Const: .word 0xe000edc0 \n"
438 " xRNRConst: .word 0xe000ed98 \n"
439 " xRBARConst: .word 0xe000ed9c \n"
440 );
441 }
442
443 #else /* configENABLE_MPU */
444
PendSV_Handler(void)445 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
446 {
447 __asm volatile
448 (
449 " .syntax unified \n"
450 " .extern SecureContext_SaveContext \n"
451 " .extern SecureContext_LoadContext \n"
452 " \n"
453 " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
454 " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
455 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
456 " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
457 " mrs r2, psp \n" /* Read PSP in r2. */
458 " \n"
459 " cbz r0, save_ns_context \n" /* No secure context to save. */
460 " push {r0-r2, r14} \n"
461 " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
462 " pop {r0-r3} \n" /* LR is now in r3. */
463 " mov lr, r3 \n" /* LR = r3. */
464 " lsls r1, r3, #25 \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
465 " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
466 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
467 " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
468 " subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
469 " str r2, [r1] \n" /* Save the new top of stack in TCB. */
470 " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
471 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
472 " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
473 " b select_next_task \n"
474 " \n"
475 " save_ns_context: \n"
476 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
477 " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
478 " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
479 " str r2, [r1] \n" /* Save the new top of stack in TCB. */
480 " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
481 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
482 " stmia r2!, {r0, r1, r3-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
483 " mov r4, r8 \n" /* r4 = r8. */
484 " mov r5, r9 \n" /* r5 = r9. */
485 " mov r6, r10 \n" /* r6 = r10. */
486 " mov r7, r11 \n" /* r7 = r11. */
487 " stmia r2!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
488 " \n"
489 " select_next_task: \n"
490 " cpsid i \n"
491 " bl vTaskSwitchContext \n"
492 " cpsie i \n"
493 " \n"
494 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
495 " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
496 " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
497 " \n"
498 " ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
499 " mov lr, r4 \n" /* LR = r4. */
500 " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
501 " str r0, [r3] \n" /* Restore the task's xSecureContext. */
502 " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
503 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
504 " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
505 " push {r2, r4} \n"
506 " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
507 " pop {r2, r4} \n"
508 " mov lr, r4 \n" /* LR = r4. */
509 " lsls r1, r4, #25 \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
510 " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
511 " msr psp, r2 \n" /* Remember the new top of stack for the task. */
512 " bx lr \n"
513 " \n"
514 " restore_ns_context: \n"
515 " adds r2, r2, #16 \n" /* Move to the high registers. */
516 " ldmia r2!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
517 " mov r8, r4 \n" /* r8 = r4. */
518 " mov r9, r5 \n" /* r9 = r5. */
519 " mov r10, r6 \n" /* r10 = r6. */
520 " mov r11, r7 \n" /* r11 = r7. */
521 " msr psp, r2 \n" /* Remember the new top of stack for the task. */
522 " subs r2, r2, #32 \n" /* Go back to the low registers. */
523 " ldmia r2!, {r4-r7} \n" /* Restore the low registers that are not automatically restored. */
524 " bx lr \n"
525 " \n"
526 " .align 4 \n"
527 "pxCurrentTCBConst: .word pxCurrentTCB \n"
528 "xSecureContextConst: .word xSecureContext \n"
529 );
530 }
531
532 #endif /* configENABLE_MPU */
533 /*-----------------------------------------------------------*/
534
535 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
536
SVC_Handler(void)537 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
538 {
539 __asm volatile
540 (
541 ".syntax unified \n"
542 ".extern vPortSVCHandler_C \n"
543 ".extern vSystemCallEnter \n"
544 ".extern vSystemCallExit \n"
545 " \n"
546 "movs r0, #4 \n"
547 "mov r1, lr \n"
548 "tst r0, r1 \n"
549 "beq stack_on_msp \n"
550 "stack_on_psp: \n"
551 " mrs r0, psp \n"
552 " b route_svc \n"
553 "stack_on_msp: \n"
554 " mrs r0, msp \n"
555 " b route_svc \n"
556 " \n"
557 "route_svc: \n"
558 " ldr r3, [r0, #24] \n"
559 " subs r3, #2 \n"
560 " ldrb r2, [r3, #0] \n"
561 " cmp r2, %0 \n"
562 " blt system_call_enter \n"
563 " cmp r2, %1 \n"
564 " beq system_call_exit \n"
565 " b vPortSVCHandler_C \n"
566 " \n"
567 "system_call_enter: \n"
568 " b vSystemCallEnter \n"
569 "system_call_exit: \n"
570 " b vSystemCallExit \n"
571 " \n"
572 : /* No outputs. */
573 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
574 : "r0", "r1", "r2", "r3", "memory"
575 );
576 }
577
578 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
579
SVC_Handler(void)580 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
581 {
582 __asm volatile
583 (
584 " .syntax unified \n"
585 " \n"
586 " movs r0, #4 \n"
587 " mov r1, lr \n"
588 " tst r0, r1 \n"
589 " beq stacking_used_msp \n"
590 " mrs r0, psp \n"
591 " ldr r2, svchandler_address_const \n"
592 " bx r2 \n"
593 " stacking_used_msp: \n"
594 " mrs r0, msp \n"
595 " ldr r2, svchandler_address_const \n"
596 " bx r2 \n"
597 " \n"
598 " .align 4 \n"
599 "svchandler_address_const: .word vPortSVCHandler_C \n"
600 );
601 }
602
603 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
604 /*-----------------------------------------------------------*/
605
vPortAllocateSecureContext(uint32_t ulSecureStackSize)606 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
607 {
608 __asm volatile
609 (
610 " .syntax unified \n"
611 " \n"
612 " svc %0 \n" /* Secure context is allocated in the supervisor call. */
613 " bx lr \n" /* Return. */
614 ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
615 );
616 }
617 /*-----------------------------------------------------------*/
618
vPortFreeSecureContext(uint32_t * pulTCB)619 void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
620 {
621 __asm volatile
622 (
623 " .syntax unified \n"
624 " \n"
625 " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */
626 " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */
627 " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */
628 " bne free_secure_context \n" /* Branch if r1 != 0. */
629 " bx lr \n" /* There is no secure context (xSecureContext is NULL). */
630 " free_secure_context: \n"
631 " svc %0 \n" /* Secure context is freed in the supervisor call. */
632 " bx lr \n" /* Return. */
633 ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
634 );
635 }
636 /*-----------------------------------------------------------*/
637
