1 /*
2  * FreeRTOS Kernel V10.6.2
3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
4  *
5  * SPDX-License-Identifier: MIT
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy of
8  * this software and associated documentation files (the "Software"), to deal in
9  * the Software without restriction, including without limitation the rights to
10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11  * the Software, and to permit persons to whom the Software is furnished to do so,
12  * subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in all
15  * copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * https://www.FreeRTOS.org
25  * https://github.com/FreeRTOS
26  *
27  */
28 
29 /*
30  * The FreeRTOS kernel's RISC-V port is split between the the code that is
31  * common across all currently supported RISC-V chips (implementations of the
32  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
33  *
34  * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
35  *   is common to all currently supported RISC-V chips.  There is only one
36  *   portASM.S file because the same file is built for all RISC-V target chips.
37  *
38  * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
39  *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
40  *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
41  *   as there are multiple RISC-V chip implementations.
42  *
43  * !!!NOTE!!!
44  * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
45  * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
46  * compiler's!) include path.  For example, if the chip in use includes a core
47  * local interrupter (CLINT) and does not include any chip specific register
48  * extensions then add the path below to the assembler's include path:
49  * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
50  *
51  */
52 
53 /*
54  * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy
55  * devices, developed and tested using the Vega board RV32M1RM.
56  */
57 
58 #ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
59 #define __FREERTOS_RISC_V_EXTENSIONS_H__
60 
61 #define portasmHAS_MTIME 0
62 
63 /* Constants to define the additional registers found on the Pulpino RI5KY. */
64 #define lpstart0    0x7b0
65 #define lpend0      0x7b1
66 #define lpcount0    0x7b2
67 #define lpstart1    0x7b4
68 #define lpend1      0x7b5
69 #define lpcount1    0x7b6
70 
71 /* Six additional registers to save and restore, as per the #defines above. */
72 #define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
73 
74 /* Save additional registers found on the Pulpino. */
75 .macro portasmSAVE_ADDITIONAL_REGISTERS
76     addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
77     csrr t0, lpstart0                            /* Load additional registers into accessible temporary registers. */
78     csrr t1, lpend0
79     csrr t2, lpcount0
80     csrr t3, lpstart1
81     csrr t4, lpend1
82     csrr t5, lpcount1
83     sw t0, 1 * portWORD_SIZE( sp )
84     sw t1, 2 * portWORD_SIZE( sp )
85     sw t2, 3 * portWORD_SIZE( sp )
86     sw t3, 4 * portWORD_SIZE( sp )
87     sw t4, 5 * portWORD_SIZE( sp )
88     sw t5, 6 * portWORD_SIZE( sp )
89     .endm
90 
91 /* Restore the additional registers found on the Pulpino. */
92 .macro portasmRESTORE_ADDITIONAL_REGISTERS
93     lw t0, 1 * portWORD_SIZE( sp )          /* Load additional registers into accessible temporary registers. */
94     lw t1, 2 * portWORD_SIZE( sp )
95     lw t2, 3 * portWORD_SIZE( sp )
96     lw t3, 4 * portWORD_SIZE( sp )
97     lw t4, 5 * portWORD_SIZE( sp )
98     lw t5, 6 * portWORD_SIZE( sp )
99     csrw lpstart0, t0
100     csrw lpend0, t1
101     csrw lpcount0, t2
102     csrw lpstart1, t3
103     csrw lpend1, t4
104     csrw lpcount1, t5
105     addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
106     .endm
107 
108 #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
109