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/Kernel-v11.1.0/.github/workflows/
Dauto-release.yml60 pip install -r ./tools/.github/scripts/release-requirements.txt
96 pip install -r ./tools/.github/scripts/release-requirements.txt
Dkernel-checks.yml54 pip install -r inspect/.github/scripts/common/requirements.txt
/Kernel-v11.1.0/portable/ThirdParty/XCC/Xtensa/
Dreadme_xtensa.txt17 Xtensa Configuration Requirements and Restrictions
23 requirements. You must use Xtensa Tools to compile and link FreeRTOS and
53 All Diamond processor cores meet these requirements and are supported.
312 basis for each task's stack size. They are minimum requirements taking
337 FreeRTOSConfig.h. Define this carefully to match your system requirements.
Dxtensa_config.h56 * STACK REQUIREMENTS
Dxtensa_rtos.h106 Check some Xtensa configuration requirements and report error if not met.
/Kernel-v11.1.0/portable/ARMv8M/secure/macros/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/IAR/ARM_CM23/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/GCC/ARM_CM55/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/IAR/ARM_CM85/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/GCC/ARM_CM23/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/IAR/ARM_CM55/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/IAR/ARM_CM35P/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/IAR/ARM_CM33/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/GCC/ARM_CM35P/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/GCC/ARM_CM85/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/portable/GCC/ARM_CM33/secure/
Dsecure_port_macros.h33 * @brief Byte alignment requirements.
/Kernel-v11.1.0/
DMISRA.md92 architecture alignment requirements specified by portBYTE_ALIGNMENT.
/Kernel-v11.1.0/include/
DFreeRTOS.h3080 * that are guaranteed to have the same size and alignment requirements of the
3133 * below is provided for this purpose. Its sizes and alignment requirements are
3207 * requirements are guaranteed to match those of the genuine structure, no
3250 * Its sizes and alignment requirements are guaranteed to match those of the
3278 * and alignment requirements are guaranteed to match those of the genuine
3305 * purpose. Its size and alignment requirements are guaranteed to match those
/Kernel-v11.1.0/portable/ThirdParty/GCC/ATmega/
Dreadme.md67 …AM__ the user will need to tune the location of stack and heap according to their own requirements.
/Kernel-v11.1.0/portable/ThirdParty/GCC/Posix/
Dport.c381 * to adjust timing according to full demo requirements */
437 * Comment code to adjust timing according to full demo requirements in vPortSystemTickHandler()
/Kernel-v11.1.0/portable/IAR/RISC-V/
Dportmacro.h88 …BYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements. */
/Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/include/
Dxtensa_config.h60 * STACK REQUIREMENTS
Dxtensa_rtos.h110 * Check some Xtensa configuration requirements and report error if not met.
/Kernel-v11.1.0/portable/GCC/RISC-V/
Dportmacro.h86 … portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements */
/Kernel-v11.1.0/portable/GCC/ARM_CRx_MPU/
Dportmacro.h175 * @brief Specifies stack pointer alignment requirements of the target CPU.

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