Searched +full:fail +full:- +full:on +full:- +full:incorrect +full:- +full:version (Results 1 – 9 of 9) sorted by relevance
| /Kernel-v11.1.0/.github/workflows/ |
| D | ci.yml | 2 on:
10 runs-on: ubuntu-20.04
12 - uses: actions/checkout@v4.1.1
13 - name: Check Formatting of FreeRTOS-Kernel Files
14 uses: FreeRTOS/CI-CD-Github-Actions/formatting@main
16 exclude-dirs: portable
18 spell-check:
19 runs-on: ubuntu-latest
21 - name: Clone This Repo
23 - name: Run spellings check
[all …]
|
| /Kernel-v11.1.0/portable/IAR/ARM_CM7/r0p1/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
45 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
96 /* The systick is a 24-bit counter. */
104 /* For strict compliance with the Cortex-M spec the task start address should
105 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
138 * Turn the VFP on.
152 /*-----------------------------------------------------------*/
192 /*-----------------------------------------------------------*/
[all …]
|
| /Kernel-v11.1.0/portable/IAR/ARM_CM3/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
41 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
87 /* The systick is a 24-bit counter. */
95 /* For strict compliance with the Cortex-M spec the task start address should
96 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
138 /*-----------------------------------------------------------*/
178 /*-----------------------------------------------------------*/
189 …pxTopOfStack--; /* Offset added to account fo… in pxPortInitialiseStack()
[all …]
|
| /Kernel-v11.1.0/portable/IAR/ARM_CM4F/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
45 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
66 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
102 /* The systick is a 24-bit counter. */
110 /* For strict compliance with the Cortex-M spec the task start address should
111 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
144 * Turn the VFP on.
158 /*-----------------------------------------------------------*/
[all …]
|
| /Kernel-v11.1.0/portable/GCC/ARM_CM3/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
80 /* The systick is a 24-bit counter. */
88 /* For strict compliance with the Cortex-M spec the task start address should
89 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
104 /* Let the user override the pre-loading of the initial LR with the address of
137 /*-----------------------------------------------------------*/
177 /*-----------------------------------------------------------*/
188 …pxTopOfStack--; /* Offset added to account fo… in pxPortInitialiseStack()
[all …]
|
| /Kernel-v11.1.0/ |
| D | History.txt | 5 + Add ARMv7-R port with Memory Protection Unit (MPU) support.
6 + Add Memory Protection Unit (MPU) support to the Cortex-M0 port.
8 buffer when a task reads from a non-empty buffer:
9 - The task reading from a non-empty stream buffer returns immediately
11 - The task reading from a non-empty steam batching buffer blocks until the
37 + Add 64-bit support to the FreeRTOS Windows Simulator port. We thank @watsk
39 + Add support for 64-bit Microblaze processor to the MicroblazeV9 port. We
43 compilers. We thank @Forty-Bot for their contribution.
44 + Update xPortIsAuthorizedToAccessBuffer() on FreeRTOS ports with MPU
54 POSIX timers to address issues with signal handling in non-FreeRTOS
[all …]
|
| /Kernel-v11.1.0/portable/GCC/ARM_CM4F/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
59 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
95 /* The systick is a 24-bit counter. */
98 /* For strict compliance with the Cortex-M spec the task start address should
99 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
119 /* Let the user override the pre-loading of the initial LR with the address of
157 /*-----------------------------------------------------------*/
197 /*-----------------------------------------------------------*/
[all …]
|
| /Kernel-v11.1.0/portable/GCC/ARM_CM7/r0p1/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
89 /* The systick is a 24-bit counter. */
92 /* For strict compliance with the Cortex-M spec the task start address should
93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
113 /* Let the user override the pre-loading of the initial LR with the address of
151 /*-----------------------------------------------------------*/
191 /*-----------------------------------------------------------*/
203 /* Offset added to account for the way the MCU uses the stack on entry/exit in pxPortInitialiseStack()
[all …]
|
| /Kernel-v11.1.0/portable/IAR/ARM_CM4F_MPU/ |
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
53 …LL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
105 /* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
152 /* The systick is a 24-bit counter. */
160 /* For strict compliance with the Cortex-M spec the task start address should
161 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
176 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
177 /*-----------------------------------------------------------*/
[all …]
|
