Searched full:64 (Results 1 – 25 of 62) sorted by relevance
123
| /Kernel-v11.1.0/portable/ThirdParty/CDK/T-HEAD_CK802/ |
| D | portasm.S | 39 ldw r0, (sp, 64)
62 stw r15, (sp, 64)
73 ldw r0, (sp, 64)
97 stw r0, (sp, 64)
120 ldw r0, (sp, 64)
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| /Kernel-v11.1.0/portable/GCC/ARM_AARCH64/ |
| D | README.md | 3 The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
5 Execution state supports the A64 instruction set. It holds addresses in 64-bit
6 registers and allows instructions in the base instruction set to use 64-bit
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| /Kernel-v11.1.0/portable/GCC/ARM_AARCH64_SRE/ |
| D | README.md | 3 The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
5 Execution state supports the A64 instruction set. It holds addresses in 64-bit
6 registers and allows instructions in the base instruction set to use 64-bit
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| /Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/include/ |
| D | xt_asm_utils.h | 52 #if XCHAL_NUM_AREGS == 64
70 #else /* if XCHAL_NUM_AREGS == 64 */
72 #endif /* if XCHAL_NUM_AREGS == 64 */
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| /Kernel-v11.1.0/portable/WizC/PIC18/ |
| D | port.c | 35 an error on devices with more than 64kB ROM.
68 * sfr's within parenthesis only on devices > 64kB
71 * 2 bytes per entry on devices <= 64kB
72 * 3 bytes per entry on devices > 64kB
175 * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the in pxPortInitialiseStack()
177 * functionpointers to point above 64kB in ROM. in pxPortInitialiseStack()
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| /Kernel-v11.1.0/portable/IAR/V850ES/ |
| D | ISR_Support.h | 57 sst.w r17, 64[ ep ]
77 sst.w r18, 64[ ep ]
136 sld.w 64[ ep ], r17
156 sld.w 64[ ep ], r18
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| D | portasm.s85 | 79 sst.w r17,64[ep]
96 sst.w r18,64[ep]
153 sld.w 64[ep],r17
171 sld.w 64[ep],r18
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| D | portasm_Hx2.s85 | 79 sst.w r17,64[ep]
96 sst.w r18,64[ep]
153 sld.w 64[ep],r17
171 sld.w 64[ep],r18
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| D | portasm_Fx3.s85 | 88 sst.w r17,64[ep]
105 sst.w r18,64[ep]
162 sld.w 64[ep],r17
180 sld.w 64[ep],r18
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| /Kernel-v11.1.0/portable/IAR/RISC-V/ |
| D | portASM.s | 99 …EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit c…
115 /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
131 #if( __riscv_xlen == 64 )
133 /* Update the 64-bit mtimer compare match value. */
140 #endif /* __riscv_xlen == 64 */
370 …scv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
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| D | portmacro.h | 52 #if __riscv_xlen == 64
63 #else /* if __riscv_xlen == 64 */
65 #endif /* if __riscv_xlen == 64 */
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| /Kernel-v11.1.0/portable/GCC/RISC-V/ |
| D | portASM.S | 93 .extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit c…
106 /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
122 #if( __riscv_xlen == 64 )
124 /* Update the 64-bit mtimer compare match value. */
131 #endif /* __riscv_xlen == 64 */
355 …scv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
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| D | portmacro.h | 50 #if __riscv_xlen == 64
61 #else /* if __riscv_xlen == 64 */
63 #endif /* if __riscv_xlen == 64 */
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| /Kernel-v11.1.0/portable/GCC/PPC440_Xilinx/ |
| D | portasm.S | 204 stfd f8, 64(r3)
253 stfs f16, 64(r3)
310 lfd f8, 64(r3)
360 lfs f16, 64(r3)
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| /Kernel-v11.1.0/portable/GCC/PPC405_Xilinx/ |
| D | portasm.S | 204 stfd f8, 64(r3)
253 stfs f16, 64(r3)
310 lfd f8, 64(r3)
360 lfs f16, 64(r3)
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| /Kernel-v11.1.0/portable/MSVC-MingW/ |
| D | portmacro.h | 75 /* 32-bit tick type on a 32/64-bit architecture, so reads of the tick
83 /* 64-bit tick type on a 64-bit architecture, so reads of the tick
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| /Kernel-v11.1.0/portable/MPLAB/PIC32MZ/ |
| D | ISR_Support.h | 67 sdc1 $f8, \offset + 64(\base)
93 ldc1 $f8, \offset + 64(\base)
213 sw a1, 64(s5)
345 lw a1, 64(s5)
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| D | port_asm.S | 218 sw a1, 64(s5)
366 lw a1, 64(s5)
480 sw a1, 64(s5)
602 lw a1, 64(s5)
735 sdc1 $f8, 64(a0)
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| /Kernel-v11.1.0/portable/GCC/NiosII/ |
| D | port_asm.S | 58 stw r15, 64(sp)
107 ldw r15, 64(sp)
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| /Kernel-v11.1.0/portable/GCC/MicroBlaze/ |
| D | portasm.s | 60 swi r17, r1, 64
103 lwi r17, r1, 64
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| /Kernel-v11.1.0/portable/MPLAB/PIC32MX/ |
| D | ISR_Support.h | 99 sw a1, 64(s5)
150 lw a1, 64(s5)
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| D | port_asm.S | 141 sw a1, 64(s5)
222 lw a1, 64(s5)
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| /Kernel-v11.1.0/portable/MPLAB/PIC32MEC14xx/ |
| D | ISR_Support.h | 117 sw a1, 64(s5)
171 lw a1, 64(s5)
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| /Kernel-v11.1.0/portable/GCC/CORTUS_APS3/ |
| D | portmacro.h | 121 …"st r3, [r1]+ 64 \n" /* Store the interrupt mask on the stack. */ …
133 …"ld r3, [r1] + 64 \n" /* Load the previous interrupt mask. */ …
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| /Kernel-v11.1.0/portable/GCC/MicroBlazeV9/ |
| D | portasm.S | 66 #define portR24_OFFSET 64
108 #define portR16_OFFSET 64
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